VADDPS (ZMM, ZMM, ZMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 74 48 58 c2    	vaddps zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.67
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 74 48 58 c2    	vaddps zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.71
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 74 48 58 c2    	vaddps zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.71
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 74 48 58 c2    	vaddps zmm0,zmm1,zmm2
   6:	62 f1 74 48 58 da    	vaddps zmm3,zmm1,zmm2
   c:	62 f1 74 48 58 e2    	vaddps zmm4,zmm1,zmm2
  12:	62 f1 74 48 58 ea    	vaddps zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.76
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 74 48 58 c2    	vaddps zmm0,zmm1,zmm2
   6:	62 f1 74 48 58 da    	vaddps zmm3,zmm1,zmm2
   c:	62 f1 74 48 58 e2    	vaddps zmm4,zmm1,zmm2
  12:	62 f1 74 48 58 ea    	vaddps zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 2.86
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 74 48 58 c2    	vaddps zmm0,zmm1,zmm2
   6:	62 f1 74 48 58 da    	vaddps zmm3,zmm1,zmm2
   c:	62 f1 74 48 58 e2    	vaddps zmm4,zmm1,zmm2
  12:	62 f1 74 48 58 ea    	vaddps zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 2.88
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 74 48 58 c2    	vaddps zmm0,zmm1,zmm2
   6:	62 f1 74 48 58 da    	vaddps zmm3,zmm1,zmm2
   c:	62 f1 74 48 58 e2    	vaddps zmm4,zmm1,zmm2
  12:	62 f1 74 48 58 ea    	vaddps zmm5,zmm1,zmm2
  18:	62 f1 74 48 58 f2    	vaddps zmm6,zmm1,zmm2
  1e:	62 f1 74 48 58 fa    	vaddps zmm7,zmm1,zmm2
  24:	62 71 74 48 58 c2    	vaddps zmm8,zmm1,zmm2
  2a:	62 71 74 48 58 ca    	vaddps zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 5.67
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 74 48 58 c2    	vaddps zmm0,zmm1,zmm2
   6:	62 f1 74 48 58 da    	vaddps zmm3,zmm1,zmm2
   c:	62 f1 74 48 58 e2    	vaddps zmm4,zmm1,zmm2
  12:	62 f1 74 48 58 ea    	vaddps zmm5,zmm1,zmm2
  18:	62 f1 74 48 58 f2    	vaddps zmm6,zmm1,zmm2
  1e:	62 f1 74 48 58 fa    	vaddps zmm7,zmm1,zmm2
  24:	62 71 74 48 58 c2    	vaddps zmm8,zmm1,zmm2
  2a:	62 71 74 48 58 ca    	vaddps zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 5.72
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 74 48 58 c2    	vaddps zmm0,zmm1,zmm2
   6:	62 f1 74 48 58 da    	vaddps zmm3,zmm1,zmm2
   c:	62 f1 74 48 58 e2    	vaddps zmm4,zmm1,zmm2
  12:	62 f1 74 48 58 ea    	vaddps zmm5,zmm1,zmm2
  18:	62 f1 74 48 58 f2    	vaddps zmm6,zmm1,zmm2
  1e:	62 f1 74 48 58 fa    	vaddps zmm7,zmm1,zmm2
  24:	62 71 74 48 58 c2    	vaddps zmm8,zmm1,zmm2
  2a:	62 71 74 48 58 ca    	vaddps zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 5.54
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.11
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 74 48 58 c2    	vaddps zmm0,zmm1,zmm2
   6:	62 f1 74 48 58 da    	vaddps zmm3,zmm1,zmm2
   c:	62 f1 74 48 58 e2    	vaddps zmm4,zmm1,zmm2
  12:	62 f1 74 48 58 ea    	vaddps zmm5,zmm1,zmm2
  18:	62 f1 74 48 58 f2    	vaddps zmm6,zmm1,zmm2
  1e:	62 f1 74 48 58 fa    	vaddps zmm7,zmm1,zmm2
  24:	62 71 74 48 58 c2    	vaddps zmm8,zmm1,zmm2
  2a:	62 71 74 48 58 ca    	vaddps zmm9,zmm1,zmm2
  30:	62 71 74 48 58 d2    	vaddps zmm10,zmm1,zmm2
  36:	62 71 74 48 58 da    	vaddps zmm11,zmm1,zmm2
  3c:	62 71 74 48 58 e2    	vaddps zmm12,zmm1,zmm2
  42:	62 e1 74 48 58 c2    	vaddps zmm16,zmm1,zmm2
  48:	62 e1 74 48 58 ca    	vaddps zmm17,zmm1,zmm2
  4e:	62 e1 74 48 58 d2    	vaddps zmm18,zmm1,zmm2
  54:	62 e1 74 48 58 da    	vaddps zmm19,zmm1,zmm2
  5a:	62 e1 74 48 58 e2    	vaddps zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 10.89
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 74 48 58 c2    	vaddps zmm0,zmm1,zmm2
   6:	62 f1 74 48 58 da    	vaddps zmm3,zmm1,zmm2
   c:	62 f1 74 48 58 e2    	vaddps zmm4,zmm1,zmm2
  12:	62 f1 74 48 58 ea    	vaddps zmm5,zmm1,zmm2
  18:	62 f1 74 48 58 f2    	vaddps zmm6,zmm1,zmm2
  1e:	62 f1 74 48 58 fa    	vaddps zmm7,zmm1,zmm2
  24:	62 71 74 48 58 c2    	vaddps zmm8,zmm1,zmm2
  2a:	62 71 74 48 58 ca    	vaddps zmm9,zmm1,zmm2
  30:	62 71 74 48 58 d2    	vaddps zmm10,zmm1,zmm2
  36:	62 71 74 48 58 da    	vaddps zmm11,zmm1,zmm2
  3c:	62 71 74 48 58 e2    	vaddps zmm12,zmm1,zmm2
  42:	62 e1 74 48 58 c2    	vaddps zmm16,zmm1,zmm2
  48:	62 e1 74 48 58 ca    	vaddps zmm17,zmm1,zmm2
  4e:	62 e1 74 48 58 d2    	vaddps zmm18,zmm1,zmm2
  54:	62 e1 74 48 58 da    	vaddps zmm19,zmm1,zmm2
  5a:	62 e1 74 48 58 e2    	vaddps zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 11.33
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 74 48 58 c2    	vaddps zmm0,zmm1,zmm2
   6:	62 f1 74 48 58 da    	vaddps zmm3,zmm1,zmm2
   c:	62 f1 74 48 58 e2    	vaddps zmm4,zmm1,zmm2
  12:	62 f1 74 48 58 ea    	vaddps zmm5,zmm1,zmm2
  18:	62 f1 74 48 58 f2    	vaddps zmm6,zmm1,zmm2
  1e:	62 f1 74 48 58 fa    	vaddps zmm7,zmm1,zmm2
  24:	62 71 74 48 58 c2    	vaddps zmm8,zmm1,zmm2
  2a:	62 71 74 48 58 ca    	vaddps zmm9,zmm1,zmm2
  30:	62 71 74 48 58 d2    	vaddps zmm10,zmm1,zmm2
  36:	62 71 74 48 58 da    	vaddps zmm11,zmm1,zmm2
  3c:	62 71 74 48 58 e2    	vaddps zmm12,zmm1,zmm2
  42:	62 e1 74 48 58 c2    	vaddps zmm16,zmm1,zmm2
  48:	62 e1 74 48 58 ca    	vaddps zmm17,zmm1,zmm2
  4e:	62 e1 74 48 58 d2    	vaddps zmm18,zmm1,zmm2
  54:	62 e1 74 48 58 da    	vaddps zmm19,zmm1,zmm2
  5a:	62 e1 74 48 58 e2    	vaddps zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.01
- Reference cycles: 11.41
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.06

With the same register for for different operands

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 7c 48 58 c0    	vaddps zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.82
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 7c 48 58 c0    	vaddps zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 2.86
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 7c 48 58 c0    	vaddps zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.0
- Reference cycles: 2.86
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

VADDPS (ZMM, ZMM, ZMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100