CRC32 (R64, R64)

With unroll_count=500 and no inner loop

Code:

   0:	f2 4d 0f 38 f1 c1    	crc32  r8,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 2.05
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	f2 4d 0f 38 f1 c1    	crc32  r8,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.0
- Reference cycles: 2.07
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	f2 4d 0f 38 f1 c1    	crc32  r8,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.0
- Reference cycles: 2.08
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	f2 4d 0f 38 f1 c1    	crc32  r8,r9
   6:	f2 4d 0f 38 f1 d1    	crc32  r10,r9
   c:	f2 4d 0f 38 f1 d9    	crc32  r11,r9
  12:	f2 4d 0f 38 f1 e1    	crc32  r12,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.76
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	f2 4d 0f 38 f1 c1    	crc32  r8,r9
   6:	f2 4d 0f 38 f1 d1    	crc32  r10,r9
   c:	f2 4d 0f 38 f1 d9    	crc32  r11,r9
  12:	f2 4d 0f 38 f1 e1    	crc32  r12,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 2.76
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	f2 4d 0f 38 f1 c1    	crc32  r8,r9
   6:	f2 4d 0f 38 f1 d1    	crc32  r10,r9
   c:	f2 4d 0f 38 f1 d9    	crc32  r11,r9
  12:	f2 4d 0f 38 f1 e1    	crc32  r12,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 2.75
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f2 4d 0f 38 f1 c1    	crc32  r8,r9
   6:	f2 4d 0f 38 f1 d1    	crc32  r10,r9
   c:	f2 4d 0f 38 f1 d9    	crc32  r11,r9
  12:	f2 4d 0f 38 f1 e1    	crc32  r12,r9
  18:	f2 4d 0f 38 f1 e9    	crc32  r13,r9
  1e:	f2 4d 0f 38 f1 f1    	crc32  r14,r9
  24:	f2 49 0f 38 f1 d9    	crc32  rbx,r9
  2a:	f2 49 0f 38 f1 c9    	crc32  rcx,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 4.91
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	f2 4d 0f 38 f1 c1    	crc32  r8,r9
   6:	f2 4d 0f 38 f1 d1    	crc32  r10,r9
   c:	f2 4d 0f 38 f1 d9    	crc32  r11,r9
  12:	f2 4d 0f 38 f1 e1    	crc32  r12,r9
  18:	f2 4d 0f 38 f1 e9    	crc32  r13,r9
  1e:	f2 4d 0f 38 f1 f1    	crc32  r14,r9
  24:	f2 49 0f 38 f1 d9    	crc32  rbx,r9
  2a:	f2 49 0f 38 f1 c9    	crc32  rcx,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 5.61
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	f2 4d 0f 38 f1 c1    	crc32  r8,r9
   6:	f2 4d 0f 38 f1 d1    	crc32  r10,r9
   c:	f2 4d 0f 38 f1 d9    	crc32  r11,r9
  12:	f2 4d 0f 38 f1 e1    	crc32  r12,r9
  18:	f2 4d 0f 38 f1 e9    	crc32  r13,r9
  1e:	f2 4d 0f 38 f1 f1    	crc32  r14,r9
  24:	f2 49 0f 38 f1 d9    	crc32  rbx,r9
  2a:	f2 49 0f 38 f1 c9    	crc32  rcx,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 5.58
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.11
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 12 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f2 4d 0f 38 f1 c1    	crc32  r8,r9
   6:	f2 4d 0f 38 f1 d1    	crc32  r10,r9
   c:	f2 4d 0f 38 f1 d9    	crc32  r11,r9
  12:	f2 4d 0f 38 f1 e1    	crc32  r12,r9
  18:	f2 4d 0f 38 f1 e9    	crc32  r13,r9
  1e:	f2 4d 0f 38 f1 f1    	crc32  r14,r9
  24:	f2 49 0f 38 f1 d9    	crc32  rbx,r9
  2a:	f2 49 0f 38 f1 c9    	crc32  rcx,r9
  30:	f2 49 0f 38 f1 d1    	crc32  rdx,r9
  36:	f2 49 0f 38 f1 f9    	crc32  rdi,r9
  3c:	f2 49 0f 38 f1 f1    	crc32  rsi,r9
  42:	f2 49 0f 38 f1 e9    	crc32  rbp,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 12.0
- Reference cycles: 8.43
- UOPS_EXECUTED.THREAD: 12.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.0

With loop_count=1000 and unroll_count=1

Code:

   0:	f2 4d 0f 38 f1 c1    	crc32  r8,r9
   6:	f2 4d 0f 38 f1 d1    	crc32  r10,r9
   c:	f2 4d 0f 38 f1 d9    	crc32  r11,r9
  12:	f2 4d 0f 38 f1 e1    	crc32  r12,r9
  18:	f2 4d 0f 38 f1 e9    	crc32  r13,r9
  1e:	f2 4d 0f 38 f1 f1    	crc32  r14,r9
  24:	f2 49 0f 38 f1 d9    	crc32  rbx,r9
  2a:	f2 49 0f 38 f1 c9    	crc32  rcx,r9
  30:	f2 49 0f 38 f1 d1    	crc32  rdx,r9
  36:	f2 49 0f 38 f1 f9    	crc32  rdi,r9
  3c:	f2 49 0f 38 f1 f1    	crc32  rsi,r9
  42:	f2 49 0f 38 f1 e9    	crc32  rbp,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 12.01
- Reference cycles: 8.63
- UOPS_EXECUTED.THREAD: 13.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	f2 4d 0f 38 f1 c1    	crc32  r8,r9
   6:	f2 4d 0f 38 f1 d1    	crc32  r10,r9
   c:	f2 4d 0f 38 f1 d9    	crc32  r11,r9
  12:	f2 4d 0f 38 f1 e1    	crc32  r12,r9
  18:	f2 4d 0f 38 f1 e9    	crc32  r13,r9
  1e:	f2 4d 0f 38 f1 f1    	crc32  r14,r9
  24:	f2 49 0f 38 f1 d9    	crc32  rbx,r9
  2a:	f2 49 0f 38 f1 c9    	crc32  rcx,r9
  30:	f2 49 0f 38 f1 d1    	crc32  rdx,r9
  36:	f2 49 0f 38 f1 f9    	crc32  rdi,r9
  3c:	f2 49 0f 38 f1 f1    	crc32  rsi,r9
  42:	f2 49 0f 38 f1 e9    	crc32  rbp,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 12.01
- Reference cycles: 8.28
- UOPS_EXECUTED.THREAD: 12.1
- RETIRE_SLOTS: 12.1
- UOPS_MITE: 0.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	f2 4d 0f 38 f1 c0    	crc32  r8,r8

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 2.02
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	f2 4d 0f 38 f1 c0    	crc32  r8,r8

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.0
- Reference cycles: 2.07
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	f2 4d 0f 38 f1 c0    	crc32  r8,r8

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.0
- Reference cycles: 2.08
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	f2 4d 0f 38 f1 c0    	crc32  r8,r8
   6:	f2 4d 0f 38 f1 c9    	crc32  r9,r9
   c:	f2 4d 0f 38 f1 d2    	crc32  r10,r10
  12:	f2 4d 0f 38 f1 db    	crc32  r11,r11

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.84
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	f2 4d 0f 38 f1 c0    	crc32  r8,r8
   6:	f2 4d 0f 38 f1 c9    	crc32  r9,r9
   c:	f2 4d 0f 38 f1 d2    	crc32  r10,r10
  12:	f2 4d 0f 38 f1 db    	crc32  r11,r11

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 2.76
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	f2 4d 0f 38 f1 c0    	crc32  r8,r8
   6:	f2 4d 0f 38 f1 c9    	crc32  r9,r9
   c:	f2 4d 0f 38 f1 d2    	crc32  r10,r10
  12:	f2 4d 0f 38 f1 db    	crc32  r11,r11

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 2.81
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f2 4d 0f 38 f1 c0    	crc32  r8,r8
   6:	f2 4d 0f 38 f1 c9    	crc32  r9,r9
   c:	f2 4d 0f 38 f1 d2    	crc32  r10,r10
  12:	f2 4d 0f 38 f1 db    	crc32  r11,r11
  18:	f2 4d 0f 38 f1 e4    	crc32  r12,r12
  1e:	f2 4d 0f 38 f1 ed    	crc32  r13,r13
  24:	f2 4d 0f 38 f1 f6    	crc32  r14,r14
  2a:	f2 48 0f 38 f1 db    	crc32  rbx,rbx

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 5.98
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	f2 4d 0f 38 f1 c0    	crc32  r8,r8
   6:	f2 4d 0f 38 f1 c9    	crc32  r9,r9
   c:	f2 4d 0f 38 f1 d2    	crc32  r10,r10
  12:	f2 4d 0f 38 f1 db    	crc32  r11,r11
  18:	f2 4d 0f 38 f1 e4    	crc32  r12,r12
  1e:	f2 4d 0f 38 f1 ed    	crc32  r13,r13
  24:	f2 4d 0f 38 f1 f6    	crc32  r14,r14
  2a:	f2 48 0f 38 f1 db    	crc32  rbx,rbx

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 5.5
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	f2 4d 0f 38 f1 c0    	crc32  r8,r8
   6:	f2 4d 0f 38 f1 c9    	crc32  r9,r9
   c:	f2 4d 0f 38 f1 d2    	crc32  r10,r10
  12:	f2 4d 0f 38 f1 db    	crc32  r11,r11
  18:	f2 4d 0f 38 f1 e4    	crc32  r12,r12
  1e:	f2 4d 0f 38 f1 ed    	crc32  r13,r13
  24:	f2 4d 0f 38 f1 f6    	crc32  r14,r14
  2a:	f2 48 0f 38 f1 db    	crc32  rbx,rbx

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 5.61
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.11
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f2 4d 0f 38 f1 c0    	crc32  r8,r8
   6:	f2 4d 0f 38 f1 c9    	crc32  r9,r9
   c:	f2 4d 0f 38 f1 d2    	crc32  r10,r10
  12:	f2 4d 0f 38 f1 db    	crc32  r11,r11
  18:	f2 4d 0f 38 f1 e4    	crc32  r12,r12
  1e:	f2 4d 0f 38 f1 ed    	crc32  r13,r13
  24:	f2 4d 0f 38 f1 f6    	crc32  r14,r14
  2a:	f2 48 0f 38 f1 db    	crc32  rbx,rbx
  30:	f2 48 0f 38 f1 c9    	crc32  rcx,rcx
  36:	f2 48 0f 38 f1 d2    	crc32  rdx,rdx
  3c:	f2 48 0f 38 f1 ff    	crc32  rdi,rdi
  42:	f2 48 0f 38 f1 f6    	crc32  rsi,rsi
  48:	f2 48 0f 38 f1 ed    	crc32  rbp,rbp

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 13.0
- Reference cycles: 8.74
- UOPS_EXECUTED.THREAD: 13.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 13.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 13.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.25

With loop_count=1000 and unroll_count=1

Code:

   0:	f2 4d 0f 38 f1 c0    	crc32  r8,r8
   6:	f2 4d 0f 38 f1 c9    	crc32  r9,r9
   c:	f2 4d 0f 38 f1 d2    	crc32  r10,r10
  12:	f2 4d 0f 38 f1 db    	crc32  r11,r11
  18:	f2 4d 0f 38 f1 e4    	crc32  r12,r12
  1e:	f2 4d 0f 38 f1 ed    	crc32  r13,r13
  24:	f2 4d 0f 38 f1 f6    	crc32  r14,r14
  2a:	f2 48 0f 38 f1 db    	crc32  rbx,rbx
  30:	f2 48 0f 38 f1 c9    	crc32  rcx,rcx
  36:	f2 48 0f 38 f1 d2    	crc32  rdx,rdx
  3c:	f2 48 0f 38 f1 ff    	crc32  rdi,rdi
  42:	f2 48 0f 38 f1 f6    	crc32  rsi,rsi
  48:	f2 48 0f 38 f1 ed    	crc32  rbp,rbp

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 13.01
- Reference cycles: 8.95
- UOPS_EXECUTED.THREAD: 14.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 13.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	f2 4d 0f 38 f1 c0    	crc32  r8,r8
   6:	f2 4d 0f 38 f1 c9    	crc32  r9,r9
   c:	f2 4d 0f 38 f1 d2    	crc32  r10,r10
  12:	f2 4d 0f 38 f1 db    	crc32  r11,r11
  18:	f2 4d 0f 38 f1 e4    	crc32  r12,r12
  1e:	f2 4d 0f 38 f1 ed    	crc32  r13,r13
  24:	f2 4d 0f 38 f1 f6    	crc32  r14,r14
  2a:	f2 48 0f 38 f1 db    	crc32  rbx,rbx
  30:	f2 48 0f 38 f1 c9    	crc32  rcx,rcx
  36:	f2 48 0f 38 f1 d2    	crc32  rdx,rdx
  3c:	f2 48 0f 38 f1 ff    	crc32  rdi,rdi
  42:	f2 48 0f 38 f1 f6    	crc32  rsi,rsi
  48:	f2 48 0f 38 f1 ed    	crc32  rbp,rbp

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 13.01
- Reference cycles: 8.95
- UOPS_EXECUTED.THREAD: 13.1
- RETIRE_SLOTS: 13.1
- UOPS_MITE: 0.13
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 13.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

CRC32 (R64, R64) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 12 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10