CMPXCHG_LOCK (M32, R32) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 18.0
  • Reference cycles: 12.51
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 10.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 10.0
  • UOPS_PORT_0: 1.13
  • UOPS_PORT_1: 0.87
  • UOPS_PORT_2: 1.33
  • UOPS_PORT_3: 0.67
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 1.13
  • UOPS_PORT_6: 1.87
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     5:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 18.0
  • Reference cycles: 12.48
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 11.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 10.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.99
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 1.01
  • UOPS_PORT_6: 2.01
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 18.0
  • Reference cycles: 12.45
  • UOPS_EXECUTED.THREAD: 8.1
  • RETIRE_SLOTS: 10.1
  • UOPS_MITE: 0.1
  • UOPS_MS: 10.01
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 1.02
  • UOPS_PORT_2: 1.08
  • UOPS_PORT_3: 0.92
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 0.98
  • UOPS_PORT_6: 2.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.1

With loop_count=100 and unroll_count=100

• Code:

     0:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 18.0
  • Reference cycles: 12.45
  • UOPS_EXECUTED.THREAD: 8.01
  • RETIRE_SLOTS: 10.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 10.01
  • UOPS_PORT_0: 0.99
  • UOPS_PORT_1: 0.86
  • UOPS_PORT_2: 1.1
  • UOPS_PORT_3: 0.9
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 1.14
  • UOPS_PORT_6: 2.02
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 18.0
  • Reference cycles: 12.39
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 11.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 10.0
  • UOPS_PORT_0: 1.51
  • UOPS_PORT_1: 1.6
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.01
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 1.48
  • UOPS_PORT_6: 2.51
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.2
  • Core cycles: 18.0
  • Reference cycles: 12.45
  • UOPS_EXECUTED.THREAD: 8.1
  • RETIRE_SLOTS: 11.1
  • UOPS_MITE: 1.1
  • UOPS_MS: 10.01
  • UOPS_PORT_0: 1.54
  • UOPS_PORT_1: 1.58
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 1.53
  • UOPS_PORT_6: 2.58
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=100

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.02
  • Core cycles: 18.0
  • Reference cycles: 12.45
  • UOPS_EXECUTED.THREAD: 8.01
  • RETIRE_SLOTS: 11.01
  • UOPS_MITE: 1.01
  • UOPS_MS: 10.01
  • UOPS_PORT_0: 1.55
  • UOPS_PORT_1: 1.59
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 1.53
  • UOPS_PORT_6: 2.51
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=200 and no inner loop

• Code:

     0:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     5:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
     b:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    11:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 84.0
  • Reference cycles: 58.19
  • UOPS_EXECUTED.THREAD: 32.0
  • RETIRE_SLOTS: 40.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 40.0
  • UOPS_PORT_0: 6.32
  • UOPS_PORT_1: 4.91
  • UOPS_PORT_2: 4.14
  • UOPS_PORT_3: 3.86
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 5.08
  • UOPS_PORT_6: 9.39
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     5:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
     b:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    11:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 84.0
  • Reference cycles: 58.11
  • UOPS_EXECUTED.THREAD: 32.5
  • RETIRE_SLOTS: 40.5
  • UOPS_MITE: 0.5
  • UOPS_MS: 40.03
  • UOPS_PORT_0: 5.6
  • UOPS_PORT_1: 5.28
  • UOPS_PORT_2: 4.3
  • UOPS_PORT_3: 3.7
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 4.72
  • UOPS_PORT_6: 10.07
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With loop_count=100 and unroll_count=20

• Code:

     0:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     5:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
     b:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    11:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 84.0
  • Reference cycles: 58.1
  • UOPS_EXECUTED.THREAD: 32.05
  • RETIRE_SLOTS: 40.06
  • UOPS_MITE: 0.05
  • UOPS_MS: 40.03
  • UOPS_PORT_0: 5.79
  • UOPS_PORT_1: 4.64
  • UOPS_PORT_2: 4.35
  • UOPS_PORT_3: 3.65
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 5.36
  • UOPS_PORT_6: 9.83
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.05

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     8:	48 31 c0             	xor    rax,rax
     b:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
    11:	48 31 c0             	xor    rax,rax
    14:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    1a:	48 31 c0             	xor    rax,rax
    1d:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 84.0
  • Reference cycles: 58.11
  • UOPS_EXECUTED.THREAD: 32.0
  • RETIRE_SLOTS: 44.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 40.0
  • UOPS_PORT_0: 9.4
  • UOPS_PORT_1: 9.32
  • UOPS_PORT_2: 4.64
  • UOPS_PORT_3: 3.36
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 9.31
  • UOPS_PORT_6: 13.14
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     8:	48 31 c0             	xor    rax,rax
     b:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
    11:	48 31 c0             	xor    rax,rax
    14:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    1a:	48 31 c0             	xor    rax,rax
    1d:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 9.0
  • Core cycles: 82.5
  • Reference cycles: 57.06
  • UOPS_EXECUTED.THREAD: 32.5
  • RETIRE_SLOTS: 44.5
  • UOPS_MITE: 4.5
  • UOPS_MS: 40.03
  • UOPS_PORT_0: 9.27
  • UOPS_PORT_1: 9.13
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 9.09
  • UOPS_PORT_6: 13.52
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=100 and unroll_count=20

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     8:	48 31 c0             	xor    rax,rax
     b:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
    11:	48 31 c0             	xor    rax,rax
    14:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    1a:	48 31 c0             	xor    rax,rax
    1d:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.1
  • Core cycles: 83.9
  • Reference cycles: 58.01
  • UOPS_EXECUTED.THREAD: 32.05
  • RETIRE_SLOTS: 44.05
  • UOPS_MITE: 4.05
  • UOPS_MS: 40.03
  • UOPS_PORT_0: 9.41
  • UOPS_PORT_1: 9.2
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 9.32
  • UOPS_PORT_6: 13.22
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With unroll_count=100 and no inner loop

• Code:

     0:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     5:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
     b:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    11:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
    17:	f0 45 0f b1 46 10    	lock cmpxchg DWORD PTR [r14+0x10],r8d
    1d:	f0 45 0f b1 46 14    	lock cmpxchg DWORD PTR [r14+0x14],r8d
    23:	f0 45 0f b1 46 18    	lock cmpxchg DWORD PTR [r14+0x18],r8d
    29:	f0 45 0f b1 46 1c    	lock cmpxchg DWORD PTR [r14+0x1c],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 168.01
  • Reference cycles: 116.07
  • UOPS_EXECUTED.THREAD: 64.0
  • RETIRE_SLOTS: 80.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 80.0
  • UOPS_PORT_0: 12.63
  • UOPS_PORT_1: 9.95
  • UOPS_PORT_2: 11.47
  • UOPS_PORT_3: 4.53
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 10.03
  • UOPS_PORT_6: 18.81
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     5:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
     b:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    11:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
    17:	f0 45 0f b1 46 10    	lock cmpxchg DWORD PTR [r14+0x10],r8d
    1d:	f0 45 0f b1 46 14    	lock cmpxchg DWORD PTR [r14+0x14],r8d
    23:	f0 45 0f b1 46 18    	lock cmpxchg DWORD PTR [r14+0x18],r8d
    29:	f0 45 0f b1 46 1c    	lock cmpxchg DWORD PTR [r14+0x1c],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 168.0
  • Reference cycles: 116.18
  • UOPS_EXECUTED.THREAD: 65.0
  • RETIRE_SLOTS: 81.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 80.06
  • UOPS_PORT_0: 11.19
  • UOPS_PORT_1: 10.56
  • UOPS_PORT_2: 8.62
  • UOPS_PORT_3: 7.39
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 9.45
  • UOPS_PORT_6: 20.13
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=10

• Code:

     0:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     5:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
     b:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    11:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
    17:	f0 45 0f b1 46 10    	lock cmpxchg DWORD PTR [r14+0x10],r8d
    1d:	f0 45 0f b1 46 14    	lock cmpxchg DWORD PTR [r14+0x14],r8d
    23:	f0 45 0f b1 46 18    	lock cmpxchg DWORD PTR [r14+0x18],r8d
    29:	f0 45 0f b1 46 1c    	lock cmpxchg DWORD PTR [r14+0x1c],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 168.01
  • Reference cycles: 116.18
  • UOPS_EXECUTED.THREAD: 64.1
  • RETIRE_SLOTS: 80.12
  • UOPS_MITE: 0.1
  • UOPS_MS: 80.06
  • UOPS_PORT_0: 11.59
  • UOPS_PORT_1: 9.23
  • UOPS_PORT_2: 8.7
  • UOPS_PORT_3: 7.3
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 10.73
  • UOPS_PORT_6: 19.66
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.1

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     8:	48 31 c0             	xor    rax,rax
     b:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
    11:	48 31 c0             	xor    rax,rax
    14:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    1a:	48 31 c0             	xor    rax,rax
    1d:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
    23:	48 31 c0             	xor    rax,rax
    26:	f0 45 0f b1 46 10    	lock cmpxchg DWORD PTR [r14+0x10],r8d
    2c:	48 31 c0             	xor    rax,rax
    2f:	f0 45 0f b1 46 14    	lock cmpxchg DWORD PTR [r14+0x14],r8d
    35:	48 31 c0             	xor    rax,rax
    38:	f0 45 0f b1 46 18    	lock cmpxchg DWORD PTR [r14+0x18],r8d
    3e:	48 31 c0             	xor    rax,rax
    41:	f0 45 0f b1 46 1c    	lock cmpxchg DWORD PTR [r14+0x1c],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 168.0
  • Reference cycles: 116.07
  • UOPS_EXECUTED.THREAD: 64.0
  • RETIRE_SLOTS: 88.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 80.0
  • UOPS_PORT_0: 19.18
  • UOPS_PORT_1: 18.32
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 18.82
  • UOPS_PORT_6: 26.77
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     8:	48 31 c0             	xor    rax,rax
     b:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
    11:	48 31 c0             	xor    rax,rax
    14:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    1a:	48 31 c0             	xor    rax,rax
    1d:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
    23:	48 31 c0             	xor    rax,rax
    26:	f0 45 0f b1 46 10    	lock cmpxchg DWORD PTR [r14+0x10],r8d
    2c:	48 31 c0             	xor    rax,rax
    2f:	f0 45 0f b1 46 14    	lock cmpxchg DWORD PTR [r14+0x14],r8d
    35:	48 31 c0             	xor    rax,rax
    38:	f0 45 0f b1 46 18    	lock cmpxchg DWORD PTR [r14+0x18],r8d
    3e:	48 31 c0             	xor    rax,rax
    41:	f0 45 0f b1 46 1c    	lock cmpxchg DWORD PTR [r14+0x1c],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 165.01
  • Reference cycles: 114.1
  • UOPS_EXECUTED.THREAD: 65.0
  • RETIRE_SLOTS: 89.0
  • UOPS_MITE: 9.01
  • UOPS_MS: 80.05
  • UOPS_PORT_0: 18.56
  • UOPS_PORT_1: 18.28
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 18.17
  • UOPS_PORT_6: 27.04
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.01

With loop_count=100 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     8:	48 31 c0             	xor    rax,rax
     b:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
    11:	48 31 c0             	xor    rax,rax
    14:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    1a:	48 31 c0             	xor    rax,rax
    1d:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
    23:	48 31 c0             	xor    rax,rax
    26:	f0 45 0f b1 46 10    	lock cmpxchg DWORD PTR [r14+0x10],r8d
    2c:	48 31 c0             	xor    rax,rax
    2f:	f0 45 0f b1 46 14    	lock cmpxchg DWORD PTR [r14+0x14],r8d
    35:	48 31 c0             	xor    rax,rax
    38:	f0 45 0f b1 46 18    	lock cmpxchg DWORD PTR [r14+0x18],r8d
    3e:	48 31 c0             	xor    rax,rax
    41:	f0 45 0f b1 46 1c    	lock cmpxchg DWORD PTR [r14+0x1c],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 167.81
  • Reference cycles: 116.04
  • UOPS_EXECUTED.THREAD: 64.1
  • RETIRE_SLOTS: 88.1
  • UOPS_MITE: 8.11
  • UOPS_MS: 80.05
  • UOPS_PORT_0: 18.79
  • UOPS_PORT_1: 18.47
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 18.6
  • UOPS_PORT_6: 26.44
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.01

With unroll_count=100 and no inner loop

• Code:

     0:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     5:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
     b:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    11:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
    17:	f0 45 0f b1 46 10    	lock cmpxchg DWORD PTR [r14+0x10],r8d
    1d:	f0 45 0f b1 46 14    	lock cmpxchg DWORD PTR [r14+0x14],r8d
    23:	f0 45 0f b1 46 18    	lock cmpxchg DWORD PTR [r14+0x18],r8d
    29:	f0 45 0f b1 46 1c    	lock cmpxchg DWORD PTR [r14+0x1c],r8d
    2f:	f0 45 0f b1 46 20    	lock cmpxchg DWORD PTR [r14+0x20],r8d
    35:	f0 45 0f b1 46 24    	lock cmpxchg DWORD PTR [r14+0x24],r8d
    3b:	f0 45 0f b1 46 28    	lock cmpxchg DWORD PTR [r14+0x28],r8d
    41:	f0 45 0f b1 46 2c    	lock cmpxchg DWORD PTR [r14+0x2c],r8d
    47:	f0 45 0f b1 46 30    	lock cmpxchg DWORD PTR [r14+0x30],r8d
    4d:	f0 45 0f b1 46 34    	lock cmpxchg DWORD PTR [r14+0x34],r8d
    53:	f0 45 0f b1 46 38    	lock cmpxchg DWORD PTR [r14+0x38],r8d
    59:	f0 45 0f b1 46 3c    	lock cmpxchg DWORD PTR [r14+0x3c],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 336.01
  • Reference cycles: 232.3
  • UOPS_EXECUTED.THREAD: 128.01
  • RETIRE_SLOTS: 160.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 160.0
  • UOPS_PORT_0: 24.76
  • UOPS_PORT_1: 19.77
  • UOPS_PORT_2: 21.75
  • UOPS_PORT_3: 10.25
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 20.53
  • UOPS_PORT_6: 37.44
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     5:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
     b:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    11:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
    17:	f0 45 0f b1 46 10    	lock cmpxchg DWORD PTR [r14+0x10],r8d
    1d:	f0 45 0f b1 46 14    	lock cmpxchg DWORD PTR [r14+0x14],r8d
    23:	f0 45 0f b1 46 18    	lock cmpxchg DWORD PTR [r14+0x18],r8d
    29:	f0 45 0f b1 46 1c    	lock cmpxchg DWORD PTR [r14+0x1c],r8d
    2f:	f0 45 0f b1 46 20    	lock cmpxchg DWORD PTR [r14+0x20],r8d
    35:	f0 45 0f b1 46 24    	lock cmpxchg DWORD PTR [r14+0x24],r8d
    3b:	f0 45 0f b1 46 28    	lock cmpxchg DWORD PTR [r14+0x28],r8d
    41:	f0 45 0f b1 46 2c    	lock cmpxchg DWORD PTR [r14+0x2c],r8d
    47:	f0 45 0f b1 46 30    	lock cmpxchg DWORD PTR [r14+0x30],r8d
    4d:	f0 45 0f b1 46 34    	lock cmpxchg DWORD PTR [r14+0x34],r8d
    53:	f0 45 0f b1 46 38    	lock cmpxchg DWORD PTR [r14+0x38],r8d
    59:	f0 45 0f b1 46 3c    	lock cmpxchg DWORD PTR [r14+0x3c],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 336.01
  • Reference cycles: 232.39
  • UOPS_EXECUTED.THREAD: 129.0
  • RETIRE_SLOTS: 161.01
  • UOPS_MITE: 1.0
  • UOPS_MS: 160.06
  • UOPS_PORT_0: 23.39
  • UOPS_PORT_1: 18.73
  • UOPS_PORT_2: 17.26
  • UOPS_PORT_3: 14.75
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 21.31
  • UOPS_PORT_6: 39.44
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=10

• Code:

     0:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     5:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
     b:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    11:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
    17:	f0 45 0f b1 46 10    	lock cmpxchg DWORD PTR [r14+0x10],r8d
    1d:	f0 45 0f b1 46 14    	lock cmpxchg DWORD PTR [r14+0x14],r8d
    23:	f0 45 0f b1 46 18    	lock cmpxchg DWORD PTR [r14+0x18],r8d
    29:	f0 45 0f b1 46 1c    	lock cmpxchg DWORD PTR [r14+0x1c],r8d
    2f:	f0 45 0f b1 46 20    	lock cmpxchg DWORD PTR [r14+0x20],r8d
    35:	f0 45 0f b1 46 24    	lock cmpxchg DWORD PTR [r14+0x24],r8d
    3b:	f0 45 0f b1 46 28    	lock cmpxchg DWORD PTR [r14+0x28],r8d
    41:	f0 45 0f b1 46 2c    	lock cmpxchg DWORD PTR [r14+0x2c],r8d
    47:	f0 45 0f b1 46 30    	lock cmpxchg DWORD PTR [r14+0x30],r8d
    4d:	f0 45 0f b1 46 34    	lock cmpxchg DWORD PTR [r14+0x34],r8d
    53:	f0 45 0f b1 46 38    	lock cmpxchg DWORD PTR [r14+0x38],r8d
    59:	f0 45 0f b1 46 3c    	lock cmpxchg DWORD PTR [r14+0x3c],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 336.0
  • Reference cycles: 232.35
  • UOPS_EXECUTED.THREAD: 128.1
  • RETIRE_SLOTS: 160.1
  • UOPS_MITE: 0.1
  • UOPS_MS: 160.06
  • UOPS_PORT_0: 23.08
  • UOPS_PORT_1: 18.46
  • UOPS_PORT_2: 17.46
  • UOPS_PORT_3: 14.54
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 21.49
  • UOPS_PORT_6: 39.57
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.1

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     8:	48 31 c0             	xor    rax,rax
     b:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
    11:	48 31 c0             	xor    rax,rax
    14:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    1a:	48 31 c0             	xor    rax,rax
    1d:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
    23:	48 31 c0             	xor    rax,rax
    26:	f0 45 0f b1 46 10    	lock cmpxchg DWORD PTR [r14+0x10],r8d
    2c:	48 31 c0             	xor    rax,rax
    2f:	f0 45 0f b1 46 14    	lock cmpxchg DWORD PTR [r14+0x14],r8d
    35:	48 31 c0             	xor    rax,rax
    38:	f0 45 0f b1 46 18    	lock cmpxchg DWORD PTR [r14+0x18],r8d
    3e:	48 31 c0             	xor    rax,rax
    41:	f0 45 0f b1 46 1c    	lock cmpxchg DWORD PTR [r14+0x1c],r8d
    47:	48 31 c0             	xor    rax,rax
    4a:	f0 45 0f b1 46 20    	lock cmpxchg DWORD PTR [r14+0x20],r8d
    50:	48 31 c0             	xor    rax,rax
    53:	f0 45 0f b1 46 24    	lock cmpxchg DWORD PTR [r14+0x24],r8d
    59:	48 31 c0             	xor    rax,rax
    5c:	f0 45 0f b1 46 28    	lock cmpxchg DWORD PTR [r14+0x28],r8d
    62:	48 31 c0             	xor    rax,rax
    65:	f0 45 0f b1 46 2c    	lock cmpxchg DWORD PTR [r14+0x2c],r8d
    6b:	48 31 c0             	xor    rax,rax
    6e:	f0 45 0f b1 46 30    	lock cmpxchg DWORD PTR [r14+0x30],r8d
    74:	48 31 c0             	xor    rax,rax
    77:	f0 45 0f b1 46 34    	lock cmpxchg DWORD PTR [r14+0x34],r8d
    7d:	48 31 c0             	xor    rax,rax
    80:	f0 45 0f b1 46 38    	lock cmpxchg DWORD PTR [r14+0x38],r8d
    86:	48 31 c0             	xor    rax,rax
    89:	f0 45 0f b1 46 3c    	lock cmpxchg DWORD PTR [r14+0x3c],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 32.0
  • Core cycles: 336.31
  • Reference cycles: 239.97
  • UOPS_EXECUTED.THREAD: 128.0
  • RETIRE_SLOTS: 176.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 160.0
  • UOPS_PORT_0: 28.25
  • UOPS_PORT_1: 28.0
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.04
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 29.01
  • UOPS_PORT_6: 42.87
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.04

With loop_count=1000 and unroll_count=1

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     8:	48 31 c0             	xor    rax,rax
     b:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
    11:	48 31 c0             	xor    rax,rax
    14:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    1a:	48 31 c0             	xor    rax,rax
    1d:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
    23:	48 31 c0             	xor    rax,rax
    26:	f0 45 0f b1 46 10    	lock cmpxchg DWORD PTR [r14+0x10],r8d
    2c:	48 31 c0             	xor    rax,rax
    2f:	f0 45 0f b1 46 14    	lock cmpxchg DWORD PTR [r14+0x14],r8d
    35:	48 31 c0             	xor    rax,rax
    38:	f0 45 0f b1 46 18    	lock cmpxchg DWORD PTR [r14+0x18],r8d
    3e:	48 31 c0             	xor    rax,rax
    41:	f0 45 0f b1 46 1c    	lock cmpxchg DWORD PTR [r14+0x1c],r8d
    47:	48 31 c0             	xor    rax,rax
    4a:	f0 45 0f b1 46 20    	lock cmpxchg DWORD PTR [r14+0x20],r8d
    50:	48 31 c0             	xor    rax,rax
    53:	f0 45 0f b1 46 24    	lock cmpxchg DWORD PTR [r14+0x24],r8d
    59:	48 31 c0             	xor    rax,rax
    5c:	f0 45 0f b1 46 28    	lock cmpxchg DWORD PTR [r14+0x28],r8d
    62:	48 31 c0             	xor    rax,rax
    65:	f0 45 0f b1 46 2c    	lock cmpxchg DWORD PTR [r14+0x2c],r8d
    6b:	48 31 c0             	xor    rax,rax
    6e:	f0 45 0f b1 46 30    	lock cmpxchg DWORD PTR [r14+0x30],r8d
    74:	48 31 c0             	xor    rax,rax
    77:	f0 45 0f b1 46 34    	lock cmpxchg DWORD PTR [r14+0x34],r8d
    7d:	48 31 c0             	xor    rax,rax
    80:	f0 45 0f b1 46 38    	lock cmpxchg DWORD PTR [r14+0x38],r8d
    86:	48 31 c0             	xor    rax,rax
    89:	f0 45 0f b1 46 3c    	lock cmpxchg DWORD PTR [r14+0x3c],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 34.0
  • Core cycles: 334.05
  • Reference cycles: 238.49
  • UOPS_EXECUTED.THREAD: 129.41
  • RETIRE_SLOTS: 177.13
  • UOPS_MITE: 17.1
  • UOPS_MS: 161.1
  • UOPS_PORT_0: 28.04
  • UOPS_PORT_1: 26.86
  • UOPS_PORT_2: 16.08
  • UOPS_PORT_3: 16.09
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 29.74
  • UOPS_PORT_6: 43.13
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=100 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 45 0f b1 06       	lock cmpxchg DWORD PTR [r14],r8d
     8:	48 31 c0             	xor    rax,rax
     b:	f0 45 0f b1 46 04    	lock cmpxchg DWORD PTR [r14+0x4],r8d
    11:	48 31 c0             	xor    rax,rax
    14:	f0 45 0f b1 46 08    	lock cmpxchg DWORD PTR [r14+0x8],r8d
    1a:	48 31 c0             	xor    rax,rax
    1d:	f0 45 0f b1 46 0c    	lock cmpxchg DWORD PTR [r14+0xc],r8d
    23:	48 31 c0             	xor    rax,rax
    26:	f0 45 0f b1 46 10    	lock cmpxchg DWORD PTR [r14+0x10],r8d
    2c:	48 31 c0             	xor    rax,rax
    2f:	f0 45 0f b1 46 14    	lock cmpxchg DWORD PTR [r14+0x14],r8d
    35:	48 31 c0             	xor    rax,rax
    38:	f0 45 0f b1 46 18    	lock cmpxchg DWORD PTR [r14+0x18],r8d
    3e:	48 31 c0             	xor    rax,rax
    41:	f0 45 0f b1 46 1c    	lock cmpxchg DWORD PTR [r14+0x1c],r8d
    47:	48 31 c0             	xor    rax,rax
    4a:	f0 45 0f b1 46 20    	lock cmpxchg DWORD PTR [r14+0x20],r8d
    50:	48 31 c0             	xor    rax,rax
    53:	f0 45 0f b1 46 24    	lock cmpxchg DWORD PTR [r14+0x24],r8d
    59:	48 31 c0             	xor    rax,rax
    5c:	f0 45 0f b1 46 28    	lock cmpxchg DWORD PTR [r14+0x28],r8d
    62:	48 31 c0             	xor    rax,rax
    65:	f0 45 0f b1 46 2c    	lock cmpxchg DWORD PTR [r14+0x2c],r8d
    6b:	48 31 c0             	xor    rax,rax
    6e:	f0 45 0f b1 46 30    	lock cmpxchg DWORD PTR [r14+0x30],r8d
    74:	48 31 c0             	xor    rax,rax
    77:	f0 45 0f b1 46 34    	lock cmpxchg DWORD PTR [r14+0x34],r8d
    7d:	48 31 c0             	xor    rax,rax
    80:	f0 45 0f b1 46 38    	lock cmpxchg DWORD PTR [r14+0x38],r8d
    86:	48 31 c0             	xor    rax,rax
    89:	f0 45 0f b1 46 3c    	lock cmpxchg DWORD PTR [r14+0x3c],r8d
  

• Show nanoBench command
• Results:
  • Instructions retired: 32.2
  • Core cycles: 335.81
  • Reference cycles: 232.21
  • UOPS_EXECUTED.THREAD: 128.1
  • RETIRE_SLOTS: 176.12
  • UOPS_MITE: 16.1
  • UOPS_MS: 160.06
  • UOPS_PORT_0: 27.89
  • UOPS_PORT_1: 28.21
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.01
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 28.6
  • UOPS_PORT_6: 42.73
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With unroll_count=500 and no inner loop

• Code:

     0:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 18.0
  • Reference cycles: 12.51
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 10.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 10.0
  • UOPS_PORT_0: 1.13
  • UOPS_PORT_1: 0.87
  • UOPS_PORT_2: 1.33
  • UOPS_PORT_3: 0.67
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 1.13
  • UOPS_PORT_6: 1.87
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     6:	90                   	nop
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 18.0
  • Reference cycles: 12.45
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 11.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 10.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.99
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 1.01
  • UOPS_PORT_6: 2.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 18.0
  • Reference cycles: 12.45
  • UOPS_EXECUTED.THREAD: 8.1
  • RETIRE_SLOTS: 10.1
  • UOPS_MITE: 0.1
  • UOPS_MS: 10.01
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 1.02
  • UOPS_PORT_2: 1.08
  • UOPS_PORT_3: 0.92
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 0.98
  • UOPS_PORT_6: 2.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.1

With loop_count=100 and unroll_count=100

• Code:

     0:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 18.0
  • Reference cycles: 12.45
  • UOPS_EXECUTED.THREAD: 8.01
  • RETIRE_SLOTS: 10.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 10.01
  • UOPS_PORT_0: 0.99
  • UOPS_PORT_1: 0.86
  • UOPS_PORT_2: 1.1
  • UOPS_PORT_3: 0.9
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 1.14
  • UOPS_PORT_6: 2.02
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 18.0
  • Reference cycles: 12.39
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 11.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 10.0
  • UOPS_PORT_0: 1.51
  • UOPS_PORT_1: 1.6
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.01
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 1.48
  • UOPS_PORT_6: 2.51
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 2.2
  • Core cycles: 18.0
  • Reference cycles: 12.45
  • UOPS_EXECUTED.THREAD: 8.1
  • RETIRE_SLOTS: 11.1
  • UOPS_MITE: 1.1
  • UOPS_MS: 10.01
  • UOPS_PORT_0: 1.54
  • UOPS_PORT_1: 1.58
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 1.53
  • UOPS_PORT_6: 2.58
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=100

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 2.02
  • Core cycles: 18.0
  • Reference cycles: 12.45
  • UOPS_EXECUTED.THREAD: 8.01
  • RETIRE_SLOTS: 11.01
  • UOPS_MITE: 1.01
  • UOPS_MS: 10.01
  • UOPS_PORT_0: 1.55
  • UOPS_PORT_1: 1.59
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 1.52
  • UOPS_PORT_6: 2.5
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=200 and no inner loop

• Code:

     0:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     6:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
     d:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    14:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 84.0
  • Reference cycles: 57.96
  • UOPS_EXECUTED.THREAD: 32.0
  • RETIRE_SLOTS: 40.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 40.0
  • UOPS_PORT_0: 5.82
  • UOPS_PORT_1: 4.96
  • UOPS_PORT_2: 3.76
  • UOPS_PORT_3: 4.24
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 5.11
  • UOPS_PORT_6: 9.23
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     6:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
     d:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    14:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 84.0
  • Reference cycles: 58.08
  • UOPS_EXECUTED.THREAD: 32.5
  • RETIRE_SLOTS: 40.5
  • UOPS_MITE: 0.5
  • UOPS_MS: 40.03
  • UOPS_PORT_0: 5.6
  • UOPS_PORT_1: 5.28
  • UOPS_PORT_2: 4.3
  • UOPS_PORT_3: 3.7
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 4.72
  • UOPS_PORT_6: 10.05
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With loop_count=100 and unroll_count=20

• Code:

     0:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     6:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
     d:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    14:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 84.0
  • Reference cycles: 58.1
  • UOPS_EXECUTED.THREAD: 32.05
  • RETIRE_SLOTS: 40.06
  • UOPS_MITE: 0.05
  • UOPS_MS: 40.03
  • UOPS_PORT_0: 5.79
  • UOPS_PORT_1: 4.64
  • UOPS_PORT_2: 4.35
  • UOPS_PORT_3: 3.65
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 5.41
  • UOPS_PORT_6: 9.83
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.05

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     9:	48 31 c0             	xor    rax,rax
     c:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
    13:	48 31 c0             	xor    rax,rax
    16:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    1d:	48 31 c0             	xor    rax,rax
    20:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 84.0
  • Reference cycles: 58.11
  • UOPS_EXECUTED.THREAD: 32.0
  • RETIRE_SLOTS: 44.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 40.0
  • UOPS_PORT_0: 9.55
  • UOPS_PORT_1: 9.17
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 9.38
  • UOPS_PORT_6: 13.32
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     9:	48 31 c0             	xor    rax,rax
     c:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
    13:	48 31 c0             	xor    rax,rax
    16:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    1d:	48 31 c0             	xor    rax,rax
    20:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 9.0
  • Core cycles: 82.5
  • Reference cycles: 57.06
  • UOPS_EXECUTED.THREAD: 32.5
  • RETIRE_SLOTS: 44.51
  • UOPS_MITE: 4.5
  • UOPS_MS: 40.03
  • UOPS_PORT_0: 9.3
  • UOPS_PORT_1: 9.12
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 9.1
  • UOPS_PORT_6: 13.56
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=100 and unroll_count=20

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     9:	48 31 c0             	xor    rax,rax
     c:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
    13:	48 31 c0             	xor    rax,rax
    16:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    1d:	48 31 c0             	xor    rax,rax
    20:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.1
  • Core cycles: 83.9
  • Reference cycles: 58.03
  • UOPS_EXECUTED.THREAD: 32.05
  • RETIRE_SLOTS: 44.06
  • UOPS_MITE: 4.05
  • UOPS_MS: 40.03
  • UOPS_PORT_0: 9.43
  • UOPS_PORT_1: 9.21
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 9.37
  • UOPS_PORT_6: 13.22
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With unroll_count=100 and no inner loop

• Code:

     0:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     6:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
     d:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    14:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
    1b:	f0 47 0f b1 44 2e 10 	lock cmpxchg DWORD PTR [r14+r13*1+0x10],r8d
    22:	f0 47 0f b1 44 2e 14 	lock cmpxchg DWORD PTR [r14+r13*1+0x14],r8d
    29:	f0 47 0f b1 44 2e 18 	lock cmpxchg DWORD PTR [r14+r13*1+0x18],r8d
    30:	f0 47 0f b1 44 2e 1c 	lock cmpxchg DWORD PTR [r14+r13*1+0x1c],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 168.01
  • Reference cycles: 116.38
  • UOPS_EXECUTED.THREAD: 64.01
  • RETIRE_SLOTS: 80.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 80.0
  • UOPS_PORT_0: 12.51
  • UOPS_PORT_1: 9.93
  • UOPS_PORT_2: 10.83
  • UOPS_PORT_3: 5.17
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 10.0
  • UOPS_PORT_6: 19.34
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     6:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
     d:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    14:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
    1b:	f0 47 0f b1 44 2e 10 	lock cmpxchg DWORD PTR [r14+r13*1+0x10],r8d
    22:	f0 47 0f b1 44 2e 14 	lock cmpxchg DWORD PTR [r14+r13*1+0x14],r8d
    29:	f0 47 0f b1 44 2e 18 	lock cmpxchg DWORD PTR [r14+r13*1+0x18],r8d
    30:	f0 47 0f b1 44 2e 1c 	lock cmpxchg DWORD PTR [r14+r13*1+0x1c],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 168.0
  • Reference cycles: 116.23
  • UOPS_EXECUTED.THREAD: 65.0
  • RETIRE_SLOTS: 81.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 80.07
  • UOPS_PORT_0: 11.19
  • UOPS_PORT_1: 10.56
  • UOPS_PORT_2: 8.62
  • UOPS_PORT_3: 7.39
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 9.42
  • UOPS_PORT_6: 20.11
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=10

• Code:

     0:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     6:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
     d:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    14:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
    1b:	f0 47 0f b1 44 2e 10 	lock cmpxchg DWORD PTR [r14+r13*1+0x10],r8d
    22:	f0 47 0f b1 44 2e 14 	lock cmpxchg DWORD PTR [r14+r13*1+0x14],r8d
    29:	f0 47 0f b1 44 2e 18 	lock cmpxchg DWORD PTR [r14+r13*1+0x18],r8d
    30:	f0 47 0f b1 44 2e 1c 	lock cmpxchg DWORD PTR [r14+r13*1+0x1c],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 168.01
  • Reference cycles: 116.13
  • UOPS_EXECUTED.THREAD: 64.1
  • RETIRE_SLOTS: 80.1
  • UOPS_MITE: 0.1
  • UOPS_MS: 80.06
  • UOPS_PORT_0: 11.59
  • UOPS_PORT_1: 9.27
  • UOPS_PORT_2: 8.7
  • UOPS_PORT_3: 7.3
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 10.73
  • UOPS_PORT_6: 19.66
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.1

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     9:	48 31 c0             	xor    rax,rax
     c:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
    13:	48 31 c0             	xor    rax,rax
    16:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    1d:	48 31 c0             	xor    rax,rax
    20:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
    27:	48 31 c0             	xor    rax,rax
    2a:	f0 47 0f b1 44 2e 10 	lock cmpxchg DWORD PTR [r14+r13*1+0x10],r8d
    31:	48 31 c0             	xor    rax,rax
    34:	f0 47 0f b1 44 2e 14 	lock cmpxchg DWORD PTR [r14+r13*1+0x14],r8d
    3b:	48 31 c0             	xor    rax,rax
    3e:	f0 47 0f b1 44 2e 18 	lock cmpxchg DWORD PTR [r14+r13*1+0x18],r8d
    45:	48 31 c0             	xor    rax,rax
    48:	f0 47 0f b1 44 2e 1c 	lock cmpxchg DWORD PTR [r14+r13*1+0x1c],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 168.0
  • Reference cycles: 116.07
  • UOPS_EXECUTED.THREAD: 64.0
  • RETIRE_SLOTS: 88.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 80.0
  • UOPS_PORT_0: 19.05
  • UOPS_PORT_1: 18.32
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 18.65
  • UOPS_PORT_6: 26.6
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     9:	48 31 c0             	xor    rax,rax
     c:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
    13:	48 31 c0             	xor    rax,rax
    16:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    1d:	48 31 c0             	xor    rax,rax
    20:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
    27:	48 31 c0             	xor    rax,rax
    2a:	f0 47 0f b1 44 2e 10 	lock cmpxchg DWORD PTR [r14+r13*1+0x10],r8d
    31:	48 31 c0             	xor    rax,rax
    34:	f0 47 0f b1 44 2e 14 	lock cmpxchg DWORD PTR [r14+r13*1+0x14],r8d
    3b:	48 31 c0             	xor    rax,rax
    3e:	f0 47 0f b1 44 2e 18 	lock cmpxchg DWORD PTR [r14+r13*1+0x18],r8d
    45:	48 31 c0             	xor    rax,rax
    48:	f0 47 0f b1 44 2e 1c 	lock cmpxchg DWORD PTR [r14+r13*1+0x1c],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 165.01
  • Reference cycles: 114.13
  • UOPS_EXECUTED.THREAD: 65.0
  • RETIRE_SLOTS: 89.02
  • UOPS_MITE: 9.0
  • UOPS_MS: 80.05
  • UOPS_PORT_0: 18.53
  • UOPS_PORT_1: 18.25
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 18.2
  • UOPS_PORT_6: 27.07
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=100 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     9:	48 31 c0             	xor    rax,rax
     c:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
    13:	48 31 c0             	xor    rax,rax
    16:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    1d:	48 31 c0             	xor    rax,rax
    20:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
    27:	48 31 c0             	xor    rax,rax
    2a:	f0 47 0f b1 44 2e 10 	lock cmpxchg DWORD PTR [r14+r13*1+0x10],r8d
    31:	48 31 c0             	xor    rax,rax
    34:	f0 47 0f b1 44 2e 14 	lock cmpxchg DWORD PTR [r14+r13*1+0x14],r8d
    3b:	48 31 c0             	xor    rax,rax
    3e:	f0 47 0f b1 44 2e 18 	lock cmpxchg DWORD PTR [r14+r13*1+0x18],r8d
    45:	48 31 c0             	xor    rax,rax
    48:	f0 47 0f b1 44 2e 1c 	lock cmpxchg DWORD PTR [r14+r13*1+0x1c],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 167.81
  • Reference cycles: 116.06
  • UOPS_EXECUTED.THREAD: 64.1
  • RETIRE_SLOTS: 88.12
  • UOPS_MITE: 8.1
  • UOPS_MS: 80.06
  • UOPS_PORT_0: 18.8
  • UOPS_PORT_1: 18.45
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 18.67
  • UOPS_PORT_6: 26.47
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With unroll_count=100 and no inner loop

• Code:

     0:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     6:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
     d:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    14:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
    1b:	f0 47 0f b1 44 2e 10 	lock cmpxchg DWORD PTR [r14+r13*1+0x10],r8d
    22:	f0 47 0f b1 44 2e 14 	lock cmpxchg DWORD PTR [r14+r13*1+0x14],r8d
    29:	f0 47 0f b1 44 2e 18 	lock cmpxchg DWORD PTR [r14+r13*1+0x18],r8d
    30:	f0 47 0f b1 44 2e 1c 	lock cmpxchg DWORD PTR [r14+r13*1+0x1c],r8d
    37:	f0 47 0f b1 44 2e 20 	lock cmpxchg DWORD PTR [r14+r13*1+0x20],r8d
    3e:	f0 47 0f b1 44 2e 24 	lock cmpxchg DWORD PTR [r14+r13*1+0x24],r8d
    45:	f0 47 0f b1 44 2e 28 	lock cmpxchg DWORD PTR [r14+r13*1+0x28],r8d
    4c:	f0 47 0f b1 44 2e 2c 	lock cmpxchg DWORD PTR [r14+r13*1+0x2c],r8d
    53:	f0 47 0f b1 44 2e 30 	lock cmpxchg DWORD PTR [r14+r13*1+0x30],r8d
    5a:	f0 47 0f b1 44 2e 34 	lock cmpxchg DWORD PTR [r14+r13*1+0x34],r8d
    61:	f0 47 0f b1 44 2e 38 	lock cmpxchg DWORD PTR [r14+r13*1+0x38],r8d
    68:	f0 47 0f b1 44 2e 3c 	lock cmpxchg DWORD PTR [r14+r13*1+0x3c],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 336.01
  • Reference cycles: 232.76
  • UOPS_EXECUTED.THREAD: 128.0
  • RETIRE_SLOTS: 160.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 160.0
  • UOPS_PORT_0: 23.78
  • UOPS_PORT_1: 19.82
  • UOPS_PORT_2: 21.68
  • UOPS_PORT_3: 10.32
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 20.17
  • UOPS_PORT_6: 39.41
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     6:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
     d:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    14:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
    1b:	f0 47 0f b1 44 2e 10 	lock cmpxchg DWORD PTR [r14+r13*1+0x10],r8d
    22:	f0 47 0f b1 44 2e 14 	lock cmpxchg DWORD PTR [r14+r13*1+0x14],r8d
    29:	f0 47 0f b1 44 2e 18 	lock cmpxchg DWORD PTR [r14+r13*1+0x18],r8d
    30:	f0 47 0f b1 44 2e 1c 	lock cmpxchg DWORD PTR [r14+r13*1+0x1c],r8d
    37:	f0 47 0f b1 44 2e 20 	lock cmpxchg DWORD PTR [r14+r13*1+0x20],r8d
    3e:	f0 47 0f b1 44 2e 24 	lock cmpxchg DWORD PTR [r14+r13*1+0x24],r8d
    45:	f0 47 0f b1 44 2e 28 	lock cmpxchg DWORD PTR [r14+r13*1+0x28],r8d
    4c:	f0 47 0f b1 44 2e 2c 	lock cmpxchg DWORD PTR [r14+r13*1+0x2c],r8d
    53:	f0 47 0f b1 44 2e 30 	lock cmpxchg DWORD PTR [r14+r13*1+0x30],r8d
    5a:	f0 47 0f b1 44 2e 34 	lock cmpxchg DWORD PTR [r14+r13*1+0x34],r8d
    61:	f0 47 0f b1 44 2e 38 	lock cmpxchg DWORD PTR [r14+r13*1+0x38],r8d
    68:	f0 47 0f b1 44 2e 3c 	lock cmpxchg DWORD PTR [r14+r13*1+0x3c],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 336.01
  • Reference cycles: 237.38
  • UOPS_EXECUTED.THREAD: 129.0
  • RETIRE_SLOTS: 161.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 160.07
  • UOPS_PORT_0: 23.41
  • UOPS_PORT_1: 18.73
  • UOPS_PORT_2: 17.27
  • UOPS_PORT_3: 14.74
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 21.24
  • UOPS_PORT_6: 39.42
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=10

• Code:

     0:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     6:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
     d:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    14:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
    1b:	f0 47 0f b1 44 2e 10 	lock cmpxchg DWORD PTR [r14+r13*1+0x10],r8d
    22:	f0 47 0f b1 44 2e 14 	lock cmpxchg DWORD PTR [r14+r13*1+0x14],r8d
    29:	f0 47 0f b1 44 2e 18 	lock cmpxchg DWORD PTR [r14+r13*1+0x18],r8d
    30:	f0 47 0f b1 44 2e 1c 	lock cmpxchg DWORD PTR [r14+r13*1+0x1c],r8d
    37:	f0 47 0f b1 44 2e 20 	lock cmpxchg DWORD PTR [r14+r13*1+0x20],r8d
    3e:	f0 47 0f b1 44 2e 24 	lock cmpxchg DWORD PTR [r14+r13*1+0x24],r8d
    45:	f0 47 0f b1 44 2e 28 	lock cmpxchg DWORD PTR [r14+r13*1+0x28],r8d
    4c:	f0 47 0f b1 44 2e 2c 	lock cmpxchg DWORD PTR [r14+r13*1+0x2c],r8d
    53:	f0 47 0f b1 44 2e 30 	lock cmpxchg DWORD PTR [r14+r13*1+0x30],r8d
    5a:	f0 47 0f b1 44 2e 34 	lock cmpxchg DWORD PTR [r14+r13*1+0x34],r8d
    61:	f0 47 0f b1 44 2e 38 	lock cmpxchg DWORD PTR [r14+r13*1+0x38],r8d
    68:	f0 47 0f b1 44 2e 3c 	lock cmpxchg DWORD PTR [r14+r13*1+0x3c],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 336.01
  • Reference cycles: 236.12
  • UOPS_EXECUTED.THREAD: 128.1
  • RETIRE_SLOTS: 160.12
  • UOPS_MITE: 0.1
  • UOPS_MS: 160.06
  • UOPS_PORT_0: 23.13
  • UOPS_PORT_1: 18.42
  • UOPS_PORT_2: 17.47
  • UOPS_PORT_3: 14.54
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 21.58
  • UOPS_PORT_6: 39.6
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.1

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     9:	48 31 c0             	xor    rax,rax
     c:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
    13:	48 31 c0             	xor    rax,rax
    16:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    1d:	48 31 c0             	xor    rax,rax
    20:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
    27:	48 31 c0             	xor    rax,rax
    2a:	f0 47 0f b1 44 2e 10 	lock cmpxchg DWORD PTR [r14+r13*1+0x10],r8d
    31:	48 31 c0             	xor    rax,rax
    34:	f0 47 0f b1 44 2e 14 	lock cmpxchg DWORD PTR [r14+r13*1+0x14],r8d
    3b:	48 31 c0             	xor    rax,rax
    3e:	f0 47 0f b1 44 2e 18 	lock cmpxchg DWORD PTR [r14+r13*1+0x18],r8d
    45:	48 31 c0             	xor    rax,rax
    48:	f0 47 0f b1 44 2e 1c 	lock cmpxchg DWORD PTR [r14+r13*1+0x1c],r8d
    4f:	48 31 c0             	xor    rax,rax
    52:	f0 47 0f b1 44 2e 20 	lock cmpxchg DWORD PTR [r14+r13*1+0x20],r8d
    59:	48 31 c0             	xor    rax,rax
    5c:	f0 47 0f b1 44 2e 24 	lock cmpxchg DWORD PTR [r14+r13*1+0x24],r8d
    63:	48 31 c0             	xor    rax,rax
    66:	f0 47 0f b1 44 2e 28 	lock cmpxchg DWORD PTR [r14+r13*1+0x28],r8d
    6d:	48 31 c0             	xor    rax,rax
    70:	f0 47 0f b1 44 2e 2c 	lock cmpxchg DWORD PTR [r14+r13*1+0x2c],r8d
    77:	48 31 c0             	xor    rax,rax
    7a:	f0 47 0f b1 44 2e 30 	lock cmpxchg DWORD PTR [r14+r13*1+0x30],r8d
    81:	48 31 c0             	xor    rax,rax
    84:	f0 47 0f b1 44 2e 34 	lock cmpxchg DWORD PTR [r14+r13*1+0x34],r8d
    8b:	48 31 c0             	xor    rax,rax
    8e:	f0 47 0f b1 44 2e 38 	lock cmpxchg DWORD PTR [r14+r13*1+0x38],r8d
    95:	48 31 c0             	xor    rax,rax
    98:	f0 47 0f b1 44 2e 3c 	lock cmpxchg DWORD PTR [r14+r13*1+0x3c],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 32.0
  • Core cycles: 336.0
  • Reference cycles: 232.15
  • UOPS_EXECUTED.THREAD: 128.0
  • RETIRE_SLOTS: 176.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 160.0
  • UOPS_PORT_0: 28.17
  • UOPS_PORT_1: 27.77
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 29.04
  • UOPS_PORT_6: 42.78
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     9:	48 31 c0             	xor    rax,rax
     c:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
    13:	48 31 c0             	xor    rax,rax
    16:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    1d:	48 31 c0             	xor    rax,rax
    20:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
    27:	48 31 c0             	xor    rax,rax
    2a:	f0 47 0f b1 44 2e 10 	lock cmpxchg DWORD PTR [r14+r13*1+0x10],r8d
    31:	48 31 c0             	xor    rax,rax
    34:	f0 47 0f b1 44 2e 14 	lock cmpxchg DWORD PTR [r14+r13*1+0x14],r8d
    3b:	48 31 c0             	xor    rax,rax
    3e:	f0 47 0f b1 44 2e 18 	lock cmpxchg DWORD PTR [r14+r13*1+0x18],r8d
    45:	48 31 c0             	xor    rax,rax
    48:	f0 47 0f b1 44 2e 1c 	lock cmpxchg DWORD PTR [r14+r13*1+0x1c],r8d
    4f:	48 31 c0             	xor    rax,rax
    52:	f0 47 0f b1 44 2e 20 	lock cmpxchg DWORD PTR [r14+r13*1+0x20],r8d
    59:	48 31 c0             	xor    rax,rax
    5c:	f0 47 0f b1 44 2e 24 	lock cmpxchg DWORD PTR [r14+r13*1+0x24],r8d
    63:	48 31 c0             	xor    rax,rax
    66:	f0 47 0f b1 44 2e 28 	lock cmpxchg DWORD PTR [r14+r13*1+0x28],r8d
    6d:	48 31 c0             	xor    rax,rax
    70:	f0 47 0f b1 44 2e 2c 	lock cmpxchg DWORD PTR [r14+r13*1+0x2c],r8d
    77:	48 31 c0             	xor    rax,rax
    7a:	f0 47 0f b1 44 2e 30 	lock cmpxchg DWORD PTR [r14+r13*1+0x30],r8d
    81:	48 31 c0             	xor    rax,rax
    84:	f0 47 0f b1 44 2e 34 	lock cmpxchg DWORD PTR [r14+r13*1+0x34],r8d
    8b:	48 31 c0             	xor    rax,rax
    8e:	f0 47 0f b1 44 2e 38 	lock cmpxchg DWORD PTR [r14+r13*1+0x38],r8d
    95:	48 31 c0             	xor    rax,rax
    98:	f0 47 0f b1 44 2e 3c 	lock cmpxchg DWORD PTR [r14+r13*1+0x3c],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 34.0
  • Core cycles: 333.41
  • Reference cycles: 236.49
  • UOPS_EXECUTED.THREAD: 129.0
  • RETIRE_SLOTS: 177.01
  • UOPS_MITE: 17.0
  • UOPS_MS: 160.06
  • UOPS_PORT_0: 27.93
  • UOPS_PORT_1: 26.78
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 29.57
  • UOPS_PORT_6: 42.76
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.01

With loop_count=100 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	f0 47 0f b1 04 2e    	lock cmpxchg DWORD PTR [r14+r13*1],r8d
     9:	48 31 c0             	xor    rax,rax
     c:	f0 47 0f b1 44 2e 04 	lock cmpxchg DWORD PTR [r14+r13*1+0x4],r8d
    13:	48 31 c0             	xor    rax,rax
    16:	f0 47 0f b1 44 2e 08 	lock cmpxchg DWORD PTR [r14+r13*1+0x8],r8d
    1d:	48 31 c0             	xor    rax,rax
    20:	f0 47 0f b1 44 2e 0c 	lock cmpxchg DWORD PTR [r14+r13*1+0xc],r8d
    27:	48 31 c0             	xor    rax,rax
    2a:	f0 47 0f b1 44 2e 10 	lock cmpxchg DWORD PTR [r14+r13*1+0x10],r8d
    31:	48 31 c0             	xor    rax,rax
    34:	f0 47 0f b1 44 2e 14 	lock cmpxchg DWORD PTR [r14+r13*1+0x14],r8d
    3b:	48 31 c0             	xor    rax,rax
    3e:	f0 47 0f b1 44 2e 18 	lock cmpxchg DWORD PTR [r14+r13*1+0x18],r8d
    45:	48 31 c0             	xor    rax,rax
    48:	f0 47 0f b1 44 2e 1c 	lock cmpxchg DWORD PTR [r14+r13*1+0x1c],r8d
    4f:	48 31 c0             	xor    rax,rax
    52:	f0 47 0f b1 44 2e 20 	lock cmpxchg DWORD PTR [r14+r13*1+0x20],r8d
    59:	48 31 c0             	xor    rax,rax
    5c:	f0 47 0f b1 44 2e 24 	lock cmpxchg DWORD PTR [r14+r13*1+0x24],r8d
    63:	48 31 c0             	xor    rax,rax
    66:	f0 47 0f b1 44 2e 28 	lock cmpxchg DWORD PTR [r14+r13*1+0x28],r8d
    6d:	48 31 c0             	xor    rax,rax
    70:	f0 47 0f b1 44 2e 2c 	lock cmpxchg DWORD PTR [r14+r13*1+0x2c],r8d
    77:	48 31 c0             	xor    rax,rax
    7a:	f0 47 0f b1 44 2e 30 	lock cmpxchg DWORD PTR [r14+r13*1+0x30],r8d
    81:	48 31 c0             	xor    rax,rax
    84:	f0 47 0f b1 44 2e 34 	lock cmpxchg DWORD PTR [r14+r13*1+0x34],r8d
    8b:	48 31 c0             	xor    rax,rax
    8e:	f0 47 0f b1 44 2e 38 	lock cmpxchg DWORD PTR [r14+r13*1+0x38],r8d
    95:	48 31 c0             	xor    rax,rax
    98:	f0 47 0f b1 44 2e 3c 	lock cmpxchg DWORD PTR [r14+r13*1+0x3c],r8d
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 32.2
  • Core cycles: 335.71
  • Reference cycles: 236.99
  • UOPS_EXECUTED.THREAD: 128.1
  • RETIRE_SLOTS: 176.1
  • UOPS_MITE: 16.11
  • UOPS_MS: 160.05
  • UOPS_PORT_0: 27.9
  • UOPS_PORT_1: 28.13
  • UOPS_PORT_2: 15.99
  • UOPS_PORT_3: 16.01
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 28.59
  • UOPS_PORT_6: 42.75
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.01