VPSHUFB_EVEX (YMM, YMM, YMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f2 75 28 00 c2    	vpshufb ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f2 75 28 00 c2    	vpshufb ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.9
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 1.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.3

With loop_count=100 and unroll_count=100

Code:

   0:	62 f2 75 28 00 c2    	vpshufb ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.91
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f2 75 28 00 c2    	vpshufb ymm0,ymm1,ymm2
   6:	62 f2 75 28 00 da    	vpshufb ymm3,ymm1,ymm2
   c:	62 f2 75 28 00 e2    	vpshufb ymm4,ymm1,ymm2
  12:	62 f2 75 28 00 ea    	vpshufb ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.75
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f2 75 28 00 c2    	vpshufb ymm0,ymm1,ymm2
   6:	62 f2 75 28 00 da    	vpshufb ymm3,ymm1,ymm2
   c:	62 f2 75 28 00 e2    	vpshufb ymm4,ymm1,ymm2
  12:	62 f2 75 28 00 ea    	vpshufb ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 3.0
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f2 75 28 00 c2    	vpshufb ymm0,ymm1,ymm2
   6:	62 f2 75 28 00 da    	vpshufb ymm3,ymm1,ymm2
   c:	62 f2 75 28 00 e2    	vpshufb ymm4,ymm1,ymm2
  12:	62 f2 75 28 00 ea    	vpshufb ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 3.0
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 75 28 00 c2    	vpshufb ymm0,ymm1,ymm2
   6:	62 f2 75 28 00 da    	vpshufb ymm3,ymm1,ymm2
   c:	62 f2 75 28 00 e2    	vpshufb ymm4,ymm1,ymm2
  12:	62 f2 75 28 00 ea    	vpshufb ymm5,ymm1,ymm2
  18:	62 f2 75 28 00 f2    	vpshufb ymm6,ymm1,ymm2
  1e:	62 f2 75 28 00 fa    	vpshufb ymm7,ymm1,ymm2
  24:	62 72 75 28 00 c2    	vpshufb ymm8,ymm1,ymm2
  2a:	62 72 75 28 00 ca    	vpshufb ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 6.04
- UOPS_EXECUTED.THREAD: 7.99
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 75 28 00 c2    	vpshufb ymm0,ymm1,ymm2
   6:	62 f2 75 28 00 da    	vpshufb ymm3,ymm1,ymm2
   c:	62 f2 75 28 00 e2    	vpshufb ymm4,ymm1,ymm2
  12:	62 f2 75 28 00 ea    	vpshufb ymm5,ymm1,ymm2
  18:	62 f2 75 28 00 f2    	vpshufb ymm6,ymm1,ymm2
  1e:	62 f2 75 28 00 fa    	vpshufb ymm7,ymm1,ymm2
  24:	62 72 75 28 00 c2    	vpshufb ymm8,ymm1,ymm2
  2a:	62 72 75 28 00 ca    	vpshufb ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 6.0
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 75 28 00 c2    	vpshufb ymm0,ymm1,ymm2
   6:	62 f2 75 28 00 da    	vpshufb ymm3,ymm1,ymm2
   c:	62 f2 75 28 00 e2    	vpshufb ymm4,ymm1,ymm2
  12:	62 f2 75 28 00 ea    	vpshufb ymm5,ymm1,ymm2
  18:	62 f2 75 28 00 f2    	vpshufb ymm6,ymm1,ymm2
  1e:	62 f2 75 28 00 fa    	vpshufb ymm7,ymm1,ymm2
  24:	62 72 75 28 00 c2    	vpshufb ymm8,ymm1,ymm2
  2a:	62 72 75 28 00 ca    	vpshufb ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.0
- Reference cycles: 6.0
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.09
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 75 28 00 c2    	vpshufb ymm0,ymm1,ymm2
   6:	62 f2 75 28 00 da    	vpshufb ymm3,ymm1,ymm2
   c:	62 f2 75 28 00 e2    	vpshufb ymm4,ymm1,ymm2
  12:	62 f2 75 28 00 ea    	vpshufb ymm5,ymm1,ymm2
  18:	62 f2 75 28 00 f2    	vpshufb ymm6,ymm1,ymm2
  1e:	62 f2 75 28 00 fa    	vpshufb ymm7,ymm1,ymm2
  24:	62 72 75 28 00 c2    	vpshufb ymm8,ymm1,ymm2
  2a:	62 72 75 28 00 ca    	vpshufb ymm9,ymm1,ymm2
  30:	62 72 75 28 00 d2    	vpshufb ymm10,ymm1,ymm2
  36:	62 72 75 28 00 da    	vpshufb ymm11,ymm1,ymm2
  3c:	62 72 75 28 00 e2    	vpshufb ymm12,ymm1,ymm2
  42:	62 e2 75 28 00 c2    	vpshufb ymm16,ymm1,ymm2
  48:	62 e2 75 28 00 ca    	vpshufb ymm17,ymm1,ymm2
  4e:	62 e2 75 28 00 d2    	vpshufb ymm18,ymm1,ymm2
  54:	62 e2 75 28 00 da    	vpshufb ymm19,ymm1,ymm2
  5a:	62 e2 75 28 00 e2    	vpshufb ymm20,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 11.25
- UOPS_EXECUTED.THREAD: 16.02
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 75 28 00 c2    	vpshufb ymm0,ymm1,ymm2
   6:	62 f2 75 28 00 da    	vpshufb ymm3,ymm1,ymm2
   c:	62 f2 75 28 00 e2    	vpshufb ymm4,ymm1,ymm2
  12:	62 f2 75 28 00 ea    	vpshufb ymm5,ymm1,ymm2
  18:	62 f2 75 28 00 f2    	vpshufb ymm6,ymm1,ymm2
  1e:	62 f2 75 28 00 fa    	vpshufb ymm7,ymm1,ymm2
  24:	62 72 75 28 00 c2    	vpshufb ymm8,ymm1,ymm2
  2a:	62 72 75 28 00 ca    	vpshufb ymm9,ymm1,ymm2
  30:	62 72 75 28 00 d2    	vpshufb ymm10,ymm1,ymm2
  36:	62 72 75 28 00 da    	vpshufb ymm11,ymm1,ymm2
  3c:	62 72 75 28 00 e2    	vpshufb ymm12,ymm1,ymm2
  42:	62 e2 75 28 00 c2    	vpshufb ymm16,ymm1,ymm2
  48:	62 e2 75 28 00 ca    	vpshufb ymm17,ymm1,ymm2
  4e:	62 e2 75 28 00 d2    	vpshufb ymm18,ymm1,ymm2
  54:	62 e2 75 28 00 da    	vpshufb ymm19,ymm1,ymm2
  5a:	62 e2 75 28 00 e2    	vpshufb ymm20,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.0
- Reference cycles: 13.0
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 75 28 00 c2    	vpshufb ymm0,ymm1,ymm2
   6:	62 f2 75 28 00 da    	vpshufb ymm3,ymm1,ymm2
   c:	62 f2 75 28 00 e2    	vpshufb ymm4,ymm1,ymm2
  12:	62 f2 75 28 00 ea    	vpshufb ymm5,ymm1,ymm2
  18:	62 f2 75 28 00 f2    	vpshufb ymm6,ymm1,ymm2
  1e:	62 f2 75 28 00 fa    	vpshufb ymm7,ymm1,ymm2
  24:	62 72 75 28 00 c2    	vpshufb ymm8,ymm1,ymm2
  2a:	62 72 75 28 00 ca    	vpshufb ymm9,ymm1,ymm2
  30:	62 72 75 28 00 d2    	vpshufb ymm10,ymm1,ymm2
  36:	62 72 75 28 00 da    	vpshufb ymm11,ymm1,ymm2
  3c:	62 72 75 28 00 e2    	vpshufb ymm12,ymm1,ymm2
  42:	62 e2 75 28 00 c2    	vpshufb ymm16,ymm1,ymm2
  48:	62 e2 75 28 00 ca    	vpshufb ymm17,ymm1,ymm2
  4e:	62 e2 75 28 00 d2    	vpshufb ymm18,ymm1,ymm2
  54:	62 e2 75 28 00 da    	vpshufb ymm19,ymm1,ymm2
  5a:	62 e2 75 28 00 e2    	vpshufb ymm20,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.0
- Reference cycles: 12.0
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 16.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With the same register for for different operands

With unroll_count=500 and no inner loop

Code:

   0:	62 f2 7d 28 00 c0    	vpshufb ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f2 7d 28 00 c0    	vpshufb ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.79
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 1.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.3

With loop_count=100 and unroll_count=100

Code:

   0:	62 f2 7d 28 00 c0    	vpshufb ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

VPSHUFB_EVEX (YMM, YMM, YMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100