VPMULLQ (YMM, YMM, YMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.5
- Reference cycles: 1.17
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.5
- UOPS_PORT_1: 1.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.5
- Reference cycles: 1.21
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.5
- UOPS_PORT_1: 1.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 2.0
- Reference cycles: 1.5
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.5
- UOPS_PORT_1: 1.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.5
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.5
- UOPS_PORT_1: 1.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.5
- Reference cycles: 1.13
- UOPS_EXECUTED.THREAD: 3.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 3.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.5
- UOPS_PORT_1: 1.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.5
- Reference cycles: 1.19
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.5
- UOPS_PORT_1: 1.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2
   6:	62 f2 f5 28 40 da    	vpmullq ymm3,ymm1,ymm2
   c:	62 f2 f5 28 40 e2    	vpmullq ymm4,ymm1,ymm2
  12:	62 f2 f5 28 40 ea    	vpmullq ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.0
- Reference cycles: 4.69
- UOPS_EXECUTED.THREAD: 12.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.0
- UOPS_PORT_1: 6.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2
   6:	62 f2 f5 28 40 da    	vpmullq ymm3,ymm1,ymm2
   c:	62 f2 f5 28 40 e2    	vpmullq ymm4,ymm1,ymm2
  12:	62 f2 f5 28 40 ea    	vpmullq ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 6.01
- Reference cycles: 4.5
- UOPS_EXECUTED.THREAD: 12.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.0
- UOPS_PORT_1: 6.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With loop_count=100 and unroll_count=20

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2
   6:	62 f2 f5 28 40 da    	vpmullq ymm3,ymm1,ymm2
   c:	62 f2 f5 28 40 e2    	vpmullq ymm4,ymm1,ymm2
  12:	62 f2 f5 28 40 ea    	vpmullq ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 6.01
- Reference cycles: 4.5
- UOPS_EXECUTED.THREAD: 12.05
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.0
- UOPS_PORT_1: 6.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2
   6:	62 f2 f5 28 40 da    	vpmullq ymm3,ymm1,ymm2
   c:	62 f2 f5 28 40 e2    	vpmullq ymm4,ymm1,ymm2
  12:	62 f2 f5 28 40 ea    	vpmullq ymm5,ymm1,ymm2
  18:	62 f2 f5 28 40 f2    	vpmullq ymm6,ymm1,ymm2
  1e:	62 f2 f5 28 40 fa    	vpmullq ymm7,ymm1,ymm2
  24:	62 72 f5 28 40 c2    	vpmullq ymm8,ymm1,ymm2
  2a:	62 72 f5 28 40 ca    	vpmullq ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.0
- Reference cycles: 9.38
- UOPS_EXECUTED.THREAD: 24.01
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 24.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2
   6:	62 f2 f5 28 40 da    	vpmullq ymm3,ymm1,ymm2
   c:	62 f2 f5 28 40 e2    	vpmullq ymm4,ymm1,ymm2
  12:	62 f2 f5 28 40 ea    	vpmullq ymm5,ymm1,ymm2
  18:	62 f2 f5 28 40 f2    	vpmullq ymm6,ymm1,ymm2
  1e:	62 f2 f5 28 40 fa    	vpmullq ymm7,ymm1,ymm2
  24:	62 72 f5 28 40 c2    	vpmullq ymm8,ymm1,ymm2
  2a:	62 72 f5 28 40 ca    	vpmullq ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 12.02
- Reference cycles: 9.0
- UOPS_EXECUTED.THREAD: 25.0
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.24
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2
   6:	62 f2 f5 28 40 da    	vpmullq ymm3,ymm1,ymm2
   c:	62 f2 f5 28 40 e2    	vpmullq ymm4,ymm1,ymm2
  12:	62 f2 f5 28 40 ea    	vpmullq ymm5,ymm1,ymm2
  18:	62 f2 f5 28 40 f2    	vpmullq ymm6,ymm1,ymm2
  1e:	62 f2 f5 28 40 fa    	vpmullq ymm7,ymm1,ymm2
  24:	62 72 f5 28 40 c2    	vpmullq ymm8,ymm1,ymm2
  2a:	62 72 f5 28 40 ca    	vpmullq ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 12.02
- Reference cycles: 9.0
- UOPS_EXECUTED.THREAD: 24.1
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.25
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2
   6:	62 f2 f5 28 40 da    	vpmullq ymm3,ymm1,ymm2
   c:	62 f2 f5 28 40 e2    	vpmullq ymm4,ymm1,ymm2
  12:	62 f2 f5 28 40 ea    	vpmullq ymm5,ymm1,ymm2
  18:	62 f2 f5 28 40 f2    	vpmullq ymm6,ymm1,ymm2
  1e:	62 f2 f5 28 40 fa    	vpmullq ymm7,ymm1,ymm2
  24:	62 72 f5 28 40 c2    	vpmullq ymm8,ymm1,ymm2
  2a:	62 72 f5 28 40 ca    	vpmullq ymm9,ymm1,ymm2
  30:	62 72 f5 28 40 d2    	vpmullq ymm10,ymm1,ymm2
  36:	62 72 f5 28 40 da    	vpmullq ymm11,ymm1,ymm2
  3c:	62 72 f5 28 40 e2    	vpmullq ymm12,ymm1,ymm2
  42:	62 e2 f5 28 40 c2    	vpmullq ymm16,ymm1,ymm2
  48:	62 e2 f5 28 40 ca    	vpmullq ymm17,ymm1,ymm2
  4e:	62 e2 f5 28 40 d2    	vpmullq ymm18,ymm1,ymm2
  54:	62 e2 f5 28 40 da    	vpmullq ymm19,ymm1,ymm2
  5a:	62 e2 f5 28 40 e2    	vpmullq ymm20,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 24.0
- Reference cycles: 18.13
- UOPS_EXECUTED.THREAD: 47.99
- RETIRE_SLOTS: 48.0
- UOPS_MITE: 48.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 24.0
- UOPS_PORT_1: 24.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2
   6:	62 f2 f5 28 40 da    	vpmullq ymm3,ymm1,ymm2
   c:	62 f2 f5 28 40 e2    	vpmullq ymm4,ymm1,ymm2
  12:	62 f2 f5 28 40 ea    	vpmullq ymm5,ymm1,ymm2
  18:	62 f2 f5 28 40 f2    	vpmullq ymm6,ymm1,ymm2
  1e:	62 f2 f5 28 40 fa    	vpmullq ymm7,ymm1,ymm2
  24:	62 72 f5 28 40 c2    	vpmullq ymm8,ymm1,ymm2
  2a:	62 72 f5 28 40 ca    	vpmullq ymm9,ymm1,ymm2
  30:	62 72 f5 28 40 d2    	vpmullq ymm10,ymm1,ymm2
  36:	62 72 f5 28 40 da    	vpmullq ymm11,ymm1,ymm2
  3c:	62 72 f5 28 40 e2    	vpmullq ymm12,ymm1,ymm2
  42:	62 e2 f5 28 40 c2    	vpmullq ymm16,ymm1,ymm2
  48:	62 e2 f5 28 40 ca    	vpmullq ymm17,ymm1,ymm2
  4e:	62 e2 f5 28 40 d2    	vpmullq ymm18,ymm1,ymm2
  54:	62 e2 f5 28 40 da    	vpmullq ymm19,ymm1,ymm2
  5a:	62 e2 f5 28 40 e2    	vpmullq ymm20,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 24.02
- Reference cycles: 18.0
- UOPS_EXECUTED.THREAD: 49.0
- RETIRE_SLOTS: 49.0
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 24.0
- UOPS_PORT_1: 24.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 f5 28 40 c2    	vpmullq ymm0,ymm1,ymm2
   6:	62 f2 f5 28 40 da    	vpmullq ymm3,ymm1,ymm2
   c:	62 f2 f5 28 40 e2    	vpmullq ymm4,ymm1,ymm2
  12:	62 f2 f5 28 40 ea    	vpmullq ymm5,ymm1,ymm2
  18:	62 f2 f5 28 40 f2    	vpmullq ymm6,ymm1,ymm2
  1e:	62 f2 f5 28 40 fa    	vpmullq ymm7,ymm1,ymm2
  24:	62 72 f5 28 40 c2    	vpmullq ymm8,ymm1,ymm2
  2a:	62 72 f5 28 40 ca    	vpmullq ymm9,ymm1,ymm2
  30:	62 72 f5 28 40 d2    	vpmullq ymm10,ymm1,ymm2
  36:	62 72 f5 28 40 da    	vpmullq ymm11,ymm1,ymm2
  3c:	62 72 f5 28 40 e2    	vpmullq ymm12,ymm1,ymm2
  42:	62 e2 f5 28 40 c2    	vpmullq ymm16,ymm1,ymm2
  48:	62 e2 f5 28 40 ca    	vpmullq ymm17,ymm1,ymm2
  4e:	62 e2 f5 28 40 d2    	vpmullq ymm18,ymm1,ymm2
  54:	62 e2 f5 28 40 da    	vpmullq ymm19,ymm1,ymm2
  5a:	62 e2 f5 28 40 e2    	vpmullq ymm20,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 24.02
- Reference cycles: 18.0
- UOPS_EXECUTED.THREAD: 48.1
- RETIRE_SLOTS: 48.1
- UOPS_MITE: 0.48
- UOPS_MS: 0.0
- UOPS_PORT_0: 24.0
- UOPS_PORT_1: 24.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With the same register for for different operands

With unroll_count=500 and no inner loop

Code:

   0:	62 f2 fd 28 40 c0    	vpmullq ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 15.0
- Reference cycles: 11.25
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.49
- UOPS_PORT_1: 1.51
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 f2 fd 28 40 c0    	vpmullq ymm0,ymm0,ymm0
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 15.0
- Reference cycles: 11.25
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.49
- UOPS_PORT_1: 1.52
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 f2 fd 28 40 c0    	vpmullq ymm0,ymm0,ymm0
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 15.0
- Reference cycles: 11.25
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.5
- UOPS_PORT_1: 1.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 f2 fd 28 40 c0    	vpmullq ymm0,ymm0,ymm0
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 15.0
- Reference cycles: 11.25
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.5
- UOPS_PORT_1: 1.5
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f2 fd 28 40 c0    	vpmullq ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 15.0
- Reference cycles: 11.25
- UOPS_EXECUTED.THREAD: 3.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 3.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.49
- UOPS_PORT_1: 1.51
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f2 fd 28 40 c0    	vpmullq ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 15.0
- Reference cycles: 11.25
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.49
- UOPS_PORT_1: 1.51
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

VPMULLQ (YMM, YMM, YMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100