RSQRTSS (XMM, XMM) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 4.0
  • Reference cycles: 3.08
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.25

With unroll_count=500 and no inner loop

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
     4:	0f ae e8             	lfence 
  

• Init:

  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 14.5
  • Reference cycles: 10.38
  • UOPS_EXECUTED.THREAD: 1.01
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 2.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 4.0
  • Reference cycles: 2.73
  • UOPS_EXECUTED.THREAD: 1.1
  • RETIRE_SLOTS: 1.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 4.0
  • Reference cycles: 2.73
  • UOPS_EXECUTED.THREAD: 1.01
  • RETIRE_SLOTS: 1.01
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With unroll_count=200 and no inner loop

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
     4:	f3 0f 52 d8          	rsqrtss xmm3,xmm0
     8:	f3 0f 52 e0          	rsqrtss xmm4,xmm0
     c:	f3 0f 52 e8          	rsqrtss xmm5,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 4.0
  • Reference cycles: 2.5
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
     4:	f3 0f 52 d8          	rsqrtss xmm3,xmm0
     8:	f3 0f 52 e0          	rsqrtss xmm4,xmm0
     c:	f3 0f 52 e8          	rsqrtss xmm5,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 4.0
  • Reference cycles: 2.61
  • UOPS_EXECUTED.THREAD: 4.5
  • RETIRE_SLOTS: 4.5
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.03

With loop_count=100 and unroll_count=20

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
     4:	f3 0f 52 d8          	rsqrtss xmm3,xmm0
     8:	f3 0f 52 e0          	rsqrtss xmm4,xmm0
     c:	f3 0f 52 e8          	rsqrtss xmm5,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 4.0
  • Reference cycles: 3.19
  • UOPS_EXECUTED.THREAD: 4.05
  • RETIRE_SLOTS: 4.05
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=100 and no inner loop

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
     4:	f3 0f 52 d8          	rsqrtss xmm3,xmm0
     8:	f3 0f 52 e0          	rsqrtss xmm4,xmm0
     c:	f3 0f 52 e8          	rsqrtss xmm5,xmm0
    10:	f3 0f 52 f0          	rsqrtss xmm6,xmm0
    14:	f3 0f 52 f8          	rsqrtss xmm7,xmm0
    18:	f3 44 0f 52 c0       	rsqrtss xmm8,xmm0
    1d:	f3 44 0f 52 c8       	rsqrtss xmm9,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 8.0
  • Reference cycles: 5.0
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
     4:	f3 0f 52 d8          	rsqrtss xmm3,xmm0
     8:	f3 0f 52 e0          	rsqrtss xmm4,xmm0
     c:	f3 0f 52 e8          	rsqrtss xmm5,xmm0
    10:	f3 0f 52 f0          	rsqrtss xmm6,xmm0
    14:	f3 0f 52 f8          	rsqrtss xmm7,xmm0
    18:	f3 44 0f 52 c0       	rsqrtss xmm8,xmm0
    1d:	f3 44 0f 52 c8       	rsqrtss xmm9,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 8.01
  • Reference cycles: 6.17
  • UOPS_EXECUTED.THREAD: 9.0
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 0.09
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.03

With loop_count=100 and unroll_count=10

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
     4:	f3 0f 52 d8          	rsqrtss xmm3,xmm0
     8:	f3 0f 52 e0          	rsqrtss xmm4,xmm0
     c:	f3 0f 52 e8          	rsqrtss xmm5,xmm0
    10:	f3 0f 52 f0          	rsqrtss xmm6,xmm0
    14:	f3 0f 52 f8          	rsqrtss xmm7,xmm0
    18:	f3 44 0f 52 c0       	rsqrtss xmm8,xmm0
    1d:	f3 44 0f 52 c8       	rsqrtss xmm9,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x3f8000003f800000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 8.01
  • Reference cycles: 5.25
  • UOPS_EXECUTED.THREAD: 8.1
  • RETIRE_SLOTS: 8.1
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.02

With unroll_count=500 and no inner loop

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 4.0
  • Reference cycles: 2.75
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.25

With unroll_count=500 and no inner loop

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
     4:	0f ae e8             	lfence 
  

• Init:

  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 14.5
  • Reference cycles: 9.5
  • UOPS_EXECUTED.THREAD: 1.01
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 2.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 4.0
  • Reference cycles: 2.79
  • UOPS_EXECUTED.THREAD: 1.1
  • RETIRE_SLOTS: 1.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 4.0
  • Reference cycles: 2.6
  • UOPS_EXECUTED.THREAD: 1.01
  • RETIRE_SLOTS: 1.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With unroll_count=200 and no inner loop

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
     4:	f3 0f 52 d8          	rsqrtss xmm3,xmm0
     8:	f3 0f 52 e0          	rsqrtss xmm4,xmm0
     c:	f3 0f 52 e8          	rsqrtss xmm5,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 4.0
  • Reference cycles: 2.5
  • UOPS_EXECUTED.THREAD: 3.99
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
     4:	f3 0f 52 d8          	rsqrtss xmm3,xmm0
     8:	f3 0f 52 e0          	rsqrtss xmm4,xmm0
     c:	f3 0f 52 e8          	rsqrtss xmm5,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 4.0
  • Reference cycles: 2.59
  • UOPS_EXECUTED.THREAD: 4.5
  • RETIRE_SLOTS: 4.5
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
     4:	f3 0f 52 d8          	rsqrtss xmm3,xmm0
     8:	f3 0f 52 e0          	rsqrtss xmm4,xmm0
     c:	f3 0f 52 e8          	rsqrtss xmm5,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 4.0
  • Reference cycles: 2.8
  • UOPS_EXECUTED.THREAD: 4.05
  • RETIRE_SLOTS: 4.05
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=100 and no inner loop

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
     4:	f3 0f 52 d8          	rsqrtss xmm3,xmm0
     8:	f3 0f 52 e0          	rsqrtss xmm4,xmm0
     c:	f3 0f 52 e8          	rsqrtss xmm5,xmm0
    10:	f3 0f 52 f0          	rsqrtss xmm6,xmm0
    14:	f3 0f 52 f8          	rsqrtss xmm7,xmm0
    18:	f3 44 0f 52 c0       	rsqrtss xmm8,xmm0
    1d:	f3 44 0f 52 c8       	rsqrtss xmm9,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 8.0
  • Reference cycles: 5.0
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
     4:	f3 0f 52 d8          	rsqrtss xmm3,xmm0
     8:	f3 0f 52 e0          	rsqrtss xmm4,xmm0
     c:	f3 0f 52 e8          	rsqrtss xmm5,xmm0
    10:	f3 0f 52 f0          	rsqrtss xmm6,xmm0
    14:	f3 0f 52 f8          	rsqrtss xmm7,xmm0
    18:	f3 44 0f 52 c0       	rsqrtss xmm8,xmm0
    1d:	f3 44 0f 52 c8       	rsqrtss xmm9,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 8.01
  • Reference cycles: 5.56
  • UOPS_EXECUTED.THREAD: 9.0
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 0.09
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.03

With loop_count=100 and unroll_count=10

• Code:

     0:	f3 0f 52 d0          	rsqrtss xmm2,xmm0
     4:	f3 0f 52 d8          	rsqrtss xmm3,xmm0
     8:	f3 0f 52 e0          	rsqrtss xmm4,xmm0
     c:	f3 0f 52 e8          	rsqrtss xmm5,xmm0
    10:	f3 0f 52 f0          	rsqrtss xmm6,xmm0
    14:	f3 0f 52 f8          	rsqrtss xmm7,xmm0
    18:	f3 44 0f 52 c0       	rsqrtss xmm8,xmm0
    1d:	f3 44 0f 52 c8       	rsqrtss xmm9,xmm0
  

• Init:

  VZEROALL;
  MOV RAX, 0x72d30ff172d30ff1;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPS XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 8.01
  • Reference cycles: 5.17
  • UOPS_EXECUTED.THREAD: 8.1
  • RETIRE_SLOTS: 8.1
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.02