RDMSR - Throughput and Uops
With unroll_count=500 and no inner loop
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.0
- Core cycles: 57.0
- Reference cycles: 38.88
- UOPS_EXECUTED.THREAD: 85.01
- RETIRE_SLOTS: 87.0
- UOPS_MITE: 0.0
- UOPS_MS: 87.0
- UOPS_PORT_0: 17.0
- UOPS_PORT_1: 15.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 19.0
- UOPS_PORT_6: 34.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0
With unroll_count=500, no inner loop, and 1 NOP
- Code:
0: 0f 32 rdmsr
2: 90 nop
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 2.0
- Core cycles: 58.0
- Reference cycles: 37.88
- UOPS_EXECUTED.THREAD: 85.0
- RETIRE_SLOTS: 88.0
- UOPS_MITE: 1.0
- UOPS_MS: 87.0
- UOPS_PORT_0: 17.0
- UOPS_PORT_1: 15.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 19.0
- UOPS_PORT_6: 34.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0
With loop_count=1000 and unroll_count=10
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.2
- Core cycles: 57.1
- Reference cycles: 37.24
- UOPS_EXECUTED.THREAD: 85.1
- RETIRE_SLOTS: 87.1
- UOPS_MITE: 0.1
- UOPS_MS: 87.0
- UOPS_PORT_0: 17.3
- UOPS_PORT_1: 15.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 18.7
- UOPS_PORT_6: 34.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.1
With loop_count=100 and unroll_count=100
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.02
- Core cycles: 57.01
- Reference cycles: 37.18
- UOPS_EXECUTED.THREAD: 85.01
- RETIRE_SLOTS: 87.01
- UOPS_MITE: 0.01
- UOPS_MS: 87.0
- UOPS_PORT_0: 17.03
- UOPS_PORT_1: 15.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 18.97
- UOPS_PORT_6: 34.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01