POPCNT (R64, R64) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 1.96
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.0
- Reference cycles: 1.83
- UOPS_EXECUTED.THREAD: 0.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	90                   	nop
   6:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 3.0
- Reference cycles: 1.96
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 3.0
- Reference cycles: 1.96
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 3.0
- Reference cycles: 2.08
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.0
- Reference cycles: 1.95
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.0
- Reference cycles: 1.95
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	f3 4d 0f b8 d1       	popcnt r10,r9
   a:	f3 4d 0f b8 d9       	popcnt r11,r9
   f:	f3 4d 0f b8 e1       	popcnt r12,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.5
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	f3 4d 0f b8 d1       	popcnt r10,r9
   a:	f3 4d 0f b8 d9       	popcnt r11,r9
   f:	f3 4d 0f b8 e1       	popcnt r12,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 2.7
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	f3 4d 0f b8 d1       	popcnt r10,r9
   a:	f3 4d 0f b8 d9       	popcnt r11,r9
   f:	f3 4d 0f b8 e1       	popcnt r12,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 2.57
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	f3 4d 0f b8 d1       	popcnt r10,r9
   a:	f3 4d 0f b8 d9       	popcnt r11,r9
   f:	f3 4d 0f b8 e1       	popcnt r12,r9
  14:	f3 4d 0f b8 e9       	popcnt r13,r9
  19:	f3 4d 0f b8 f1       	popcnt r14,r9
  1e:	f3 49 0f b8 d9       	popcnt rbx,r9
  23:	f3 49 0f b8 c9       	popcnt rcx,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 5.0
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	f3 4d 0f b8 d1       	popcnt r10,r9
   a:	f3 4d 0f b8 d9       	popcnt r11,r9
   f:	f3 4d 0f b8 e1       	popcnt r12,r9
  14:	f3 4d 0f b8 e9       	popcnt r13,r9
  19:	f3 4d 0f b8 f1       	popcnt r14,r9
  1e:	f3 49 0f b8 d9       	popcnt rbx,r9
  23:	f3 49 0f b8 c9       	popcnt rcx,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.0
- Reference cycles: 5.27
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	f3 4d 0f b8 d1       	popcnt r10,r9
   a:	f3 4d 0f b8 d9       	popcnt r11,r9
   f:	f3 4d 0f b8 e1       	popcnt r12,r9
  14:	f3 4d 0f b8 e9       	popcnt r13,r9
  19:	f3 4d 0f b8 f1       	popcnt r14,r9
  1e:	f3 49 0f b8 d9       	popcnt rbx,r9
  23:	f3 49 0f b8 c9       	popcnt rcx,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.0
- Reference cycles: 5.23
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.09
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	f3 4d 0f b8 d1       	popcnt r10,r9
   a:	f3 4d 0f b8 d9       	popcnt r11,r9
   f:	f3 4d 0f b8 e1       	popcnt r12,r9
  14:	f3 4d 0f b8 e9       	popcnt r13,r9
  19:	f3 4d 0f b8 f1       	popcnt r14,r9
  1e:	f3 49 0f b8 d9       	popcnt rbx,r9
  23:	f3 49 0f b8 c9       	popcnt rcx,r9
  28:	f3 49 0f b8 d1       	popcnt rdx,r9
  2d:	f3 49 0f b8 c1       	popcnt rax,r9
  32:	f3 49 0f b8 f9       	popcnt rdi,r9
  37:	f3 49 0f b8 f1       	popcnt rsi,r9
  3c:	f3 49 0f b8 e9       	popcnt rbp,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 13.0
- Reference cycles: 7.5
- UOPS_EXECUTED.THREAD: 13.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 13.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 13.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 13.0

With loop_count=1000 and unroll_count=1

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	f3 4d 0f b8 d1       	popcnt r10,r9
   a:	f3 4d 0f b8 d9       	popcnt r11,r9
   f:	f3 4d 0f b8 e1       	popcnt r12,r9
  14:	f3 4d 0f b8 e9       	popcnt r13,r9
  19:	f3 4d 0f b8 f1       	popcnt r14,r9
  1e:	f3 49 0f b8 d9       	popcnt rbx,r9
  23:	f3 49 0f b8 c9       	popcnt rcx,r9
  28:	f3 49 0f b8 d1       	popcnt rdx,r9
  2d:	f3 49 0f b8 c1       	popcnt rax,r9
  32:	f3 49 0f b8 f9       	popcnt rdi,r9
  37:	f3 49 0f b8 f1       	popcnt rsi,r9
  3c:	f3 49 0f b8 e9       	popcnt rbp,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 13.0
- Reference cycles: 8.5
- UOPS_EXECUTED.THREAD: 14.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 13.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	f3 4d 0f b8 d1       	popcnt r10,r9
   a:	f3 4d 0f b8 d9       	popcnt r11,r9
   f:	f3 4d 0f b8 e1       	popcnt r12,r9
  14:	f3 4d 0f b8 e9       	popcnt r13,r9
  19:	f3 4d 0f b8 f1       	popcnt r14,r9
  1e:	f3 49 0f b8 d9       	popcnt rbx,r9
  23:	f3 49 0f b8 c9       	popcnt rcx,r9
  28:	f3 49 0f b8 d1       	popcnt rdx,r9
  2d:	f3 49 0f b8 c1       	popcnt rax,r9
  32:	f3 49 0f b8 f9       	popcnt rdi,r9
  37:	f3 49 0f b8 f1       	popcnt rsi,r9
  3c:	f3 49 0f b8 e9       	popcnt rbp,r9

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 13.0
- Reference cycles: 8.46
- UOPS_EXECUTED.THREAD: 13.1
- RETIRE_SLOTS: 13.1
- UOPS_MITE: 0.13
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 13.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.13

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 1.92
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8
   5:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.0
- Reference cycles: 1.88
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8
   5:	90                   	nop
   6:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 3.0
- Reference cycles: 1.92
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 3.0
- Reference cycles: 1.88
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 3.0
- Reference cycles: 1.96
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.0
- Reference cycles: 1.95
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.0
- Reference cycles: 1.96
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8
   5:	f3 4d 0f b8 c9       	popcnt r9,r9
   a:	f3 4d 0f b8 d2       	popcnt r10,r10
   f:	f3 4d 0f b8 db       	popcnt r11,r11

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.5
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8
   5:	f3 4d 0f b8 c9       	popcnt r9,r9
   a:	f3 4d 0f b8 d2       	popcnt r10,r10
   f:	f3 4d 0f b8 db       	popcnt r11,r11

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 2.63
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8
   5:	f3 4d 0f b8 c9       	popcnt r9,r9
   a:	f3 4d 0f b8 d2       	popcnt r10,r10
   f:	f3 4d 0f b8 db       	popcnt r11,r11

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 2.56
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8
   5:	f3 4d 0f b8 c9       	popcnt r9,r9
   a:	f3 4d 0f b8 d2       	popcnt r10,r10
   f:	f3 4d 0f b8 db       	popcnt r11,r11
  14:	f3 4d 0f b8 e4       	popcnt r12,r12
  19:	f3 4d 0f b8 ed       	popcnt r13,r13
  1e:	f3 4d 0f b8 f6       	popcnt r14,r14
  23:	f3 48 0f b8 db       	popcnt rbx,rbx

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 5.0
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8
   5:	f3 4d 0f b8 c9       	popcnt r9,r9
   a:	f3 4d 0f b8 d2       	popcnt r10,r10
   f:	f3 4d 0f b8 db       	popcnt r11,r11
  14:	f3 4d 0f b8 e4       	popcnt r12,r12
  19:	f3 4d 0f b8 ed       	popcnt r13,r13
  1e:	f3 4d 0f b8 f6       	popcnt r14,r14
  23:	f3 48 0f b8 db       	popcnt rbx,rbx

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.0
- Reference cycles: 5.25
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8
   5:	f3 4d 0f b8 c9       	popcnt r9,r9
   a:	f3 4d 0f b8 d2       	popcnt r10,r10
   f:	f3 4d 0f b8 db       	popcnt r11,r11
  14:	f3 4d 0f b8 e4       	popcnt r12,r12
  19:	f3 4d 0f b8 ed       	popcnt r13,r13
  1e:	f3 4d 0f b8 f6       	popcnt r14,r14
  23:	f3 48 0f b8 db       	popcnt rbx,rbx

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.0
- Reference cycles: 5.15
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 14 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8
   5:	f3 4d 0f b8 c9       	popcnt r9,r9
   a:	f3 4d 0f b8 d2       	popcnt r10,r10
   f:	f3 4d 0f b8 db       	popcnt r11,r11
  14:	f3 4d 0f b8 e4       	popcnt r12,r12
  19:	f3 4d 0f b8 ed       	popcnt r13,r13
  1e:	f3 4d 0f b8 f6       	popcnt r14,r14
  23:	f3 48 0f b8 db       	popcnt rbx,rbx
  28:	f3 48 0f b8 c9       	popcnt rcx,rcx
  2d:	f3 48 0f b8 d2       	popcnt rdx,rdx
  32:	f3 48 0f b8 c0       	popcnt rax,rax
  37:	f3 48 0f b8 ff       	popcnt rdi,rdi
  3c:	f3 48 0f b8 f6       	popcnt rsi,rsi
  41:	f3 48 0f b8 ed       	popcnt rbp,rbp

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 14.0
- Reference cycles: 9.38
- UOPS_EXECUTED.THREAD: 14.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 14.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 14.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 14.0

With loop_count=1000 and unroll_count=1

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8
   5:	f3 4d 0f b8 c9       	popcnt r9,r9
   a:	f3 4d 0f b8 d2       	popcnt r10,r10
   f:	f3 4d 0f b8 db       	popcnt r11,r11
  14:	f3 4d 0f b8 e4       	popcnt r12,r12
  19:	f3 4d 0f b8 ed       	popcnt r13,r13
  1e:	f3 4d 0f b8 f6       	popcnt r14,r14
  23:	f3 48 0f b8 db       	popcnt rbx,rbx
  28:	f3 48 0f b8 c9       	popcnt rcx,rcx
  2d:	f3 48 0f b8 d2       	popcnt rdx,rdx
  32:	f3 48 0f b8 c0       	popcnt rax,rax
  37:	f3 48 0f b8 ff       	popcnt rdi,rdi
  3c:	f3 48 0f b8 f6       	popcnt rsi,rsi
  41:	f3 48 0f b8 ed       	popcnt rbp,rbp

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 14.0
- Reference cycles: 9.15
- UOPS_EXECUTED.THREAD: 15.0
- RETIRE_SLOTS: 15.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 14.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	f3 4d 0f b8 c0       	popcnt r8,r8
   5:	f3 4d 0f b8 c9       	popcnt r9,r9
   a:	f3 4d 0f b8 d2       	popcnt r10,r10
   f:	f3 4d 0f b8 db       	popcnt r11,r11
  14:	f3 4d 0f b8 e4       	popcnt r12,r12
  19:	f3 4d 0f b8 ed       	popcnt r13,r13
  1e:	f3 4d 0f b8 f6       	popcnt r14,r14
  23:	f3 48 0f b8 db       	popcnt rbx,rbx
  28:	f3 48 0f b8 c9       	popcnt rcx,rcx
  2d:	f3 48 0f b8 d2       	popcnt rdx,rdx
  32:	f3 48 0f b8 c0       	popcnt rax,rax
  37:	f3 48 0f b8 ff       	popcnt rdi,rdi
  3c:	f3 48 0f b8 f6       	popcnt rsi,rsi
  41:	f3 48 0f b8 ed       	popcnt rbp,rbp

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 14.2
- Core cycles: 14.0
- Reference cycles: 9.13
- UOPS_EXECUTED.THREAD: 14.1
- RETIRE_SLOTS: 14.1
- UOPS_MITE: 1.43
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 14.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.33

Tests for macro-fusion

With JB (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 82 00 00 00 00    	jb     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JB (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	72 00                	jb     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.01
- UOPS_PORT_3: 0.02
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JBE (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 86 00 00 00 00    	jbe    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.03
- Reference cycles: 1.25
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.58
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.97
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.79

With JBE (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	76 00                	jbe    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.04
- Reference cycles: 2.29
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.89
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.95
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.97

With JL (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 8c 00 00 00 00    	jl     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.46
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.96
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JL (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	7c 00                	jl     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.96
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JLE (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 8e 00 00 00 00    	jle    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.57
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.01
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.93
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.81

With JLE (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	7e 00                	jle    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.05
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.9
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.03
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.93
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With JNB (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 83 00 00 00 00    	jae    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.05
- Reference cycles: 1.46
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.6
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.03
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.93
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.79

With JNB (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	73 00                	jae    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.05
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 2.02
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.81
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.03
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.95
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.93

With JNBE (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 87 00 00 00 00    	ja     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.06
- Reference cycles: 1.88
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JNBE (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	77 00                	ja     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.03
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.96
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JNL (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 8d 00 00 00 00    	jge    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.03
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.59
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.03
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.8

With JNL (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	7d 00                	jge    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.03
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.9
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.95
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.86

With JNLE (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 8f 00 00 00 00    	jg     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.96
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JNLE (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	7f 00                	jg     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.96
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JNO (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 81 00 00 00 00    	jno    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.46
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.65
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.02
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.96
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.78

With JNO (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	71 00                	jno    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.05
- Reference cycles: 1.46
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.88
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.03
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.93
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.93

With JNP (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 8b 00 00 00 00    	jnp    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.05
- Reference cycles: 1.25
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.45
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.02
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.95
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.81

With JNP (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	7b 00                	jnp    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.03
- Reference cycles: 1.88
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.86
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.03
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.93
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.92

With JNS (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 89 00 00 00 00    	jns    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.05
- Reference cycles: 1.46
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.52
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.02
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.95
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.81

With JNS (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	79 00                	jns    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.05
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.9
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.01
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.93
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.97

With JNZ (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 85 00 00 00 00    	jne    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.46
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JNZ (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	75 00                	jne    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.88
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JO (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 80 00 00 00 00    	jo     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.96
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JO (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	70 00                	jo     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.88
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JP (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 8a 00 00 00 00    	jp     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.96
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JP (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	7a 00                	jp     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.46
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JS (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 88 00 00 00 00    	js     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JS (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	78 00                	js     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.67
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JZ (Rel32)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	0f 84 00 00 00 00    	je     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.02
- Reference cycles: 1.88
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.59
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.01
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.97
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.83

With JZ (Rel8)

Code:

   0:	f3 4d 0f b8 c1       	popcnt r8,r9
   5:	74 00                	je     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.03
- Reference cycles: 1.46
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.9
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.03
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.98