PHMINPOSUW (XMM, XMM)

With unroll_count=500 and no inner loop

Code:

   0:	66 0f 38 41 c1       	phminposuw xmm0,xmm1

Init:
```
VZEROALL;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.71
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	66 0f 38 41 c1       	phminposuw xmm0,xmm1

Init:
```
VZEROALL;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.65
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	66 0f 38 41 c1       	phminposuw xmm0,xmm1

Init:
```
VZEROALL;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.65
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	66 0f 38 41 c1       	phminposuw xmm0,xmm1
   5:	66 0f 38 41 d1       	phminposuw xmm2,xmm1
   a:	66 0f 38 41 d9       	phminposuw xmm3,xmm1
   f:	66 0f 38 41 e1       	phminposuw xmm4,xmm1

Init:
```
VZEROALL;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.92
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	66 0f 38 41 c1       	phminposuw xmm0,xmm1
   5:	66 0f 38 41 d1       	phminposuw xmm2,xmm1
   a:	66 0f 38 41 d9       	phminposuw xmm3,xmm1
   f:	66 0f 38 41 e1       	phminposuw xmm4,xmm1

Init:
```
VZEROALL;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 2.63
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	66 0f 38 41 c1       	phminposuw xmm0,xmm1
   5:	66 0f 38 41 d1       	phminposuw xmm2,xmm1
   a:	66 0f 38 41 d9       	phminposuw xmm3,xmm1
   f:	66 0f 38 41 e1       	phminposuw xmm4,xmm1

Init:
```
VZEROALL;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 2.57
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	66 0f 38 41 c1       	phminposuw xmm0,xmm1
   5:	66 0f 38 41 d1       	phminposuw xmm2,xmm1
   a:	66 0f 38 41 d9       	phminposuw xmm3,xmm1
   f:	66 0f 38 41 e1       	phminposuw xmm4,xmm1
  14:	66 0f 38 41 e9       	phminposuw xmm5,xmm1
  19:	66 0f 38 41 f1       	phminposuw xmm6,xmm1
  1e:	66 0f 38 41 f9       	phminposuw xmm7,xmm1
  23:	66 44 0f 38 41 c1    	phminposuw xmm8,xmm1

Init:
```
VZEROALL;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 5.42
- UOPS_EXECUTED.THREAD: 7.97
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	66 0f 38 41 c1       	phminposuw xmm0,xmm1
   5:	66 0f 38 41 d1       	phminposuw xmm2,xmm1
   a:	66 0f 38 41 d9       	phminposuw xmm3,xmm1
   f:	66 0f 38 41 e1       	phminposuw xmm4,xmm1
  14:	66 0f 38 41 e9       	phminposuw xmm5,xmm1
  19:	66 0f 38 41 f1       	phminposuw xmm6,xmm1
  1e:	66 0f 38 41 f9       	phminposuw xmm7,xmm1
  23:	66 44 0f 38 41 c1    	phminposuw xmm8,xmm1

Init:
```
VZEROALL;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 5.44
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	66 0f 38 41 c1       	phminposuw xmm0,xmm1
   5:	66 0f 38 41 d1       	phminposuw xmm2,xmm1
   a:	66 0f 38 41 d9       	phminposuw xmm3,xmm1
   f:	66 0f 38 41 e1       	phminposuw xmm4,xmm1
  14:	66 0f 38 41 e9       	phminposuw xmm5,xmm1
  19:	66 0f 38 41 f1       	phminposuw xmm6,xmm1
  1e:	66 0f 38 41 f9       	phminposuw xmm7,xmm1
  23:	66 44 0f 38 41 c1    	phminposuw xmm8,xmm1

Init:
```
VZEROALL;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 5.19
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.68
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.09
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.22

With 12 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	66 0f 38 41 c1       	phminposuw xmm0,xmm1
   5:	66 0f 38 41 d1       	phminposuw xmm2,xmm1
   a:	66 0f 38 41 d9       	phminposuw xmm3,xmm1
   f:	66 0f 38 41 e1       	phminposuw xmm4,xmm1
  14:	66 0f 38 41 e9       	phminposuw xmm5,xmm1
  19:	66 0f 38 41 f1       	phminposuw xmm6,xmm1
  1e:	66 0f 38 41 f9       	phminposuw xmm7,xmm1
  23:	66 44 0f 38 41 c1    	phminposuw xmm8,xmm1
  29:	66 44 0f 38 41 c9    	phminposuw xmm9,xmm1
  2f:	66 44 0f 38 41 d1    	phminposuw xmm10,xmm1
  35:	66 44 0f 38 41 d9    	phminposuw xmm11,xmm1
  3b:	66 44 0f 38 41 e1    	phminposuw xmm12,xmm1

Init:
```
VZEROALL;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 11.98
- Reference cycles: 7.5
- UOPS_EXECUTED.THREAD: 12.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.0

With loop_count=1000 and unroll_count=1

Code:

   0:	66 0f 38 41 c1       	phminposuw xmm0,xmm1
   5:	66 0f 38 41 d1       	phminposuw xmm2,xmm1
   a:	66 0f 38 41 d9       	phminposuw xmm3,xmm1
   f:	66 0f 38 41 e1       	phminposuw xmm4,xmm1
  14:	66 0f 38 41 e9       	phminposuw xmm5,xmm1
  19:	66 0f 38 41 f1       	phminposuw xmm6,xmm1
  1e:	66 0f 38 41 f9       	phminposuw xmm7,xmm1
  23:	66 44 0f 38 41 c1    	phminposuw xmm8,xmm1
  29:	66 44 0f 38 41 c9    	phminposuw xmm9,xmm1
  2f:	66 44 0f 38 41 d1    	phminposuw xmm10,xmm1
  35:	66 44 0f 38 41 d9    	phminposuw xmm11,xmm1
  3b:	66 44 0f 38 41 e1    	phminposuw xmm12,xmm1

Init:
```
VZEROALL;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 12.01
- Reference cycles: 7.83
- UOPS_EXECUTED.THREAD: 13.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	66 0f 38 41 c1       	phminposuw xmm0,xmm1
   5:	66 0f 38 41 d1       	phminposuw xmm2,xmm1
   a:	66 0f 38 41 d9       	phminposuw xmm3,xmm1
   f:	66 0f 38 41 e1       	phminposuw xmm4,xmm1
  14:	66 0f 38 41 e9       	phminposuw xmm5,xmm1
  19:	66 0f 38 41 f1       	phminposuw xmm6,xmm1
  1e:	66 0f 38 41 f9       	phminposuw xmm7,xmm1
  23:	66 44 0f 38 41 c1    	phminposuw xmm8,xmm1
  29:	66 44 0f 38 41 c9    	phminposuw xmm9,xmm1
  2f:	66 44 0f 38 41 d1    	phminposuw xmm10,xmm1
  35:	66 44 0f 38 41 d9    	phminposuw xmm11,xmm1
  3b:	66 44 0f 38 41 e1    	phminposuw xmm12,xmm1

Init:
```
VZEROALL;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 12.01
- Reference cycles: 7.81
- UOPS_EXECUTED.THREAD: 12.1
- RETIRE_SLOTS: 12.1
- UOPS_MITE: 0.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 12.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.71
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 2.61
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.0
- Reference cycles: 2.6
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0
   5:	66 0f 38 41 c9       	phminposuw xmm1,xmm1
   a:	66 0f 38 41 d2       	phminposuw xmm2,xmm2
   f:	66 0f 38 41 db       	phminposuw xmm3,xmm3

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.5
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0
   5:	66 0f 38 41 c9       	phminposuw xmm1,xmm1
   a:	66 0f 38 41 d2       	phminposuw xmm2,xmm2
   f:	66 0f 38 41 db       	phminposuw xmm3,xmm3

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 2.72
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0
   5:	66 0f 38 41 c9       	phminposuw xmm1,xmm1
   a:	66 0f 38 41 d2       	phminposuw xmm2,xmm2
   f:	66 0f 38 41 db       	phminposuw xmm3,xmm3

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 2.56
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0
   5:	66 0f 38 41 c9       	phminposuw xmm1,xmm1
   a:	66 0f 38 41 d2       	phminposuw xmm2,xmm2
   f:	66 0f 38 41 db       	phminposuw xmm3,xmm3
  14:	66 0f 38 41 e4       	phminposuw xmm4,xmm4
  19:	66 0f 38 41 ed       	phminposuw xmm5,xmm5
  1e:	66 0f 38 41 f6       	phminposuw xmm6,xmm6
  23:	66 0f 38 41 ff       	phminposuw xmm7,xmm7

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 5.0
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0
   5:	66 0f 38 41 c9       	phminposuw xmm1,xmm1
   a:	66 0f 38 41 d2       	phminposuw xmm2,xmm2
   f:	66 0f 38 41 db       	phminposuw xmm3,xmm3
  14:	66 0f 38 41 e4       	phminposuw xmm4,xmm4
  19:	66 0f 38 41 ed       	phminposuw xmm5,xmm5
  1e:	66 0f 38 41 f6       	phminposuw xmm6,xmm6
  23:	66 0f 38 41 ff       	phminposuw xmm7,xmm7

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 5.21
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0
   5:	66 0f 38 41 c9       	phminposuw xmm1,xmm1
   a:	66 0f 38 41 d2       	phminposuw xmm2,xmm2
   f:	66 0f 38 41 db       	phminposuw xmm3,xmm3
  14:	66 0f 38 41 e4       	phminposuw xmm4,xmm4
  19:	66 0f 38 41 ed       	phminposuw xmm5,xmm5
  1e:	66 0f 38 41 f6       	phminposuw xmm6,xmm6
  23:	66 0f 38 41 ff       	phminposuw xmm7,xmm7

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 5.25
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0
   5:	66 0f 38 41 c9       	phminposuw xmm1,xmm1
   a:	66 0f 38 41 d2       	phminposuw xmm2,xmm2
   f:	66 0f 38 41 db       	phminposuw xmm3,xmm3
  14:	66 0f 38 41 e4       	phminposuw xmm4,xmm4
  19:	66 0f 38 41 ed       	phminposuw xmm5,xmm5
  1e:	66 0f 38 41 f6       	phminposuw xmm6,xmm6
  23:	66 0f 38 41 ff       	phminposuw xmm7,xmm7
  28:	66 45 0f 38 41 c0    	phminposuw xmm8,xmm8
  2e:	66 45 0f 38 41 c9    	phminposuw xmm9,xmm9
  34:	66 45 0f 38 41 d2    	phminposuw xmm10,xmm10
  3a:	66 45 0f 38 41 db    	phminposuw xmm11,xmm11
  40:	66 45 0f 38 41 e4    	phminposuw xmm12,xmm12

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 12.98
- Reference cycles: 8.33
- UOPS_EXECUTED.THREAD: 13.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 13.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 13.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.02
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.25

With loop_count=1000 and unroll_count=1

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0
   5:	66 0f 38 41 c9       	phminposuw xmm1,xmm1
   a:	66 0f 38 41 d2       	phminposuw xmm2,xmm2
   f:	66 0f 38 41 db       	phminposuw xmm3,xmm3
  14:	66 0f 38 41 e4       	phminposuw xmm4,xmm4
  19:	66 0f 38 41 ed       	phminposuw xmm5,xmm5
  1e:	66 0f 38 41 f6       	phminposuw xmm6,xmm6
  23:	66 0f 38 41 ff       	phminposuw xmm7,xmm7
  28:	66 45 0f 38 41 c0    	phminposuw xmm8,xmm8
  2e:	66 45 0f 38 41 c9    	phminposuw xmm9,xmm9
  34:	66 45 0f 38 41 d2    	phminposuw xmm10,xmm10
  3a:	66 45 0f 38 41 db    	phminposuw xmm11,xmm11
  40:	66 45 0f 38 41 e4    	phminposuw xmm12,xmm12

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 13.01
- Reference cycles: 8.48
- UOPS_EXECUTED.THREAD: 14.0
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 13.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0
   5:	66 0f 38 41 c9       	phminposuw xmm1,xmm1
   a:	66 0f 38 41 d2       	phminposuw xmm2,xmm2
   f:	66 0f 38 41 db       	phminposuw xmm3,xmm3
  14:	66 0f 38 41 e4       	phminposuw xmm4,xmm4
  19:	66 0f 38 41 ed       	phminposuw xmm5,xmm5
  1e:	66 0f 38 41 f6       	phminposuw xmm6,xmm6
  23:	66 0f 38 41 ff       	phminposuw xmm7,xmm7
  28:	66 45 0f 38 41 c0    	phminposuw xmm8,xmm8
  2e:	66 45 0f 38 41 c9    	phminposuw xmm9,xmm9
  34:	66 45 0f 38 41 d2    	phminposuw xmm10,xmm10
  3a:	66 45 0f 38 41 db    	phminposuw xmm11,xmm11
  40:	66 45 0f 38 41 e4    	phminposuw xmm12,xmm12

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 13.01
- Reference cycles: 8.44
- UOPS_EXECUTED.THREAD: 13.1
- RETIRE_SLOTS: 13.1
- UOPS_MITE: 1.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 13.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.33

PHMINPOSUW (XMM, XMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 12 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10