ADC (RAX, I32) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	48 15 00 00 00 01    	adc    rax,0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 2.01
  • Reference cycles: 1.5
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.54
  • UOPS_PORT_1: 0.46
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.47
  • UOPS_PORT_6: 0.52
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	48 15 00 00 00 01    	adc    rax,0x1000000
     6:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 2.0
  • Reference cycles: 1.5
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.53
  • UOPS_PORT_1: 0.47
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.47
  • UOPS_PORT_6: 0.54
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	48 15 00 00 00 01    	adc    rax,0x1000000
     6:	90                   	nop
     7:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 2.0
  • Reference cycles: 1.25
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.54
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.43
  • UOPS_PORT_6: 0.55
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	48 15 00 00 00 01    	adc    rax,0x1000000
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 2.0
  • Reference cycles: 1.25
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 5.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.53
  • UOPS_PORT_1: 0.46
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.47
  • UOPS_PORT_6: 0.54
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

• Code:

     0:	48 15 00 00 00 01    	adc    rax,0x1000000
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 2.0
  • Reference cycles: 1.5
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 6.0
  • UOPS_MITE: 6.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.71
  • UOPS_PORT_1: 0.29
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.43
  • UOPS_PORT_6: 0.57
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	48 15 00 00 00 01    	adc    rax,0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 2.0
  • Reference cycles: 1.3
  • UOPS_EXECUTED.THREAD: 2.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 2.11
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.55
  • UOPS_PORT_1: 0.45
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.45
  • UOPS_PORT_6: 0.64
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	40                   	rex
     2:	48 15 00 00 00 01    	adc    rax,0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 2.0
  • Reference cycles: 1.36
  • UOPS_EXECUTED.THREAD: 2.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.55
  • UOPS_PORT_1: 0.45
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.45
  • UOPS_PORT_6: 0.64
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	48 15 00 00 00 01    	adc    rax,0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 2.0
  • Reference cycles: 1.36
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 0.11
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.55
  • UOPS_PORT_1: 0.45
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.45
  • UOPS_PORT_6: 0.55
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.05

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	40                   	rex
     2:	48 15 00 00 00 01    	adc    rax,0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 2.0
  • Reference cycles: 1.58
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.55
  • UOPS_PORT_1: 0.45
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.45
  • UOPS_PORT_6: 0.55
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	48 15 00 00 00 01    	adc    rax,0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.92
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.44
  • UOPS_PORT_1: 0.45
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.44
  • UOPS_PORT_6: 0.67
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	48 15 00 00 00 01    	adc    rax,0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.2
  • Core cycles: 0.8
  • Reference cycles: 0.55
  • UOPS_EXECUTED.THREAD: 2.1
  • RETIRE_SLOTS: 3.1
  • UOPS_MITE: 0.9
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.58
  • UOPS_PORT_1: 0.43
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.47
  • UOPS_PORT_6: 0.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.3

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	40                   	rex
     4:	40                   	rex
     5:	40                   	rex
     6:	40                   	rex
     7:	40                   	rex
     8:	40                   	rex
     9:	40                   	rex
     a:	40                   	rex
     b:	48 15 00 00 00 01    	adc    rax,0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.2
  • Core cycles: 0.78
  • Reference cycles: 0.54
  • UOPS_EXECUTED.THREAD: 2.1
  • RETIRE_SLOTS: 3.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.56
  • UOPS_PORT_1: 0.46
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.45
  • UOPS_PORT_6: 0.63
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	48 15 00 00 00 01    	adc    rax,0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.02
  • Core cycles: 0.76
  • Reference cycles: 0.59
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 3.01
  • UOPS_MITE: 0.03
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.52
  • UOPS_PORT_1: 0.47
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.44
  • UOPS_PORT_6: 0.58
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	40                   	rex
     4:	40                   	rex
     5:	40                   	rex
     6:	40                   	rex
     7:	40                   	rex
     8:	40                   	rex
     9:	40                   	rex
     a:	40                   	rex
     b:	48 15 00 00 00 01    	adc    rax,0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.02
  • Core cycles: 0.76
  • Reference cycles: 0.59
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 3.01
  • UOPS_MITE: 0.03
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.52
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.44
  • UOPS_PORT_6: 0.58
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01