VPXOR (YMM, YMM, M256)

With unroll_count=500 and no inner loop

Code:

   0:	c4 c1 75 ef 06       	vpxor  ymm0,ymm1,YMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.53
- Reference cycles: 0.46
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.33
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 c1 75 ef 06       	vpxor  ymm0,ymm1,YMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.5
- Reference cycles: 0.4
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.34
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 c1 75 ef 06       	vpxor  ymm0,ymm1,YMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.5
- Reference cycles: 0.4
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.35
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 c1 75 ef 06       	vpxor  ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 75 ef 56 20    	vpxor  ymm2,ymm1,YMMWORD PTR [r14+0x20]
   b:	c4 c1 75 ef 5e 40    	vpxor  ymm3,ymm1,YMMWORD PTR [r14+0x40]
  11:	c4 c1 75 ef 66 60    	vpxor  ymm4,ymm1,YMMWORD PTR [r14+0x60]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.54
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.33
- UOPS_PORT_1: 1.34
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.34
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 c1 75 ef 06       	vpxor  ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 75 ef 56 20    	vpxor  ymm2,ymm1,YMMWORD PTR [r14+0x20]
   b:	c4 c1 75 ef 5e 40    	vpxor  ymm3,ymm1,YMMWORD PTR [r14+0x40]
  11:	c4 c1 75 ef 66 60    	vpxor  ymm4,ymm1,YMMWORD PTR [r14+0x60]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.01
- Reference cycles: 1.58
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.31
- UOPS_PORT_1: 1.33
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.36
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 c1 75 ef 06       	vpxor  ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 75 ef 56 20    	vpxor  ymm2,ymm1,YMMWORD PTR [r14+0x20]
   b:	c4 c1 75 ef 5e 40    	vpxor  ymm3,ymm1,YMMWORD PTR [r14+0x40]
  11:	c4 c1 75 ef 66 60    	vpxor  ymm4,ymm1,YMMWORD PTR [r14+0x60]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.01
- Reference cycles: 1.57
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.3
- UOPS_PORT_1: 1.31
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.39
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c1 75 ef 06       	vpxor  ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 75 ef 56 20    	vpxor  ymm2,ymm1,YMMWORD PTR [r14+0x20]
   b:	c4 c1 75 ef 5e 40    	vpxor  ymm3,ymm1,YMMWORD PTR [r14+0x40]
  11:	c4 c1 75 ef 66 60    	vpxor  ymm4,ymm1,YMMWORD PTR [r14+0x60]
  17:	c4 c1 75 ef ae 80 00 	vpxor  ymm5,ymm1,YMMWORD PTR [r14+0x80]
  1e:	00 00 
  20:	c4 c1 75 ef b6 a0 00 	vpxor  ymm6,ymm1,YMMWORD PTR [r14+0xa0]
  27:	00 00 
  29:	c4 c1 75 ef be c0 00 	vpxor  ymm7,ymm1,YMMWORD PTR [r14+0xc0]
  30:	00 00 
  32:	c4 41 75 ef 86 e0 00 	vpxor  ymm8,ymm1,YMMWORD PTR [r14+0xe0]
  39:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 2.82
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.54
- UOPS_PORT_1: 2.56
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.9
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c1 75 ef 06       	vpxor  ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 75 ef 56 20    	vpxor  ymm2,ymm1,YMMWORD PTR [r14+0x20]
   b:	c4 c1 75 ef 5e 40    	vpxor  ymm3,ymm1,YMMWORD PTR [r14+0x40]
  11:	c4 c1 75 ef 66 60    	vpxor  ymm4,ymm1,YMMWORD PTR [r14+0x60]
  17:	c4 c1 75 ef ae 80 00 	vpxor  ymm5,ymm1,YMMWORD PTR [r14+0x80]
  1e:	00 00 
  20:	c4 c1 75 ef b6 a0 00 	vpxor  ymm6,ymm1,YMMWORD PTR [r14+0xa0]
  27:	00 00 
  29:	c4 c1 75 ef be c0 00 	vpxor  ymm7,ymm1,YMMWORD PTR [r14+0xc0]
  30:	00 00 
  32:	c4 41 75 ef 86 e0 00 	vpxor  ymm8,ymm1,YMMWORD PTR [r14+0xe0]
  39:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 5.01
- Reference cycles: 4.0
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 9.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.5
- UOPS_PORT_1: 2.63
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.87
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.99

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c1 75 ef 06       	vpxor  ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 75 ef 56 20    	vpxor  ymm2,ymm1,YMMWORD PTR [r14+0x20]
   b:	c4 c1 75 ef 5e 40    	vpxor  ymm3,ymm1,YMMWORD PTR [r14+0x40]
  11:	c4 c1 75 ef 66 60    	vpxor  ymm4,ymm1,YMMWORD PTR [r14+0x60]
  17:	c4 c1 75 ef ae 80 00 	vpxor  ymm5,ymm1,YMMWORD PTR [r14+0x80]
  1e:	00 00 
  20:	c4 c1 75 ef b6 a0 00 	vpxor  ymm6,ymm1,YMMWORD PTR [r14+0xa0]
  27:	00 00 
  29:	c4 c1 75 ef be c0 00 	vpxor  ymm7,ymm1,YMMWORD PTR [r14+0xc0]
  30:	00 00 
  32:	c4 41 75 ef 86 e0 00 	vpxor  ymm8,ymm1,YMMWORD PTR [r14+0xe0]
  39:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.02
- Reference cycles: 3.21
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.6
- UOPS_PORT_1: 2.63
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.77
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 12 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c1 75 ef 06       	vpxor  ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 75 ef 56 20    	vpxor  ymm2,ymm1,YMMWORD PTR [r14+0x20]
   b:	c4 c1 75 ef 5e 40    	vpxor  ymm3,ymm1,YMMWORD PTR [r14+0x40]
  11:	c4 c1 75 ef 66 60    	vpxor  ymm4,ymm1,YMMWORD PTR [r14+0x60]
  17:	c4 c1 75 ef ae 80 00 	vpxor  ymm5,ymm1,YMMWORD PTR [r14+0x80]
  1e:	00 00 
  20:	c4 c1 75 ef b6 a0 00 	vpxor  ymm6,ymm1,YMMWORD PTR [r14+0xa0]
  27:	00 00 
  29:	c4 c1 75 ef be c0 00 	vpxor  ymm7,ymm1,YMMWORD PTR [r14+0xc0]
  30:	00 00 
  32:	c4 41 75 ef 86 e0 00 	vpxor  ymm8,ymm1,YMMWORD PTR [r14+0xe0]
  39:	00 00 
  3b:	c4 41 75 ef 8e 00 01 	vpxor  ymm9,ymm1,YMMWORD PTR [r14+0x100]
  42:	00 00 
  44:	c4 41 75 ef 96 20 01 	vpxor  ymm10,ymm1,YMMWORD PTR [r14+0x120]
  4b:	00 00 
  4d:	c4 41 75 ef 9e 40 01 	vpxor  ymm11,ymm1,YMMWORD PTR [r14+0x140]
  54:	00 00 
  56:	c4 41 75 ef a6 60 01 	vpxor  ymm12,ymm1,YMMWORD PTR [r14+0x160]
  5d:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 6.0
- Reference cycles: 4.62
- UOPS_EXECUTED.THREAD: 24.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.82
- UOPS_PORT_1: 3.81
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.37
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.99

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c1 75 ef 06       	vpxor  ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 75 ef 56 20    	vpxor  ymm2,ymm1,YMMWORD PTR [r14+0x20]
   b:	c4 c1 75 ef 5e 40    	vpxor  ymm3,ymm1,YMMWORD PTR [r14+0x40]
  11:	c4 c1 75 ef 66 60    	vpxor  ymm4,ymm1,YMMWORD PTR [r14+0x60]
  17:	c4 c1 75 ef ae 80 00 	vpxor  ymm5,ymm1,YMMWORD PTR [r14+0x80]
  1e:	00 00 
  20:	c4 c1 75 ef b6 a0 00 	vpxor  ymm6,ymm1,YMMWORD PTR [r14+0xa0]
  27:	00 00 
  29:	c4 c1 75 ef be c0 00 	vpxor  ymm7,ymm1,YMMWORD PTR [r14+0xc0]
  30:	00 00 
  32:	c4 41 75 ef 86 e0 00 	vpxor  ymm8,ymm1,YMMWORD PTR [r14+0xe0]
  39:	00 00 
  3b:	c4 41 75 ef 8e 00 01 	vpxor  ymm9,ymm1,YMMWORD PTR [r14+0x100]
  42:	00 00 
  44:	c4 41 75 ef 96 20 01 	vpxor  ymm10,ymm1,YMMWORD PTR [r14+0x120]
  4b:	00 00 
  4d:	c4 41 75 ef 9e 40 01 	vpxor  ymm11,ymm1,YMMWORD PTR [r14+0x140]
  54:	00 00 
  56:	c4 41 75 ef a6 60 01 	vpxor  ymm12,ymm1,YMMWORD PTR [r14+0x160]
  5d:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 6.02
- Reference cycles: 4.77
- UOPS_EXECUTED.THREAD: 25.0
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 4.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.93
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.07
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c1 75 ef 06       	vpxor  ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 75 ef 56 20    	vpxor  ymm2,ymm1,YMMWORD PTR [r14+0x20]
   b:	c4 c1 75 ef 5e 40    	vpxor  ymm3,ymm1,YMMWORD PTR [r14+0x40]
  11:	c4 c1 75 ef 66 60    	vpxor  ymm4,ymm1,YMMWORD PTR [r14+0x60]
  17:	c4 c1 75 ef ae 80 00 	vpxor  ymm5,ymm1,YMMWORD PTR [r14+0x80]
  1e:	00 00 
  20:	c4 c1 75 ef b6 a0 00 	vpxor  ymm6,ymm1,YMMWORD PTR [r14+0xa0]
  27:	00 00 
  29:	c4 c1 75 ef be c0 00 	vpxor  ymm7,ymm1,YMMWORD PTR [r14+0xc0]
  30:	00 00 
  32:	c4 41 75 ef 86 e0 00 	vpxor  ymm8,ymm1,YMMWORD PTR [r14+0xe0]
  39:	00 00 
  3b:	c4 41 75 ef 8e 00 01 	vpxor  ymm9,ymm1,YMMWORD PTR [r14+0x100]
  42:	00 00 
  44:	c4 41 75 ef 96 20 01 	vpxor  ymm10,ymm1,YMMWORD PTR [r14+0x120]
  4b:	00 00 
  4d:	c4 41 75 ef 9e 40 01 	vpxor  ymm11,ymm1,YMMWORD PTR [r14+0x140]
  54:	00 00 
  56:	c4 41 75 ef a6 60 01 	vpxor  ymm12,ymm1,YMMWORD PTR [r14+0x160]
  5d:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 6.02
- Reference cycles: 4.75
- UOPS_EXECUTED.THREAD: 24.1
- RETIRE_SLOTS: 12.1
- UOPS_MITE: 0.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.9
- UOPS_PORT_1: 3.95
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.15
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 81 75 ef 04 2e    	vpxor  ymm0,ymm1,YMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.5
- Reference cycles: 0.46
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.36
- UOPS_PORT_1: 0.36
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.28
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 81 75 ef 04 2e    	vpxor  ymm0,ymm1,YMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.55
- Reference cycles: 0.43
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 1.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.36
- UOPS_PORT_1: 0.37
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.27
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.3

With loop_count=100 and unroll_count=100

Code:

   0:	c4 81 75 ef 04 2e    	vpxor  ymm0,ymm1,YMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.51
- Reference cycles: 0.4
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.36
- UOPS_PORT_1: 0.36
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.28
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 81 75 ef 04 2e    	vpxor  ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 81 75 ef 54 2e 20 	vpxor  ymm2,ymm1,YMMWORD PTR [r14+r13*1+0x20]
   d:	c4 81 75 ef 5c 2e 40 	vpxor  ymm3,ymm1,YMMWORD PTR [r14+r13*1+0x40]
  14:	c4 81 75 ef 64 2e 60 	vpxor  ymm4,ymm1,YMMWORD PTR [r14+r13*1+0x60]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.41
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.43
- UOPS_PORT_1: 1.43
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.15
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 81 75 ef 04 2e    	vpxor  ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 81 75 ef 54 2e 20 	vpxor  ymm2,ymm1,YMMWORD PTR [r14+r13*1+0x20]
   d:	c4 81 75 ef 5c 2e 40 	vpxor  ymm3,ymm1,YMMWORD PTR [r14+r13*1+0x40]
  14:	c4 81 75 ef 64 2e 60 	vpxor  ymm4,ymm1,YMMWORD PTR [r14+r13*1+0x60]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.26
- Reference cycles: 1.78
- UOPS_EXECUTED.THREAD: 8.51
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.42
- UOPS_PORT_1: 1.5
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.09
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 81 75 ef 04 2e    	vpxor  ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 81 75 ef 54 2e 20 	vpxor  ymm2,ymm1,YMMWORD PTR [r14+r13*1+0x20]
   d:	c4 81 75 ef 5c 2e 40 	vpxor  ymm3,ymm1,YMMWORD PTR [r14+r13*1+0x40]
  14:	c4 81 75 ef 64 2e 60 	vpxor  ymm4,ymm1,YMMWORD PTR [r14+r13*1+0x60]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.04
- Reference cycles: 1.62
- UOPS_EXECUTED.THREAD: 8.06
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.29
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.42
- UOPS_PORT_1: 1.44
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.14
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.11

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 81 75 ef 04 2e    	vpxor  ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 81 75 ef 54 2e 20 	vpxor  ymm2,ymm1,YMMWORD PTR [r14+r13*1+0x20]
   d:	c4 81 75 ef 5c 2e 40 	vpxor  ymm3,ymm1,YMMWORD PTR [r14+r13*1+0x40]
  14:	c4 81 75 ef 64 2e 60 	vpxor  ymm4,ymm1,YMMWORD PTR [r14+r13*1+0x60]
  1b:	c4 81 75 ef ac 2e 80 	vpxor  ymm5,ymm1,YMMWORD PTR [r14+r13*1+0x80]
  22:	00 00 00 
  25:	c4 81 75 ef b4 2e a0 	vpxor  ymm6,ymm1,YMMWORD PTR [r14+r13*1+0xa0]
  2c:	00 00 00 
  2f:	c4 81 75 ef bc 2e c0 	vpxor  ymm7,ymm1,YMMWORD PTR [r14+r13*1+0xc0]
  36:	00 00 00 
  39:	c4 01 75 ef 84 2e e0 	vpxor  ymm8,ymm1,YMMWORD PTR [r14+r13*1+0xe0]
  40:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.19
- Reference cycles: 3.85
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.9
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.43
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.19

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 81 75 ef 04 2e    	vpxor  ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 81 75 ef 54 2e 20 	vpxor  ymm2,ymm1,YMMWORD PTR [r14+r13*1+0x20]
   d:	c4 81 75 ef 5c 2e 40 	vpxor  ymm3,ymm1,YMMWORD PTR [r14+r13*1+0x40]
  14:	c4 81 75 ef 64 2e 60 	vpxor  ymm4,ymm1,YMMWORD PTR [r14+r13*1+0x60]
  1b:	c4 81 75 ef ac 2e 80 	vpxor  ymm5,ymm1,YMMWORD PTR [r14+r13*1+0x80]
  22:	00 00 00 
  25:	c4 81 75 ef b4 2e a0 	vpxor  ymm6,ymm1,YMMWORD PTR [r14+r13*1+0xa0]
  2c:	00 00 00 
  2f:	c4 81 75 ef bc 2e c0 	vpxor  ymm7,ymm1,YMMWORD PTR [r14+r13*1+0xc0]
  36:	00 00 00 
  39:	c4 01 75 ef 84 2e e0 	vpxor  ymm8,ymm1,YMMWORD PTR [r14+r13*1+0xe0]
  40:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.53
- Reference cycles: 3.54
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.83
- UOPS_PORT_1: 2.99
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.18
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 81 75 ef 04 2e    	vpxor  ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 81 75 ef 54 2e 20 	vpxor  ymm2,ymm1,YMMWORD PTR [r14+r13*1+0x20]
   d:	c4 81 75 ef 5c 2e 40 	vpxor  ymm3,ymm1,YMMWORD PTR [r14+r13*1+0x40]
  14:	c4 81 75 ef 64 2e 60 	vpxor  ymm4,ymm1,YMMWORD PTR [r14+r13*1+0x60]
  1b:	c4 81 75 ef ac 2e 80 	vpxor  ymm5,ymm1,YMMWORD PTR [r14+r13*1+0x80]
  22:	00 00 00 
  25:	c4 81 75 ef b4 2e a0 	vpxor  ymm6,ymm1,YMMWORD PTR [r14+r13*1+0xa0]
  2c:	00 00 00 
  2f:	c4 81 75 ef bc 2e c0 	vpxor  ymm7,ymm1,YMMWORD PTR [r14+r13*1+0xc0]
  36:	00 00 00 
  39:	c4 01 75 ef 84 2e e0 	vpxor  ymm8,ymm1,YMMWORD PTR [r14+r13*1+0xe0]
  40:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.08
- Reference cycles: 3.23
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.48
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.84
- UOPS_PORT_1: 2.88
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.29
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.12

With 12 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 81 75 ef 04 2e    	vpxor  ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 81 75 ef 54 2e 20 	vpxor  ymm2,ymm1,YMMWORD PTR [r14+r13*1+0x20]
   d:	c4 81 75 ef 5c 2e 40 	vpxor  ymm3,ymm1,YMMWORD PTR [r14+r13*1+0x40]
  14:	c4 81 75 ef 64 2e 60 	vpxor  ymm4,ymm1,YMMWORD PTR [r14+r13*1+0x60]
  1b:	c4 81 75 ef ac 2e 80 	vpxor  ymm5,ymm1,YMMWORD PTR [r14+r13*1+0x80]
  22:	00 00 00 
  25:	c4 81 75 ef b4 2e a0 	vpxor  ymm6,ymm1,YMMWORD PTR [r14+r13*1+0xa0]
  2c:	00 00 00 
  2f:	c4 81 75 ef bc 2e c0 	vpxor  ymm7,ymm1,YMMWORD PTR [r14+r13*1+0xc0]
  36:	00 00 00 
  39:	c4 01 75 ef 84 2e e0 	vpxor  ymm8,ymm1,YMMWORD PTR [r14+r13*1+0xe0]
  40:	00 00 00 
  43:	c4 01 75 ef 8c 2e 00 	vpxor  ymm9,ymm1,YMMWORD PTR [r14+r13*1+0x100]
  4a:	01 00 00 
  4d:	c4 01 75 ef 94 2e 20 	vpxor  ymm10,ymm1,YMMWORD PTR [r14+r13*1+0x120]
  54:	01 00 00 
  57:	c4 01 75 ef 9c 2e 40 	vpxor  ymm11,ymm1,YMMWORD PTR [r14+r13*1+0x140]
  5e:	01 00 00 
  61:	c4 01 75 ef a4 2e 60 	vpxor  ymm12,ymm1,YMMWORD PTR [r14+r13*1+0x160]
  68:	01 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 6.69
- Reference cycles: 5.13
- UOPS_EXECUTED.THREAD: 24.0
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.34
- UOPS_PORT_1: 4.54
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 3.12
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 6.69

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 81 75 ef 04 2e    	vpxor  ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 81 75 ef 54 2e 20 	vpxor  ymm2,ymm1,YMMWORD PTR [r14+r13*1+0x20]
   d:	c4 81 75 ef 5c 2e 40 	vpxor  ymm3,ymm1,YMMWORD PTR [r14+r13*1+0x40]
  14:	c4 81 75 ef 64 2e 60 	vpxor  ymm4,ymm1,YMMWORD PTR [r14+r13*1+0x60]
  1b:	c4 81 75 ef ac 2e 80 	vpxor  ymm5,ymm1,YMMWORD PTR [r14+r13*1+0x80]
  22:	00 00 00 
  25:	c4 81 75 ef b4 2e a0 	vpxor  ymm6,ymm1,YMMWORD PTR [r14+r13*1+0xa0]
  2c:	00 00 00 
  2f:	c4 81 75 ef bc 2e c0 	vpxor  ymm7,ymm1,YMMWORD PTR [r14+r13*1+0xc0]
  36:	00 00 00 
  39:	c4 01 75 ef 84 2e e0 	vpxor  ymm8,ymm1,YMMWORD PTR [r14+r13*1+0xe0]
  40:	00 00 00 
  43:	c4 01 75 ef 8c 2e 00 	vpxor  ymm9,ymm1,YMMWORD PTR [r14+r13*1+0x100]
  4a:	01 00 00 
  4d:	c4 01 75 ef 94 2e 20 	vpxor  ymm10,ymm1,YMMWORD PTR [r14+r13*1+0x120]
  54:	01 00 00 
  57:	c4 01 75 ef 9c 2e 40 	vpxor  ymm11,ymm1,YMMWORD PTR [r14+r13*1+0x140]
  5e:	01 00 00 
  61:	c4 01 75 ef a4 2e 60 	vpxor  ymm12,ymm1,YMMWORD PTR [r14+r13*1+0x160]
  68:	01 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 6.53
- Reference cycles: 5.13
- UOPS_EXECUTED.THREAD: 25.01
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.24
- UOPS_PORT_1: 4.19
- UOPS_PORT_2: 6.01
- UOPS_PORT_3: 6.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 3.57
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 81 75 ef 04 2e    	vpxor  ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 81 75 ef 54 2e 20 	vpxor  ymm2,ymm1,YMMWORD PTR [r14+r13*1+0x20]
   d:	c4 81 75 ef 5c 2e 40 	vpxor  ymm3,ymm1,YMMWORD PTR [r14+r13*1+0x40]
  14:	c4 81 75 ef 64 2e 60 	vpxor  ymm4,ymm1,YMMWORD PTR [r14+r13*1+0x60]
  1b:	c4 81 75 ef ac 2e 80 	vpxor  ymm5,ymm1,YMMWORD PTR [r14+r13*1+0x80]
  22:	00 00 00 
  25:	c4 81 75 ef b4 2e a0 	vpxor  ymm6,ymm1,YMMWORD PTR [r14+r13*1+0xa0]
  2c:	00 00 00 
  2f:	c4 81 75 ef bc 2e c0 	vpxor  ymm7,ymm1,YMMWORD PTR [r14+r13*1+0xc0]
  36:	00 00 00 
  39:	c4 01 75 ef 84 2e e0 	vpxor  ymm8,ymm1,YMMWORD PTR [r14+r13*1+0xe0]
  40:	00 00 00 
  43:	c4 01 75 ef 8c 2e 00 	vpxor  ymm9,ymm1,YMMWORD PTR [r14+r13*1+0x100]
  4a:	01 00 00 
  4d:	c4 01 75 ef 94 2e 20 	vpxor  ymm10,ymm1,YMMWORD PTR [r14+r13*1+0x120]
  54:	01 00 00 
  57:	c4 01 75 ef 9c 2e 40 	vpxor  ymm11,ymm1,YMMWORD PTR [r14+r13*1+0x140]
  5e:	01 00 00 
  61:	c4 01 75 ef a4 2e 60 	vpxor  ymm12,ymm1,YMMWORD PTR [r14+r13*1+0x160]
  68:	01 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 6.07
- Reference cycles: 4.8
- UOPS_EXECUTED.THREAD: 24.11
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.23
- UOPS_PORT_1: 4.29
- UOPS_PORT_2: 6.01
- UOPS_PORT_3: 6.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 3.48
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

VPXOR (YMM, YMM, M256) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 12 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 12 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10