POPCNT (R32, M32) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 2.26
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.0
- Reference cycles: 2.21
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	90                   	nop
   6:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 3.0
- Reference cycles: 2.31
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 3.0
- Reference cycles: 2.26
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 3.0
- Reference cycles: 2.41
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.0
- Reference cycles: 2.36
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.0
- Reference cycles: 2.36
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	f3 45 0f b8 4e 04    	popcnt r9d,DWORD PTR [r14+0x4]
   b:	f3 45 0f b8 56 08    	popcnt r10d,DWORD PTR [r14+0x8]
  11:	f3 45 0f b8 5e 0c    	popcnt r11d,DWORD PTR [r14+0xc]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.34
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	f3 45 0f b8 4e 04    	popcnt r9d,DWORD PTR [r14+0x4]
   b:	f3 45 0f b8 56 08    	popcnt r10d,DWORD PTR [r14+0x8]
  11:	f3 45 0f b8 5e 0c    	popcnt r11d,DWORD PTR [r14+0xc]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 3.13
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	f3 45 0f b8 4e 04    	popcnt r9d,DWORD PTR [r14+0x4]
   b:	f3 45 0f b8 56 08    	popcnt r10d,DWORD PTR [r14+0x8]
  11:	f3 45 0f b8 5e 0c    	popcnt r11d,DWORD PTR [r14+0xc]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 3.16
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	f3 45 0f b8 4e 04    	popcnt r9d,DWORD PTR [r14+0x4]
   b:	f3 45 0f b8 56 08    	popcnt r10d,DWORD PTR [r14+0x8]
  11:	f3 45 0f b8 5e 0c    	popcnt r11d,DWORD PTR [r14+0xc]
  17:	f3 45 0f b8 66 10    	popcnt r12d,DWORD PTR [r14+0x10]
  1d:	f3 41 0f b8 5e 14    	popcnt ebx,DWORD PTR [r14+0x14]
  23:	f3 41 0f b8 4e 18    	popcnt ecx,DWORD PTR [r14+0x18]
  29:	f3 41 0f b8 56 1c    	popcnt edx,DWORD PTR [r14+0x1c]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 6.42
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.02
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	f3 45 0f b8 4e 04    	popcnt r9d,DWORD PTR [r14+0x4]
   b:	f3 45 0f b8 56 08    	popcnt r10d,DWORD PTR [r14+0x8]
  11:	f3 45 0f b8 5e 0c    	popcnt r11d,DWORD PTR [r14+0xc]
  17:	f3 45 0f b8 66 10    	popcnt r12d,DWORD PTR [r14+0x10]
  1d:	f3 41 0f b8 5e 14    	popcnt ebx,DWORD PTR [r14+0x14]
  23:	f3 41 0f b8 4e 18    	popcnt ecx,DWORD PTR [r14+0x18]
  29:	f3 41 0f b8 56 1c    	popcnt edx,DWORD PTR [r14+0x1c]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 6.31
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	f3 45 0f b8 4e 04    	popcnt r9d,DWORD PTR [r14+0x4]
   b:	f3 45 0f b8 56 08    	popcnt r10d,DWORD PTR [r14+0x8]
  11:	f3 45 0f b8 5e 0c    	popcnt r11d,DWORD PTR [r14+0xc]
  17:	f3 45 0f b8 66 10    	popcnt r12d,DWORD PTR [r14+0x10]
  1d:	f3 41 0f b8 5e 14    	popcnt ebx,DWORD PTR [r14+0x14]
  23:	f3 41 0f b8 4e 18    	popcnt ecx,DWORD PTR [r14+0x18]
  29:	f3 41 0f b8 56 1c    	popcnt edx,DWORD PTR [r14+0x1c]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 6.31
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	f3 47 0f b8 04 2e    	popcnt r8d,DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 2.41
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	f3 47 0f b8 04 2e    	popcnt r8d,DWORD PTR [r14+r13*1]
   6:	90                   	nop

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.0
- Reference cycles: 2.41
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	f3 47 0f b8 04 2e    	popcnt r8d,DWORD PTR [r14+r13*1]
   6:	90                   	nop
   7:	90                   	nop

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 3.0
- Reference cycles: 2.31
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	f3 47 0f b8 04 2e    	popcnt r8d,DWORD PTR [r14+r13*1]
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 3.0
- Reference cycles: 2.21
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	f3 47 0f b8 04 2e    	popcnt r8d,DWORD PTR [r14+r13*1]
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 3.0
- Reference cycles: 2.31
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	f3 47 0f b8 04 2e    	popcnt r8d,DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.0
- Reference cycles: 2.36
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 1.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.01

With loop_count=100 and unroll_count=100

Code:

   0:	f3 47 0f b8 04 2e    	popcnt r8d,DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.0
- Reference cycles: 2.36
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	f3 47 0f b8 04 2e    	popcnt r8d,DWORD PTR [r14+r13*1]
   6:	f3 47 0f b8 4c 2e 04 	popcnt r9d,DWORD PTR [r14+r13*1+0x4]
   d:	f3 47 0f b8 54 2e 08 	popcnt r10d,DWORD PTR [r14+r13*1+0x8]
  14:	f3 47 0f b8 5c 2e 0c 	popcnt r11d,DWORD PTR [r14+r13*1+0xc]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.34
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	f3 47 0f b8 04 2e    	popcnt r8d,DWORD PTR [r14+r13*1]
   6:	f3 47 0f b8 4c 2e 04 	popcnt r9d,DWORD PTR [r14+r13*1+0x4]
   d:	f3 47 0f b8 54 2e 08 	popcnt r10d,DWORD PTR [r14+r13*1+0x8]
  14:	f3 47 0f b8 5c 2e 0c 	popcnt r11d,DWORD PTR [r14+r13*1+0xc]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 3.16
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	f3 47 0f b8 04 2e    	popcnt r8d,DWORD PTR [r14+r13*1]
   6:	f3 47 0f b8 4c 2e 04 	popcnt r9d,DWORD PTR [r14+r13*1+0x4]
   d:	f3 47 0f b8 54 2e 08 	popcnt r10d,DWORD PTR [r14+r13*1+0x8]
  14:	f3 47 0f b8 5c 2e 0c 	popcnt r11d,DWORD PTR [r14+r13*1+0xc]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 3.16
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.29
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.24

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	f3 47 0f b8 04 2e    	popcnt r8d,DWORD PTR [r14+r13*1]
   6:	f3 47 0f b8 4c 2e 04 	popcnt r9d,DWORD PTR [r14+r13*1+0x4]
   d:	f3 47 0f b8 54 2e 08 	popcnt r10d,DWORD PTR [r14+r13*1+0x8]
  14:	f3 47 0f b8 5c 2e 0c 	popcnt r11d,DWORD PTR [r14+r13*1+0xc]
  1b:	f3 47 0f b8 64 2e 10 	popcnt r12d,DWORD PTR [r14+r13*1+0x10]
  22:	f3 43 0f b8 5c 2e 14 	popcnt ebx,DWORD PTR [r14+r13*1+0x14]
  29:	f3 43 0f b8 4c 2e 18 	popcnt ecx,DWORD PTR [r14+r13*1+0x18]
  30:	f3 43 0f b8 54 2e 1c 	popcnt edx,DWORD PTR [r14+r13*1+0x1c]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 6.42
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	f3 47 0f b8 04 2e    	popcnt r8d,DWORD PTR [r14+r13*1]
   6:	f3 47 0f b8 4c 2e 04 	popcnt r9d,DWORD PTR [r14+r13*1+0x4]
   d:	f3 47 0f b8 54 2e 08 	popcnt r10d,DWORD PTR [r14+r13*1+0x8]
  14:	f3 47 0f b8 5c 2e 0c 	popcnt r11d,DWORD PTR [r14+r13*1+0xc]
  1b:	f3 47 0f b8 64 2e 10 	popcnt r12d,DWORD PTR [r14+r13*1+0x10]
  22:	f3 43 0f b8 5c 2e 14 	popcnt ebx,DWORD PTR [r14+r13*1+0x14]
  29:	f3 43 0f b8 4c 2e 18 	popcnt ecx,DWORD PTR [r14+r13*1+0x18]
  30:	f3 43 0f b8 54 2e 1c 	popcnt edx,DWORD PTR [r14+r13*1+0x1c]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 6.31
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 9.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.01

With loop_count=100 and unroll_count=10

Code:

   0:	f3 47 0f b8 04 2e    	popcnt r8d,DWORD PTR [r14+r13*1]
   6:	f3 47 0f b8 4c 2e 04 	popcnt r9d,DWORD PTR [r14+r13*1+0x4]
   d:	f3 47 0f b8 54 2e 08 	popcnt r10d,DWORD PTR [r14+r13*1+0x8]
  14:	f3 47 0f b8 5c 2e 0c 	popcnt r11d,DWORD PTR [r14+r13*1+0xc]
  1b:	f3 47 0f b8 64 2e 10 	popcnt r12d,DWORD PTR [r14+r13*1+0x10]
  22:	f3 43 0f b8 5c 2e 14 	popcnt ebx,DWORD PTR [r14+r13*1+0x14]
  29:	f3 43 0f b8 4c 2e 18 	popcnt ecx,DWORD PTR [r14+r13*1+0x18]
  30:	f3 43 0f b8 54 2e 1c 	popcnt edx,DWORD PTR [r14+r13*1+0x1c]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 6.31
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

Tests for macro-fusion

With JB (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 82 00 00 00 00    	jb     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.08
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JB (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	72 00                	jb     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 2.57
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JBE (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 86 00 00 00 00    	jbe    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 2.82
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JBE (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	76 00                	jbe    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 3.08
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JL (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 8c 00 00 00 00    	jl     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.08
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JL (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	7c 00                	jl     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 2.31
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JLE (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 8e 00 00 00 00    	jle    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 2.31
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JLE (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	7e 00                	jle    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.08
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JNB (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 83 00 00 00 00    	jae    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 1.54
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.65
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.86

With JNB (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	73 00                	jae    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.12
- Reference cycles: 2.82
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.75
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.87

With JNBE (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 87 00 00 00 00    	ja     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.12
- Reference cycles: 3.08
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.7
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.81

With JNBE (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	77 00                	ja     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.12
- Reference cycles: 2.05
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.58
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.81

With JNL (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 8d 00 00 00 00    	jge    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 2.82
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.5
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.86

With JNL (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	7d 00                	jge    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 2.82
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.67
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.82

With JNLE (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 8f 00 00 00 00    	jg     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 2.57
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.69
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.83

With JNLE (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	7f 00                	jg     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 2.31
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.38
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.79

With JNO (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 81 00 00 00 00    	jno    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 2.57
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.6
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.81

With JNO (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	71 00                	jno    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.08
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.74
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.89

With JNP (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 8b 00 00 00 00    	jnp    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 3.08
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.55
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.84

With JNP (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	7b 00                	jnp    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 2.82
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.81
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.83

With JNS (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 89 00 00 00 00    	jns    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 2.82
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.7
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.84

With JNS (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	79 00                	jns    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 2.57
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.65
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.81

With JNZ (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 85 00 00 00 00    	jne    0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.11
- Reference cycles: 3.08
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.61
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.81

With JNZ (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	75 00                	jne    0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.08
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.61
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.01
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.99
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.81

With JO (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 80 00 00 00 00    	jo     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 2.31
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JO (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	70 00                	jo     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.08
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JP (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 8a 00 00 00 00    	jp     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 2.82
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JP (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	7a 00                	jp     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 2.82
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JS (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 88 00 00 00 00    	js     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 3.08
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JS (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	78 00                	js     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 2.82
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JZ (Rel32)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	0f 84 00 00 00 00    	je     0xb

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 2.82
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With JZ (Rel8)

Code:

   0:	f3 45 0f b8 06       	popcnt r8d,DWORD PTR [r14]
   5:	74 00                	je     0x7

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.1
- Reference cycles: 2.05
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.02
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.98
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0