VPSLLVQ (YMM, YMM, YMM) - Throughput and Uops (IACA 2.2)
With different registers for different operands
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles Throughput Bottleneck: Port0
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | CP | vpsllvq ymm0, ymm1, ymm2
Total Num Of Uops: 1
With 11 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 11.00 Cycles Throughput Bottleneck: Port0
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 11.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | CP | vpsllvq ymm0, ymm1, ymm2
| 1 | 1.0 | | | | | | | | CP | vpsllvq ymm3, ymm1, ymm2
| 1 | 1.0 | | | | | | | | CP | vpsllvq ymm4, ymm1, ymm2
| 1 | 1.0 | | | | | | | | CP | vpsllvq ymm5, ymm1, ymm2
| 1 | 1.0 | | | | | | | | CP | vpsllvq ymm6, ymm1, ymm2
| 1 | 1.0 | | | | | | | | CP | vpsllvq ymm7, ymm1, ymm2
| 1 | 1.0 | | | | | | | | CP | vpsllvq ymm8, ymm1, ymm2
| 1 | 1.0 | | | | | | | | CP | vpsllvq ymm9, ymm1, ymm2
| 1 | 1.0 | | | | | | | | CP | vpsllvq ymm10, ymm1, ymm2
| 1 | 1.0 | | | | | | | | CP | vpsllvq ymm11, ymm1, ymm2
| 1 | 1.0 | | | | | | | | CP | vpsllvq ymm12, ymm1, ymm2
Total Num Of Uops: 11
With the same register for for different operands
Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles Throughput Bottleneck: Port0
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | CP | vpsllvq ymm0, ymm0, ymm0
Total Num Of Uops: 1
With the -no_interiteration flag
Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles Throughput Bottleneck: Port0
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | CP | vpsllvq ymm0, ymm1, ymm2
Total Num Of Uops: 1