VPMULUDQ (YMM, YMM, YMM) - Throughput and Uops (IACA 3.0)
With different registers for different operands
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 0.99 Cycles Throughput Bottleneck: Backend
Loop Count: 76
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | vpmuludq ymm0, ymm1, ymm2
Total Num Of Uops: 1
With 11 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 10.95 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 11.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | vpmuludq ymm0, ymm1, ymm2
| 1 | 1.0 | | | | | | | | vpmuludq ymm3, ymm1, ymm2
| 1 | 1.0 | | | | | | | | vpmuludq ymm4, ymm1, ymm2
| 1 | 1.0 | | | | | | | | vpmuludq ymm5, ymm1, ymm2
| 1 | 1.0 | | | | | | | | vpmuludq ymm6, ymm1, ymm2
| 1 | 1.0 | | | | | | | | vpmuludq ymm7, ymm1, ymm2
| 1 | 1.0 | | | | | | | | vpmuludq ymm8, ymm1, ymm2
| 1 | 1.0 | | | | | | | | vpmuludq ymm9, ymm1, ymm2
| 1 | 1.0 | | | | | | | | vpmuludq ymm10, ymm1, ymm2
| 1 | 1.0 | | | | | | | | vpmuludq ymm11, ymm1, ymm2
| 1 | 1.0 | | | | | | | | vpmuludq ymm12, ymm1, ymm2
Total Num Of Uops: 11
With the same register for for different operands
Throughput Analysis Report
--------------------------
Block Throughput: 4.92 Cycles Throughput Bottleneck: Backend
Loop Count: 68
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | vpmuludq ymm0, ymm0, ymm0
Total Num Of Uops: 1