VEXTRACTI128 (M128, YMM, I8)

With unroll_count=500 and no inner loop

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.04
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 1.05
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.71
- UOPS_PORT_3: 0.29
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 1.05
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.43
- UOPS_PORT_3: 0.57
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 2.11
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.75
- UOPS_PORT_3: 0.25
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 1.05
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.55
- UOPS_PORT_3: 0.45
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 1.05
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2
   6:	c4 c3 7d 39 46 10 02 	vextracti128 XMMWORD PTR [r14+0x10],ymm0,0x2
   d:	c4 c3 7d 39 46 20 02 	vextracti128 XMMWORD PTR [r14+0x20],ymm0,0x2
  14:	c4 c3 7d 39 46 30 02 	vextracti128 XMMWORD PTR [r14+0x30],ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 4.2
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2
   6:	c4 c3 7d 39 46 10 02 	vextracti128 XMMWORD PTR [r14+0x10],ymm0,0x2
   d:	c4 c3 7d 39 46 20 02 	vextracti128 XMMWORD PTR [r14+0x20],ymm0,0x2
  14:	c4 c3 7d 39 46 30 02 	vextracti128 XMMWORD PTR [r14+0x30],ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 4.22
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 1.51
- UOPS_PORT_3: 2.49
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2
   6:	c4 c3 7d 39 46 10 02 	vextracti128 XMMWORD PTR [r14+0x10],ymm0,0x2
   d:	c4 c3 7d 39 46 20 02 	vextracti128 XMMWORD PTR [r14+0x20],ymm0,0x2
  14:	c4 c3 7d 39 46 30 02 	vextracti128 XMMWORD PTR [r14+0x30],ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 4.22
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 1.98
- UOPS_PORT_3: 2.02
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2
   6:	c4 c3 7d 39 46 10 02 	vextracti128 XMMWORD PTR [r14+0x10],ymm0,0x2
   d:	c4 c3 7d 39 46 20 02 	vextracti128 XMMWORD PTR [r14+0x20],ymm0,0x2
  14:	c4 c3 7d 39 46 30 02 	vextracti128 XMMWORD PTR [r14+0x30],ymm0,0x2
  1b:	c4 c3 7d 39 46 40 02 	vextracti128 XMMWORD PTR [r14+0x40],ymm0,0x2
  22:	c4 c3 7d 39 46 50 02 	vextracti128 XMMWORD PTR [r14+0x50],ymm0,0x2
  29:	c4 c3 7d 39 46 60 02 	vextracti128 XMMWORD PTR [r14+0x60],ymm0,0x2
  30:	c4 c3 7d 39 46 70 02 	vextracti128 XMMWORD PTR [r14+0x70],ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 8.37
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2
   6:	c4 c3 7d 39 46 10 02 	vextracti128 XMMWORD PTR [r14+0x10],ymm0,0x2
   d:	c4 c3 7d 39 46 20 02 	vextracti128 XMMWORD PTR [r14+0x20],ymm0,0x2
  14:	c4 c3 7d 39 46 30 02 	vextracti128 XMMWORD PTR [r14+0x30],ymm0,0x2
  1b:	c4 c3 7d 39 46 40 02 	vextracti128 XMMWORD PTR [r14+0x40],ymm0,0x2
  22:	c4 c3 7d 39 46 50 02 	vextracti128 XMMWORD PTR [r14+0x50],ymm0,0x2
  29:	c4 c3 7d 39 46 60 02 	vextracti128 XMMWORD PTR [r14+0x60],ymm0,0x2
  30:	c4 c3 7d 39 46 70 02 	vextracti128 XMMWORD PTR [r14+0x70],ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 8.44
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 3.02
- UOPS_PORT_3: 4.98
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2
   6:	c4 c3 7d 39 46 10 02 	vextracti128 XMMWORD PTR [r14+0x10],ymm0,0x2
   d:	c4 c3 7d 39 46 20 02 	vextracti128 XMMWORD PTR [r14+0x20],ymm0,0x2
  14:	c4 c3 7d 39 46 30 02 	vextracti128 XMMWORD PTR [r14+0x30],ymm0,0x2
  1b:	c4 c3 7d 39 46 40 02 	vextracti128 XMMWORD PTR [r14+0x40],ymm0,0x2
  22:	c4 c3 7d 39 46 50 02 	vextracti128 XMMWORD PTR [r14+0x50],ymm0,0x2
  29:	c4 c3 7d 39 46 60 02 	vextracti128 XMMWORD PTR [r14+0x60],ymm0,0x2
  30:	c4 c3 7d 39 46 70 02 	vextracti128 XMMWORD PTR [r14+0x70],ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 8.43
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 3.96
- UOPS_PORT_3: 4.04
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2
   6:	c4 c3 7d 39 46 10 02 	vextracti128 XMMWORD PTR [r14+0x10],ymm0,0x2
   d:	c4 c3 7d 39 46 20 02 	vextracti128 XMMWORD PTR [r14+0x20],ymm0,0x2
  14:	c4 c3 7d 39 46 30 02 	vextracti128 XMMWORD PTR [r14+0x30],ymm0,0x2
  1b:	c4 c3 7d 39 46 40 02 	vextracti128 XMMWORD PTR [r14+0x40],ymm0,0x2
  22:	c4 c3 7d 39 46 50 02 	vextracti128 XMMWORD PTR [r14+0x50],ymm0,0x2
  29:	c4 c3 7d 39 46 60 02 	vextracti128 XMMWORD PTR [r14+0x60],ymm0,0x2
  30:	c4 c3 7d 39 46 70 02 	vextracti128 XMMWORD PTR [r14+0x70],ymm0,0x2
  37:	c4 c3 7d 39 86 80 00 	vextracti128 XMMWORD PTR [r14+0x80],ymm0,0x2
  3e:	00 00 02 
  41:	c4 c3 7d 39 86 90 00 	vextracti128 XMMWORD PTR [r14+0x90],ymm0,0x2
  48:	00 00 02 
  4b:	c4 c3 7d 39 86 a0 00 	vextracti128 XMMWORD PTR [r14+0xa0],ymm0,0x2
  52:	00 00 02 
  55:	c4 c3 7d 39 86 b0 00 	vextracti128 XMMWORD PTR [r14+0xb0],ymm0,0x2
  5c:	00 00 02 
  5f:	c4 c3 7d 39 86 c0 00 	vextracti128 XMMWORD PTR [r14+0xc0],ymm0,0x2
  66:	00 00 02 
  69:	c4 c3 7d 39 86 d0 00 	vextracti128 XMMWORD PTR [r14+0xd0],ymm0,0x2
  70:	00 00 02 
  73:	c4 c3 7d 39 86 e0 00 	vextracti128 XMMWORD PTR [r14+0xe0],ymm0,0x2
  7a:	00 00 02 
  7d:	c4 c3 7d 39 86 f0 00 	vextracti128 XMMWORD PTR [r14+0xf0],ymm0,0x2
  84:	00 00 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 16.8
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2
   6:	c4 c3 7d 39 46 10 02 	vextracti128 XMMWORD PTR [r14+0x10],ymm0,0x2
   d:	c4 c3 7d 39 46 20 02 	vextracti128 XMMWORD PTR [r14+0x20],ymm0,0x2
  14:	c4 c3 7d 39 46 30 02 	vextracti128 XMMWORD PTR [r14+0x30],ymm0,0x2
  1b:	c4 c3 7d 39 46 40 02 	vextracti128 XMMWORD PTR [r14+0x40],ymm0,0x2
  22:	c4 c3 7d 39 46 50 02 	vextracti128 XMMWORD PTR [r14+0x50],ymm0,0x2
  29:	c4 c3 7d 39 46 60 02 	vextracti128 XMMWORD PTR [r14+0x60],ymm0,0x2
  30:	c4 c3 7d 39 46 70 02 	vextracti128 XMMWORD PTR [r14+0x70],ymm0,0x2
  37:	c4 c3 7d 39 86 80 00 	vextracti128 XMMWORD PTR [r14+0x80],ymm0,0x2
  3e:	00 00 02 
  41:	c4 c3 7d 39 86 90 00 	vextracti128 XMMWORD PTR [r14+0x90],ymm0,0x2
  48:	00 00 02 
  4b:	c4 c3 7d 39 86 a0 00 	vextracti128 XMMWORD PTR [r14+0xa0],ymm0,0x2
  52:	00 00 02 
  55:	c4 c3 7d 39 86 b0 00 	vextracti128 XMMWORD PTR [r14+0xb0],ymm0,0x2
  5c:	00 00 02 
  5f:	c4 c3 7d 39 86 c0 00 	vextracti128 XMMWORD PTR [r14+0xc0],ymm0,0x2
  66:	00 00 02 
  69:	c4 c3 7d 39 86 d0 00 	vextracti128 XMMWORD PTR [r14+0xd0],ymm0,0x2
  70:	00 00 02 
  73:	c4 c3 7d 39 86 e0 00 	vextracti128 XMMWORD PTR [r14+0xe0],ymm0,0x2
  7a:	00 00 02 
  7d:	c4 c3 7d 39 86 f0 00 	vextracti128 XMMWORD PTR [r14+0xf0],ymm0,0x2
  84:	00 00 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 16.86
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c3 7d 39 06 02    	vextracti128 XMMWORD PTR [r14],ymm0,0x2
   6:	c4 c3 7d 39 46 10 02 	vextracti128 XMMWORD PTR [r14+0x10],ymm0,0x2
   d:	c4 c3 7d 39 46 20 02 	vextracti128 XMMWORD PTR [r14+0x20],ymm0,0x2
  14:	c4 c3 7d 39 46 30 02 	vextracti128 XMMWORD PTR [r14+0x30],ymm0,0x2
  1b:	c4 c3 7d 39 46 40 02 	vextracti128 XMMWORD PTR [r14+0x40],ymm0,0x2
  22:	c4 c3 7d 39 46 50 02 	vextracti128 XMMWORD PTR [r14+0x50],ymm0,0x2
  29:	c4 c3 7d 39 46 60 02 	vextracti128 XMMWORD PTR [r14+0x60],ymm0,0x2
  30:	c4 c3 7d 39 46 70 02 	vextracti128 XMMWORD PTR [r14+0x70],ymm0,0x2
  37:	c4 c3 7d 39 86 80 00 	vextracti128 XMMWORD PTR [r14+0x80],ymm0,0x2
  3e:	00 00 02 
  41:	c4 c3 7d 39 86 90 00 	vextracti128 XMMWORD PTR [r14+0x90],ymm0,0x2
  48:	00 00 02 
  4b:	c4 c3 7d 39 86 a0 00 	vextracti128 XMMWORD PTR [r14+0xa0],ymm0,0x2
  52:	00 00 02 
  55:	c4 c3 7d 39 86 b0 00 	vextracti128 XMMWORD PTR [r14+0xb0],ymm0,0x2
  5c:	00 00 02 
  5f:	c4 c3 7d 39 86 c0 00 	vextracti128 XMMWORD PTR [r14+0xc0],ymm0,0x2
  66:	00 00 02 
  69:	c4 c3 7d 39 86 d0 00 	vextracti128 XMMWORD PTR [r14+0xd0],ymm0,0x2
  70:	00 00 02 
  73:	c4 c3 7d 39 86 e0 00 	vextracti128 XMMWORD PTR [r14+0xe0],ymm0,0x2
  7a:	00 00 02 
  7d:	c4 c3 7d 39 86 f0 00 	vextracti128 XMMWORD PTR [r14+0xf0],ymm0,0x2
  84:	00 00 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.01
- Reference cycles: 16.86
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 7.97
- UOPS_PORT_3: 8.03
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.05
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 1.04
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.71
- UOPS_PORT_3: 0.29
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 1.04
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.43
- UOPS_PORT_3: 0.57
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 2.11
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.75
- UOPS_PORT_3: 0.25
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 1.05
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.55
- UOPS_PORT_3: 0.45
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 1.05
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2
   7:	c4 83 7d 39 44 2e 10 	vextracti128 XMMWORD PTR [r14+r13*1+0x10],ymm0,0x2
   e:	02 
   f:	c4 83 7d 39 44 2e 20 	vextracti128 XMMWORD PTR [r14+r13*1+0x20],ymm0,0x2
  16:	02 
  17:	c4 83 7d 39 44 2e 30 	vextracti128 XMMWORD PTR [r14+r13*1+0x30],ymm0,0x2
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 4.22
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2
   7:	c4 83 7d 39 44 2e 10 	vextracti128 XMMWORD PTR [r14+r13*1+0x10],ymm0,0x2
   e:	02 
   f:	c4 83 7d 39 44 2e 20 	vextracti128 XMMWORD PTR [r14+r13*1+0x20],ymm0,0x2
  16:	02 
  17:	c4 83 7d 39 44 2e 30 	vextracti128 XMMWORD PTR [r14+r13*1+0x30],ymm0,0x2
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 4.22
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 1.51
- UOPS_PORT_3: 2.49
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2
   7:	c4 83 7d 39 44 2e 10 	vextracti128 XMMWORD PTR [r14+r13*1+0x10],ymm0,0x2
   e:	02 
   f:	c4 83 7d 39 44 2e 20 	vextracti128 XMMWORD PTR [r14+r13*1+0x20],ymm0,0x2
  16:	02 
  17:	c4 83 7d 39 44 2e 30 	vextracti128 XMMWORD PTR [r14+r13*1+0x30],ymm0,0x2
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 4.22
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 1.98
- UOPS_PORT_3: 2.02
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2
   7:	c4 83 7d 39 44 2e 10 	vextracti128 XMMWORD PTR [r14+r13*1+0x10],ymm0,0x2
   e:	02 
   f:	c4 83 7d 39 44 2e 20 	vextracti128 XMMWORD PTR [r14+r13*1+0x20],ymm0,0x2
  16:	02 
  17:	c4 83 7d 39 44 2e 30 	vextracti128 XMMWORD PTR [r14+r13*1+0x30],ymm0,0x2
  1e:	02 
  1f:	c4 83 7d 39 44 2e 40 	vextracti128 XMMWORD PTR [r14+r13*1+0x40],ymm0,0x2
  26:	02 
  27:	c4 83 7d 39 44 2e 50 	vextracti128 XMMWORD PTR [r14+r13*1+0x50],ymm0,0x2
  2e:	02 
  2f:	c4 83 7d 39 44 2e 60 	vextracti128 XMMWORD PTR [r14+r13*1+0x60],ymm0,0x2
  36:	02 
  37:	c4 83 7d 39 44 2e 70 	vextracti128 XMMWORD PTR [r14+r13*1+0x70],ymm0,0x2
  3e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 8.43
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2
   7:	c4 83 7d 39 44 2e 10 	vextracti128 XMMWORD PTR [r14+r13*1+0x10],ymm0,0x2
   e:	02 
   f:	c4 83 7d 39 44 2e 20 	vextracti128 XMMWORD PTR [r14+r13*1+0x20],ymm0,0x2
  16:	02 
  17:	c4 83 7d 39 44 2e 30 	vextracti128 XMMWORD PTR [r14+r13*1+0x30],ymm0,0x2
  1e:	02 
  1f:	c4 83 7d 39 44 2e 40 	vextracti128 XMMWORD PTR [r14+r13*1+0x40],ymm0,0x2
  26:	02 
  27:	c4 83 7d 39 44 2e 50 	vextracti128 XMMWORD PTR [r14+r13*1+0x50],ymm0,0x2
  2e:	02 
  2f:	c4 83 7d 39 44 2e 60 	vextracti128 XMMWORD PTR [r14+r13*1+0x60],ymm0,0x2
  36:	02 
  37:	c4 83 7d 39 44 2e 70 	vextracti128 XMMWORD PTR [r14+r13*1+0x70],ymm0,0x2
  3e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 8.44
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 3.03
- UOPS_PORT_3: 4.98
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2
   7:	c4 83 7d 39 44 2e 10 	vextracti128 XMMWORD PTR [r14+r13*1+0x10],ymm0,0x2
   e:	02 
   f:	c4 83 7d 39 44 2e 20 	vextracti128 XMMWORD PTR [r14+r13*1+0x20],ymm0,0x2
  16:	02 
  17:	c4 83 7d 39 44 2e 30 	vextracti128 XMMWORD PTR [r14+r13*1+0x30],ymm0,0x2
  1e:	02 
  1f:	c4 83 7d 39 44 2e 40 	vextracti128 XMMWORD PTR [r14+r13*1+0x40],ymm0,0x2
  26:	02 
  27:	c4 83 7d 39 44 2e 50 	vextracti128 XMMWORD PTR [r14+r13*1+0x50],ymm0,0x2
  2e:	02 
  2f:	c4 83 7d 39 44 2e 60 	vextracti128 XMMWORD PTR [r14+r13*1+0x60],ymm0,0x2
  36:	02 
  37:	c4 83 7d 39 44 2e 70 	vextracti128 XMMWORD PTR [r14+r13*1+0x70],ymm0,0x2
  3e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 8.44
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 3.96
- UOPS_PORT_3: 4.04
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2
   7:	c4 83 7d 39 44 2e 10 	vextracti128 XMMWORD PTR [r14+r13*1+0x10],ymm0,0x2
   e:	02 
   f:	c4 83 7d 39 44 2e 20 	vextracti128 XMMWORD PTR [r14+r13*1+0x20],ymm0,0x2
  16:	02 
  17:	c4 83 7d 39 44 2e 30 	vextracti128 XMMWORD PTR [r14+r13*1+0x30],ymm0,0x2
  1e:	02 
  1f:	c4 83 7d 39 44 2e 40 	vextracti128 XMMWORD PTR [r14+r13*1+0x40],ymm0,0x2
  26:	02 
  27:	c4 83 7d 39 44 2e 50 	vextracti128 XMMWORD PTR [r14+r13*1+0x50],ymm0,0x2
  2e:	02 
  2f:	c4 83 7d 39 44 2e 60 	vextracti128 XMMWORD PTR [r14+r13*1+0x60],ymm0,0x2
  36:	02 
  37:	c4 83 7d 39 44 2e 70 	vextracti128 XMMWORD PTR [r14+r13*1+0x70],ymm0,0x2
  3e:	02 
  3f:	c4 83 7d 39 84 2e 80 	vextracti128 XMMWORD PTR [r14+r13*1+0x80],ymm0,0x2
  46:	00 00 00 02 
  4a:	c4 83 7d 39 84 2e 90 	vextracti128 XMMWORD PTR [r14+r13*1+0x90],ymm0,0x2
  51:	00 00 00 02 
  55:	c4 83 7d 39 84 2e a0 	vextracti128 XMMWORD PTR [r14+r13*1+0xa0],ymm0,0x2
  5c:	00 00 00 02 
  60:	c4 83 7d 39 84 2e b0 	vextracti128 XMMWORD PTR [r14+r13*1+0xb0],ymm0,0x2
  67:	00 00 00 02 
  6b:	c4 83 7d 39 84 2e c0 	vextracti128 XMMWORD PTR [r14+r13*1+0xc0],ymm0,0x2
  72:	00 00 00 02 
  76:	c4 83 7d 39 84 2e d0 	vextracti128 XMMWORD PTR [r14+r13*1+0xd0],ymm0,0x2
  7d:	00 00 00 02 
  81:	c4 83 7d 39 84 2e e0 	vextracti128 XMMWORD PTR [r14+r13*1+0xe0],ymm0,0x2
  88:	00 00 00 02 
  8c:	c4 83 7d 39 84 2e f0 	vextracti128 XMMWORD PTR [r14+r13*1+0xf0],ymm0,0x2
  93:	00 00 00 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 16.8
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2
   7:	c4 83 7d 39 44 2e 10 	vextracti128 XMMWORD PTR [r14+r13*1+0x10],ymm0,0x2
   e:	02 
   f:	c4 83 7d 39 44 2e 20 	vextracti128 XMMWORD PTR [r14+r13*1+0x20],ymm0,0x2
  16:	02 
  17:	c4 83 7d 39 44 2e 30 	vextracti128 XMMWORD PTR [r14+r13*1+0x30],ymm0,0x2
  1e:	02 
  1f:	c4 83 7d 39 44 2e 40 	vextracti128 XMMWORD PTR [r14+r13*1+0x40],ymm0,0x2
  26:	02 
  27:	c4 83 7d 39 44 2e 50 	vextracti128 XMMWORD PTR [r14+r13*1+0x50],ymm0,0x2
  2e:	02 
  2f:	c4 83 7d 39 44 2e 60 	vextracti128 XMMWORD PTR [r14+r13*1+0x60],ymm0,0x2
  36:	02 
  37:	c4 83 7d 39 44 2e 70 	vextracti128 XMMWORD PTR [r14+r13*1+0x70],ymm0,0x2
  3e:	02 
  3f:	c4 83 7d 39 84 2e 80 	vextracti128 XMMWORD PTR [r14+r13*1+0x80],ymm0,0x2
  46:	00 00 00 02 
  4a:	c4 83 7d 39 84 2e 90 	vextracti128 XMMWORD PTR [r14+r13*1+0x90],ymm0,0x2
  51:	00 00 00 02 
  55:	c4 83 7d 39 84 2e a0 	vextracti128 XMMWORD PTR [r14+r13*1+0xa0],ymm0,0x2
  5c:	00 00 00 02 
  60:	c4 83 7d 39 84 2e b0 	vextracti128 XMMWORD PTR [r14+r13*1+0xb0],ymm0,0x2
  67:	00 00 00 02 
  6b:	c4 83 7d 39 84 2e c0 	vextracti128 XMMWORD PTR [r14+r13*1+0xc0],ymm0,0x2
  72:	00 00 00 02 
  76:	c4 83 7d 39 84 2e d0 	vextracti128 XMMWORD PTR [r14+r13*1+0xd0],ymm0,0x2
  7d:	00 00 00 02 
  81:	c4 83 7d 39 84 2e e0 	vextracti128 XMMWORD PTR [r14+r13*1+0xe0],ymm0,0x2
  88:	00 00 00 02 
  8c:	c4 83 7d 39 84 2e f0 	vextracti128 XMMWORD PTR [r14+r13*1+0xf0],ymm0,0x2
  93:	00 00 00 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 16.86
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	c4 83 7d 39 04 2e 02 	vextracti128 XMMWORD PTR [r14+r13*1],ymm0,0x2
   7:	c4 83 7d 39 44 2e 10 	vextracti128 XMMWORD PTR [r14+r13*1+0x10],ymm0,0x2
   e:	02 
   f:	c4 83 7d 39 44 2e 20 	vextracti128 XMMWORD PTR [r14+r13*1+0x20],ymm0,0x2
  16:	02 
  17:	c4 83 7d 39 44 2e 30 	vextracti128 XMMWORD PTR [r14+r13*1+0x30],ymm0,0x2
  1e:	02 
  1f:	c4 83 7d 39 44 2e 40 	vextracti128 XMMWORD PTR [r14+r13*1+0x40],ymm0,0x2
  26:	02 
  27:	c4 83 7d 39 44 2e 50 	vextracti128 XMMWORD PTR [r14+r13*1+0x50],ymm0,0x2
  2e:	02 
  2f:	c4 83 7d 39 44 2e 60 	vextracti128 XMMWORD PTR [r14+r13*1+0x60],ymm0,0x2
  36:	02 
  37:	c4 83 7d 39 44 2e 70 	vextracti128 XMMWORD PTR [r14+r13*1+0x70],ymm0,0x2
  3e:	02 
  3f:	c4 83 7d 39 84 2e 80 	vextracti128 XMMWORD PTR [r14+r13*1+0x80],ymm0,0x2
  46:	00 00 00 02 
  4a:	c4 83 7d 39 84 2e 90 	vextracti128 XMMWORD PTR [r14+r13*1+0x90],ymm0,0x2
  51:	00 00 00 02 
  55:	c4 83 7d 39 84 2e a0 	vextracti128 XMMWORD PTR [r14+r13*1+0xa0],ymm0,0x2
  5c:	00 00 00 02 
  60:	c4 83 7d 39 84 2e b0 	vextracti128 XMMWORD PTR [r14+r13*1+0xb0],ymm0,0x2
  67:	00 00 00 02 
  6b:	c4 83 7d 39 84 2e c0 	vextracti128 XMMWORD PTR [r14+r13*1+0xc0],ymm0,0x2
  72:	00 00 00 02 
  76:	c4 83 7d 39 84 2e d0 	vextracti128 XMMWORD PTR [r14+r13*1+0xd0],ymm0,0x2
  7d:	00 00 00 02 
  81:	c4 83 7d 39 84 2e e0 	vextracti128 XMMWORD PTR [r14+r13*1+0xe0],ymm0,0x2
  88:	00 00 00 02 
  8c:	c4 83 7d 39 84 2e f0 	vextracti128 XMMWORD PTR [r14+r13*1+0xf0],ymm0,0x2
  93:	00 00 00 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.01
- Reference cycles: 16.85
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 7.97
- UOPS_PORT_3: 8.03
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

VEXTRACTI128 (M128, YMM, I8) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10