VCVTDQ2PD (XMM, M64) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 1.0
  • Reference cycles: 1.06
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
     5:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 1.05
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
     5:	90                   	nop
     6:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 1.0
  • Reference cycles: 1.07
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
     5:	90                   	nop
     6:	90                   	nop
     7:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 2.0
  • Reference cycles: 2.09
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 5.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 1.0
  • Reference cycles: 1.06
  • UOPS_EXECUTED.THREAD: 2.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 1.0
  • Reference cycles: 1.05
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=200 and no inner loop

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
     5:	c4 c1 7a e6 4e 08    	vcvtdq2pd xmm1,QWORD PTR [r14+0x8]
     b:	c4 c1 7a e6 56 10    	vcvtdq2pd xmm2,QWORD PTR [r14+0x10]
    11:	c4 c1 7a e6 5e 18    	vcvtdq2pd xmm3,QWORD PTR [r14+0x18]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 4.0
  • Reference cycles: 4.2
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 2.0
  • UOPS_PORT_3: 2.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
     5:	c4 c1 7a e6 4e 08    	vcvtdq2pd xmm1,QWORD PTR [r14+0x8]
     b:	c4 c1 7a e6 56 10    	vcvtdq2pd xmm2,QWORD PTR [r14+0x10]
    11:	c4 c1 7a e6 5e 18    	vcvtdq2pd xmm3,QWORD PTR [r14+0x18]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 4.01
  • Reference cycles: 4.22
  • UOPS_EXECUTED.THREAD: 8.5
  • RETIRE_SLOTS: 8.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 2.0
  • UOPS_PORT_3: 2.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
     5:	c4 c1 7a e6 4e 08    	vcvtdq2pd xmm1,QWORD PTR [r14+0x8]
     b:	c4 c1 7a e6 56 10    	vcvtdq2pd xmm2,QWORD PTR [r14+0x10]
    11:	c4 c1 7a e6 5e 18    	vcvtdq2pd xmm3,QWORD PTR [r14+0x18]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 4.01
  • Reference cycles: 4.22
  • UOPS_EXECUTED.THREAD: 8.06
  • RETIRE_SLOTS: 8.05
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 2.0
  • UOPS_PORT_3: 2.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.04

With unroll_count=100 and no inner loop

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
     5:	c4 c1 7a e6 4e 08    	vcvtdq2pd xmm1,QWORD PTR [r14+0x8]
     b:	c4 c1 7a e6 56 10    	vcvtdq2pd xmm2,QWORD PTR [r14+0x10]
    11:	c4 c1 7a e6 5e 18    	vcvtdq2pd xmm3,QWORD PTR [r14+0x18]
    17:	c4 c1 7a e6 66 20    	vcvtdq2pd xmm4,QWORD PTR [r14+0x20]
    1d:	c4 c1 7a e6 6e 28    	vcvtdq2pd xmm5,QWORD PTR [r14+0x28]
    23:	c4 c1 7a e6 76 30    	vcvtdq2pd xmm6,QWORD PTR [r14+0x30]
    29:	c4 c1 7a e6 7e 38    	vcvtdq2pd xmm7,QWORD PTR [r14+0x38]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 8.0
  • Reference cycles: 8.4
  • UOPS_EXECUTED.THREAD: 16.0
  • RETIRE_SLOTS: 16.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 8.0
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
     5:	c4 c1 7a e6 4e 08    	vcvtdq2pd xmm1,QWORD PTR [r14+0x8]
     b:	c4 c1 7a e6 56 10    	vcvtdq2pd xmm2,QWORD PTR [r14+0x10]
    11:	c4 c1 7a e6 5e 18    	vcvtdq2pd xmm3,QWORD PTR [r14+0x18]
    17:	c4 c1 7a e6 66 20    	vcvtdq2pd xmm4,QWORD PTR [r14+0x20]
    1d:	c4 c1 7a e6 6e 28    	vcvtdq2pd xmm5,QWORD PTR [r14+0x28]
    23:	c4 c1 7a e6 76 30    	vcvtdq2pd xmm6,QWORD PTR [r14+0x30]
    29:	c4 c1 7a e6 7e 38    	vcvtdq2pd xmm7,QWORD PTR [r14+0x38]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 8.02
  • Reference cycles: 8.44
  • UOPS_EXECUTED.THREAD: 17.0
  • RETIRE_SLOTS: 17.0
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 8.0
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
     5:	c4 c1 7a e6 4e 08    	vcvtdq2pd xmm1,QWORD PTR [r14+0x8]
     b:	c4 c1 7a e6 56 10    	vcvtdq2pd xmm2,QWORD PTR [r14+0x10]
    11:	c4 c1 7a e6 5e 18    	vcvtdq2pd xmm3,QWORD PTR [r14+0x18]
    17:	c4 c1 7a e6 66 20    	vcvtdq2pd xmm4,QWORD PTR [r14+0x20]
    1d:	c4 c1 7a e6 6e 28    	vcvtdq2pd xmm5,QWORD PTR [r14+0x28]
    23:	c4 c1 7a e6 76 30    	vcvtdq2pd xmm6,QWORD PTR [r14+0x30]
    29:	c4 c1 7a e6 7e 38    	vcvtdq2pd xmm7,QWORD PTR [r14+0x38]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 8.02
  • Reference cycles: 8.44
  • UOPS_EXECUTED.THREAD: 16.11
  • RETIRE_SLOTS: 16.1
  • UOPS_MITE: 0.16
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 8.0
  • UOPS_PORT_2: 4.01
  • UOPS_PORT_3: 4.01
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.08

With unroll_count=100 and no inner loop

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
     5:	c4 c1 7a e6 4e 08    	vcvtdq2pd xmm1,QWORD PTR [r14+0x8]
     b:	c4 c1 7a e6 56 10    	vcvtdq2pd xmm2,QWORD PTR [r14+0x10]
    11:	c4 c1 7a e6 5e 18    	vcvtdq2pd xmm3,QWORD PTR [r14+0x18]
    17:	c4 c1 7a e6 66 20    	vcvtdq2pd xmm4,QWORD PTR [r14+0x20]
    1d:	c4 c1 7a e6 6e 28    	vcvtdq2pd xmm5,QWORD PTR [r14+0x28]
    23:	c4 c1 7a e6 76 30    	vcvtdq2pd xmm6,QWORD PTR [r14+0x30]
    29:	c4 c1 7a e6 7e 38    	vcvtdq2pd xmm7,QWORD PTR [r14+0x38]
    2f:	c4 41 7a e6 46 40    	vcvtdq2pd xmm8,QWORD PTR [r14+0x40]
    35:	c4 41 7a e6 4e 48    	vcvtdq2pd xmm9,QWORD PTR [r14+0x48]
    3b:	c4 41 7a e6 56 50    	vcvtdq2pd xmm10,QWORD PTR [r14+0x50]
    41:	c4 41 7a e6 5e 58    	vcvtdq2pd xmm11,QWORD PTR [r14+0x58]
    47:	c4 41 7a e6 66 60    	vcvtdq2pd xmm12,QWORD PTR [r14+0x60]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 13.0
  • Core cycles: 13.0
  • Reference cycles: 13.73
  • UOPS_EXECUTED.THREAD: 26.0
  • RETIRE_SLOTS: 26.0
  • UOPS_MITE: 26.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 13.0
  • UOPS_PORT_2: 6.5
  • UOPS_PORT_3: 6.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 13.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
     5:	c4 c1 7a e6 4e 08    	vcvtdq2pd xmm1,QWORD PTR [r14+0x8]
     b:	c4 c1 7a e6 56 10    	vcvtdq2pd xmm2,QWORD PTR [r14+0x10]
    11:	c4 c1 7a e6 5e 18    	vcvtdq2pd xmm3,QWORD PTR [r14+0x18]
    17:	c4 c1 7a e6 66 20    	vcvtdq2pd xmm4,QWORD PTR [r14+0x20]
    1d:	c4 c1 7a e6 6e 28    	vcvtdq2pd xmm5,QWORD PTR [r14+0x28]
    23:	c4 c1 7a e6 76 30    	vcvtdq2pd xmm6,QWORD PTR [r14+0x30]
    29:	c4 c1 7a e6 7e 38    	vcvtdq2pd xmm7,QWORD PTR [r14+0x38]
    2f:	c4 41 7a e6 46 40    	vcvtdq2pd xmm8,QWORD PTR [r14+0x40]
    35:	c4 41 7a e6 4e 48    	vcvtdq2pd xmm9,QWORD PTR [r14+0x48]
    3b:	c4 41 7a e6 56 50    	vcvtdq2pd xmm10,QWORD PTR [r14+0x50]
    41:	c4 41 7a e6 5e 58    	vcvtdq2pd xmm11,QWORD PTR [r14+0x58]
    47:	c4 41 7a e6 66 60    	vcvtdq2pd xmm12,QWORD PTR [r14+0x60]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 15.0
  • Core cycles: 13.02
  • Reference cycles: 13.7
  • UOPS_EXECUTED.THREAD: 27.01
  • RETIRE_SLOTS: 27.0
  • UOPS_MITE: 0.03
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 13.0
  • UOPS_PORT_2: 6.5
  • UOPS_PORT_3: 6.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]
     5:	c4 c1 7a e6 4e 08    	vcvtdq2pd xmm1,QWORD PTR [r14+0x8]
     b:	c4 c1 7a e6 56 10    	vcvtdq2pd xmm2,QWORD PTR [r14+0x10]
    11:	c4 c1 7a e6 5e 18    	vcvtdq2pd xmm3,QWORD PTR [r14+0x18]
    17:	c4 c1 7a e6 66 20    	vcvtdq2pd xmm4,QWORD PTR [r14+0x20]
    1d:	c4 c1 7a e6 6e 28    	vcvtdq2pd xmm5,QWORD PTR [r14+0x28]
    23:	c4 c1 7a e6 76 30    	vcvtdq2pd xmm6,QWORD PTR [r14+0x30]
    29:	c4 c1 7a e6 7e 38    	vcvtdq2pd xmm7,QWORD PTR [r14+0x38]
    2f:	c4 41 7a e6 46 40    	vcvtdq2pd xmm8,QWORD PTR [r14+0x40]
    35:	c4 41 7a e6 4e 48    	vcvtdq2pd xmm9,QWORD PTR [r14+0x48]
    3b:	c4 41 7a e6 56 50    	vcvtdq2pd xmm10,QWORD PTR [r14+0x50]
    41:	c4 41 7a e6 5e 58    	vcvtdq2pd xmm11,QWORD PTR [r14+0x58]
    47:	c4 41 7a e6 66 60    	vcvtdq2pd xmm12,QWORD PTR [r14+0x60]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 13.2
  • Core cycles: 13.01
  • Reference cycles: 13.7
  • UOPS_EXECUTED.THREAD: 26.11
  • RETIRE_SLOTS: 26.1
  • UOPS_MITE: 0.26
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 13.0
  • UOPS_PORT_2: 6.51
  • UOPS_PORT_3: 6.51
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.13

With unroll_count=500 and no inner loop

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 1.0
  • Reference cycles: 1.07
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
     6:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 1.08
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
     6:	90                   	nop
     7:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 1.0
  • Reference cycles: 1.05
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 2.0
  • Reference cycles: 2.08
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 5.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 1.0
  • Reference cycles: 1.05
  • UOPS_EXECUTED.THREAD: 2.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 1.0
  • Reference cycles: 1.06
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 1.0
  • UOPS_PORT_2: 0.5
  • UOPS_PORT_3: 0.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=200 and no inner loop

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
     6:	c4 81 7a e6 4c 2e 08 	vcvtdq2pd xmm1,QWORD PTR [r14+r13*1+0x8]
     d:	c4 81 7a e6 54 2e 10 	vcvtdq2pd xmm2,QWORD PTR [r14+r13*1+0x10]
    14:	c4 81 7a e6 5c 2e 18 	vcvtdq2pd xmm3,QWORD PTR [r14+r13*1+0x18]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 4.0
  • Reference cycles: 4.2
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 2.0
  • UOPS_PORT_3: 2.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
     6:	c4 81 7a e6 4c 2e 08 	vcvtdq2pd xmm1,QWORD PTR [r14+r13*1+0x8]
     d:	c4 81 7a e6 54 2e 10 	vcvtdq2pd xmm2,QWORD PTR [r14+r13*1+0x10]
    14:	c4 81 7a e6 5c 2e 18 	vcvtdq2pd xmm3,QWORD PTR [r14+r13*1+0x18]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 4.01
  • Reference cycles: 4.22
  • UOPS_EXECUTED.THREAD: 8.5
  • RETIRE_SLOTS: 8.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 2.0
  • UOPS_PORT_3: 2.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
     6:	c4 81 7a e6 4c 2e 08 	vcvtdq2pd xmm1,QWORD PTR [r14+r13*1+0x8]
     d:	c4 81 7a e6 54 2e 10 	vcvtdq2pd xmm2,QWORD PTR [r14+r13*1+0x10]
    14:	c4 81 7a e6 5c 2e 18 	vcvtdq2pd xmm3,QWORD PTR [r14+r13*1+0x18]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 4.01
  • Reference cycles: 4.22
  • UOPS_EXECUTED.THREAD: 8.06
  • RETIRE_SLOTS: 8.05
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 4.0
  • UOPS_PORT_2: 2.0
  • UOPS_PORT_3: 2.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.04

With unroll_count=100 and no inner loop

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
     6:	c4 81 7a e6 4c 2e 08 	vcvtdq2pd xmm1,QWORD PTR [r14+r13*1+0x8]
     d:	c4 81 7a e6 54 2e 10 	vcvtdq2pd xmm2,QWORD PTR [r14+r13*1+0x10]
    14:	c4 81 7a e6 5c 2e 18 	vcvtdq2pd xmm3,QWORD PTR [r14+r13*1+0x18]
    1b:	c4 81 7a e6 64 2e 20 	vcvtdq2pd xmm4,QWORD PTR [r14+r13*1+0x20]
    22:	c4 81 7a e6 6c 2e 28 	vcvtdq2pd xmm5,QWORD PTR [r14+r13*1+0x28]
    29:	c4 81 7a e6 74 2e 30 	vcvtdq2pd xmm6,QWORD PTR [r14+r13*1+0x30]
    30:	c4 81 7a e6 7c 2e 38 	vcvtdq2pd xmm7,QWORD PTR [r14+r13*1+0x38]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 8.0
  • Reference cycles: 8.57
  • UOPS_EXECUTED.THREAD: 16.0
  • RETIRE_SLOTS: 16.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 8.0
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.02
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
     6:	c4 81 7a e6 4c 2e 08 	vcvtdq2pd xmm1,QWORD PTR [r14+r13*1+0x8]
     d:	c4 81 7a e6 54 2e 10 	vcvtdq2pd xmm2,QWORD PTR [r14+r13*1+0x10]
    14:	c4 81 7a e6 5c 2e 18 	vcvtdq2pd xmm3,QWORD PTR [r14+r13*1+0x18]
    1b:	c4 81 7a e6 64 2e 20 	vcvtdq2pd xmm4,QWORD PTR [r14+r13*1+0x20]
    22:	c4 81 7a e6 6c 2e 28 	vcvtdq2pd xmm5,QWORD PTR [r14+r13*1+0x28]
    29:	c4 81 7a e6 74 2e 30 	vcvtdq2pd xmm6,QWORD PTR [r14+r13*1+0x30]
    30:	c4 81 7a e6 7c 2e 38 	vcvtdq2pd xmm7,QWORD PTR [r14+r13*1+0x38]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 8.01
  • Reference cycles: 8.44
  • UOPS_EXECUTED.THREAD: 17.0
  • RETIRE_SLOTS: 17.0
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 8.0
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
     6:	c4 81 7a e6 4c 2e 08 	vcvtdq2pd xmm1,QWORD PTR [r14+r13*1+0x8]
     d:	c4 81 7a e6 54 2e 10 	vcvtdq2pd xmm2,QWORD PTR [r14+r13*1+0x10]
    14:	c4 81 7a e6 5c 2e 18 	vcvtdq2pd xmm3,QWORD PTR [r14+r13*1+0x18]
    1b:	c4 81 7a e6 64 2e 20 	vcvtdq2pd xmm4,QWORD PTR [r14+r13*1+0x20]
    22:	c4 81 7a e6 6c 2e 28 	vcvtdq2pd xmm5,QWORD PTR [r14+r13*1+0x28]
    29:	c4 81 7a e6 74 2e 30 	vcvtdq2pd xmm6,QWORD PTR [r14+r13*1+0x30]
    30:	c4 81 7a e6 7c 2e 38 	vcvtdq2pd xmm7,QWORD PTR [r14+r13*1+0x38]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 8.01
  • Reference cycles: 8.44
  • UOPS_EXECUTED.THREAD: 16.11
  • RETIRE_SLOTS: 16.1
  • UOPS_MITE: 0.16
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 8.0
  • UOPS_PORT_2: 4.01
  • UOPS_PORT_3: 4.01
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.08

With unroll_count=100 and no inner loop

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
     6:	c4 81 7a e6 4c 2e 08 	vcvtdq2pd xmm1,QWORD PTR [r14+r13*1+0x8]
     d:	c4 81 7a e6 54 2e 10 	vcvtdq2pd xmm2,QWORD PTR [r14+r13*1+0x10]
    14:	c4 81 7a e6 5c 2e 18 	vcvtdq2pd xmm3,QWORD PTR [r14+r13*1+0x18]
    1b:	c4 81 7a e6 64 2e 20 	vcvtdq2pd xmm4,QWORD PTR [r14+r13*1+0x20]
    22:	c4 81 7a e6 6c 2e 28 	vcvtdq2pd xmm5,QWORD PTR [r14+r13*1+0x28]
    29:	c4 81 7a e6 74 2e 30 	vcvtdq2pd xmm6,QWORD PTR [r14+r13*1+0x30]
    30:	c4 81 7a e6 7c 2e 38 	vcvtdq2pd xmm7,QWORD PTR [r14+r13*1+0x38]
    37:	c4 01 7a e6 44 2e 40 	vcvtdq2pd xmm8,QWORD PTR [r14+r13*1+0x40]
    3e:	c4 01 7a e6 4c 2e 48 	vcvtdq2pd xmm9,QWORD PTR [r14+r13*1+0x48]
    45:	c4 01 7a e6 54 2e 50 	vcvtdq2pd xmm10,QWORD PTR [r14+r13*1+0x50]
    4c:	c4 01 7a e6 5c 2e 58 	vcvtdq2pd xmm11,QWORD PTR [r14+r13*1+0x58]
    53:	c4 01 7a e6 64 2e 60 	vcvtdq2pd xmm12,QWORD PTR [r14+r13*1+0x60]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 13.0
  • Core cycles: 13.0
  • Reference cycles: 13.6
  • UOPS_EXECUTED.THREAD: 26.0
  • RETIRE_SLOTS: 26.0
  • UOPS_MITE: 26.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 13.0
  • UOPS_PORT_2: 6.5
  • UOPS_PORT_3: 6.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 13.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
     6:	c4 81 7a e6 4c 2e 08 	vcvtdq2pd xmm1,QWORD PTR [r14+r13*1+0x8]
     d:	c4 81 7a e6 54 2e 10 	vcvtdq2pd xmm2,QWORD PTR [r14+r13*1+0x10]
    14:	c4 81 7a e6 5c 2e 18 	vcvtdq2pd xmm3,QWORD PTR [r14+r13*1+0x18]
    1b:	c4 81 7a e6 64 2e 20 	vcvtdq2pd xmm4,QWORD PTR [r14+r13*1+0x20]
    22:	c4 81 7a e6 6c 2e 28 	vcvtdq2pd xmm5,QWORD PTR [r14+r13*1+0x28]
    29:	c4 81 7a e6 74 2e 30 	vcvtdq2pd xmm6,QWORD PTR [r14+r13*1+0x30]
    30:	c4 81 7a e6 7c 2e 38 	vcvtdq2pd xmm7,QWORD PTR [r14+r13*1+0x38]
    37:	c4 01 7a e6 44 2e 40 	vcvtdq2pd xmm8,QWORD PTR [r14+r13*1+0x40]
    3e:	c4 01 7a e6 4c 2e 48 	vcvtdq2pd xmm9,QWORD PTR [r14+r13*1+0x48]
    45:	c4 01 7a e6 54 2e 50 	vcvtdq2pd xmm10,QWORD PTR [r14+r13*1+0x50]
    4c:	c4 01 7a e6 5c 2e 58 	vcvtdq2pd xmm11,QWORD PTR [r14+r13*1+0x58]
    53:	c4 01 7a e6 64 2e 60 	vcvtdq2pd xmm12,QWORD PTR [r14+r13*1+0x60]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 15.0
  • Core cycles: 13.01
  • Reference cycles: 13.7
  • UOPS_EXECUTED.THREAD: 27.01
  • RETIRE_SLOTS: 27.0
  • UOPS_MITE: 0.03
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 13.0
  • UOPS_PORT_2: 6.5
  • UOPS_PORT_3: 6.5
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]
     6:	c4 81 7a e6 4c 2e 08 	vcvtdq2pd xmm1,QWORD PTR [r14+r13*1+0x8]
     d:	c4 81 7a e6 54 2e 10 	vcvtdq2pd xmm2,QWORD PTR [r14+r13*1+0x10]
    14:	c4 81 7a e6 5c 2e 18 	vcvtdq2pd xmm3,QWORD PTR [r14+r13*1+0x18]
    1b:	c4 81 7a e6 64 2e 20 	vcvtdq2pd xmm4,QWORD PTR [r14+r13*1+0x20]
    22:	c4 81 7a e6 6c 2e 28 	vcvtdq2pd xmm5,QWORD PTR [r14+r13*1+0x28]
    29:	c4 81 7a e6 74 2e 30 	vcvtdq2pd xmm6,QWORD PTR [r14+r13*1+0x30]
    30:	c4 81 7a e6 7c 2e 38 	vcvtdq2pd xmm7,QWORD PTR [r14+r13*1+0x38]
    37:	c4 01 7a e6 44 2e 40 	vcvtdq2pd xmm8,QWORD PTR [r14+r13*1+0x40]
    3e:	c4 01 7a e6 4c 2e 48 	vcvtdq2pd xmm9,QWORD PTR [r14+r13*1+0x48]
    45:	c4 01 7a e6 54 2e 50 	vcvtdq2pd xmm10,QWORD PTR [r14+r13*1+0x50]
    4c:	c4 01 7a e6 5c 2e 58 	vcvtdq2pd xmm11,QWORD PTR [r14+r13*1+0x58]
    53:	c4 01 7a e6 64 2e 60 	vcvtdq2pd xmm12,QWORD PTR [r14+r13*1+0x60]
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 13.2
  • Core cycles: 13.01
  • Reference cycles: 13.7
  • UOPS_EXECUTED.THREAD: 26.11
  • RETIRE_SLOTS: 26.1
  • UOPS_MITE: 0.26
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.0
  • UOPS_PORT_1: 13.0
  • UOPS_PORT_2: 6.51
  • UOPS_PORT_3: 6.51
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.13