RDMSR - Throughput and Uops
With unroll_count=500 and no inner loop
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.0
- Core cycles: 91.14
- Reference cycles: 95.93
- UOPS_EXECUTED.THREAD: 72.71
- RETIRE_SLOTS: 68.0
- UOPS_MITE: 0.0
- UOPS_MS: 74.0
- UOPS_PORT_0: 14.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 15.0
- UOPS_PORT_6: 31.71
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0
With unroll_count=500, no inner loop, and 1 NOP
- Code:
0: 0f 32 rdmsr
2: 90 nop
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 2.0
- Core cycles: 92.71
- Reference cycles: 97.58
- UOPS_EXECUTED.THREAD: 72.29
- RETIRE_SLOTS: 69.0
- UOPS_MITE: 1.0
- UOPS_MS: 74.0
- UOPS_PORT_0: 14.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 15.0
- UOPS_PORT_6: 31.28
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0
With loop_count=1000 and unroll_count=10
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.2
- Core cycles: 91.43
- Reference cycles: 96.24
- UOPS_EXECUTED.THREAD: 72.77
- RETIRE_SLOTS: 68.1
- UOPS_MITE: 0.1
- UOPS_MS: 74.0
- UOPS_PORT_0: 14.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 15.0
- UOPS_PORT_6: 31.77
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.1
With loop_count=100 and unroll_count=100
- Code:
0: 0f 32 rdmsr
- Init:
MOV RCX, 0xE7
- Show nanoBench command
- Results:
- Instructions retired: 1.02
- Core cycles: 91.3
- Reference cycles: 96.11
- UOPS_EXECUTED.THREAD: 72.72
- RETIRE_SLOTS: 68.01
- UOPS_MITE: 0.01
- UOPS_MS: 74.0
- UOPS_PORT_0: 14.0
- UOPS_PORT_1: 12.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 15.0
- UOPS_PORT_6: 31.72
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01