IMUL (M8) - Throughput and Uops (IACA 2.2)
With a non-indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 3.00 Cycles Throughput Bottleneck: Dependency chains (possibly between iterations)
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | | | CP | imul byte ptr [r14]
Total Num Of Uops: 2
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles Throughput Bottleneck: Port1
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | | | CP | imul byte ptr [r14]
| 1* | | | | | | | | | | xor rax, rax
Total Num Of Uops: 3
With 16 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 48.00 Cycles Throughput Bottleneck: Dependency chains (possibly between iterations)
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 16.0 | 8.0 8.0 | 8.0 8.0 | 0.0 | 0.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14]
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0x1]
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+0x2]
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0x3]
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+0x4]
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0x5]
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+0x6]
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0x7]
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+0x8]
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0x9]
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+0xa]
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0xb]
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+0xc]
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0xd]
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+0xe]
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0xf]
Total Num Of Uops: 32
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 16.00 Cycles Throughput Bottleneck: Port1
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 16.0 | 8.0 8.0 | 8.0 8.0 | 0.0 | 0.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0x1]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+0x2]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0x3]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+0x4]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0x5]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+0x6]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0x7]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+0x8]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0x9]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+0xa]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0xb]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+0xc]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0xd]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+0xe]
| 1* | | | | | | | | | | xor rax, rax
| 2^ | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+0xf]
| 1* | | | | | | | | | | xor rax, rax
Total Num Of Uops: 48
With an indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 3.00 Cycles Throughput Bottleneck: Dependency chains (possibly between iterations)
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | | | CP | imul byte ptr [r14+r13*1]
Total Num Of Uops: 2
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles Throughput Bottleneck: Port1
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | | | CP | imul byte ptr [r14+r13*1]
| 1* | | | | | | | | | | xor rax, rax
Total Num Of Uops: 3
With 16 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 48.00 Cycles Throughput Bottleneck: Dependency chains (possibly between iterations)
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 16.0 | 8.0 8.0 | 8.0 8.0 | 0.0 | 0.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1]
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0x1]
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1+0x2]
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0x3]
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1+0x4]
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0x5]
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1+0x6]
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0x7]
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1+0x8]
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0x9]
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1+0xa]
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0xb]
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1+0xc]
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0xd]
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1+0xe]
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0xf]
Total Num Of Uops: 32
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 16.00 Cycles Throughput Bottleneck: Port1
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 16.0 | 8.0 8.0 | 8.0 8.0 | 0.0 | 0.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0x1]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1+0x2]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0x3]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1+0x4]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0x5]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1+0x6]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0x7]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1+0x8]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0x9]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1+0xa]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0xb]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1+0xc]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0xd]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | 1.0 1.0 | | | | | | CP | imul byte ptr [r14+r13*1+0xe]
| 1* | | | | | | | | | | xor rax, rax
| 2 | | 1.0 | | 1.0 1.0 | | | | | CP | imul byte ptr [r14+r13*1+0xf]
| 1* | | | | | | | | | | xor rax, rax
Total Num Of Uops: 48
With the -no_interiteration flag
Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles Throughput Bottleneck: Port1
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | | | CP | imul byte ptr [r14]
Total Num Of Uops: 2