ADD (M64, R64)

With unroll_count=500 and no inner loop

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 6.0
- Reference cycles: 6.35
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.77
- UOPS_PORT_1: 1.75
- UOPS_PORT_2: 0.56
- UOPS_PORT_3: 0.94
- UOPS_PORT_4: 5.23
- UOPS_PORT_5: 1.94
- UOPS_PORT_6: 1.38
- UOPS_PORT_7: 0.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8
   3:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.42
- Reference cycles: 6.76
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.73
- UOPS_PORT_1: 1.75
- UOPS_PORT_2: 0.71
- UOPS_PORT_3: 0.78
- UOPS_PORT_4: 4.26
- UOPS_PORT_5: 1.79
- UOPS_PORT_6: 1.8
- UOPS_PORT_7: 0.51
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8
   3:	90                   	nop
   4:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 7.42
- Reference cycles: 7.81
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.96
- UOPS_PORT_1: 1.97
- UOPS_PORT_2: 0.71
- UOPS_PORT_3: 0.74
- UOPS_PORT_4: 1.63
- UOPS_PORT_5: 2.25
- UOPS_PORT_6: 1.3
- UOPS_PORT_7: 0.55
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8
   3:	90                   	nop
   4:	90                   	nop
   5:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.01
- Reference cycles: 6.33
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.67
- UOPS_PORT_1: 1.75
- UOPS_PORT_2: 0.72
- UOPS_PORT_3: 0.75
- UOPS_PORT_4: 5.91
- UOPS_PORT_5: 1.73
- UOPS_PORT_6: 1.76
- UOPS_PORT_7: 0.54
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.0
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 2.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.69
- UOPS_PORT_1: 1.7
- UOPS_PORT_2: 0.76
- UOPS_PORT_3: 0.89
- UOPS_PORT_4: 5.37
- UOPS_PORT_5: 1.71
- UOPS_PORT_6: 1.82
- UOPS_PORT_7: 0.35
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	4d 01 06             	add    QWORD PTR [r14],r8

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.0
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.66
- UOPS_PORT_1: 1.68
- UOPS_PORT_2: 0.76
- UOPS_PORT_3: 0.89
- UOPS_PORT_4: 5.52
- UOPS_PORT_5: 1.78
- UOPS_PORT_6: 1.86
- UOPS_PORT_7: 0.35
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.0
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 2.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.69
- UOPS_PORT_1: 1.71
- UOPS_PORT_2: 0.78
- UOPS_PORT_3: 0.94
- UOPS_PORT_4: 5.34
- UOPS_PORT_5: 1.71
- UOPS_PORT_6: 1.68
- UOPS_PORT_7: 0.28
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	4d 01 06             	add    QWORD PTR [r14],r8

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.0
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.71
- UOPS_PORT_1: 1.73
- UOPS_PORT_2: 0.78
- UOPS_PORT_3: 0.94
- UOPS_PORT_4: 5.43
- UOPS_PORT_5: 1.77
- UOPS_PORT_6: 1.69
- UOPS_PORT_7: 0.28
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8
   3:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
   7:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
   b:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.39
- Reference cycles: 6.73
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.62
- UOPS_PORT_1: 2.82
- UOPS_PORT_2: 2.87
- UOPS_PORT_3: 2.94
- UOPS_PORT_4: 5.8
- UOPS_PORT_5: 2.74
- UOPS_PORT_6: 2.49
- UOPS_PORT_7: 2.2
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8
   3:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
   7:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
   b:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 6.01
- Reference cycles: 6.33
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.54
- UOPS_PORT_1: 2.58
- UOPS_PORT_2: 2.94
- UOPS_PORT_3: 3.15
- UOPS_PORT_4: 5.93
- UOPS_PORT_5: 2.59
- UOPS_PORT_6: 2.95
- UOPS_PORT_7: 1.91
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	4d 01 06             	add    QWORD PTR [r14],r8
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 6.01
- Reference cycles: 6.33
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.52
- UOPS_PORT_1: 2.56
- UOPS_PORT_2: 2.93
- UOPS_PORT_3: 3.16
- UOPS_PORT_4: 5.74
- UOPS_PORT_5: 2.56
- UOPS_PORT_6: 2.9
- UOPS_PORT_7: 1.91
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8
   3:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
   7:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
   b:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 6.16
- Reference cycles: 6.49
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.09
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.5
- UOPS_PORT_1: 2.55
- UOPS_PORT_2: 2.96
- UOPS_PORT_3: 2.92
- UOPS_PORT_4: 5.86
- UOPS_PORT_5: 2.65
- UOPS_PORT_6: 2.64
- UOPS_PORT_7: 2.12
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	4d 01 06             	add    QWORD PTR [r14],r8
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 6.17
- Reference cycles: 6.51
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.5
- UOPS_PORT_1: 2.55
- UOPS_PORT_2: 2.96
- UOPS_PORT_3: 2.92
- UOPS_PORT_4: 5.86
- UOPS_PORT_5: 2.65
- UOPS_PORT_6: 2.64
- UOPS_PORT_7: 2.12
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8
   3:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
   7:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
   b:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8
   f:	4d 01 46 20          	add    QWORD PTR [r14+0x20],r8
  13:	4d 01 46 28          	add    QWORD PTR [r14+0x28],r8
  17:	4d 01 46 30          	add    QWORD PTR [r14+0x30],r8
  1b:	4d 01 46 38          	add    QWORD PTR [r14+0x38],r8

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.33
- Reference cycles: 8.8
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.9
- UOPS_PORT_1: 4.14
- UOPS_PORT_2: 5.54
- UOPS_PORT_3: 5.6
- UOPS_PORT_4: 8.03
- UOPS_PORT_5: 4.17
- UOPS_PORT_6: 3.11
- UOPS_PORT_7: 4.86
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8
   3:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
   7:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
   b:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8
   f:	4d 01 46 20          	add    QWORD PTR [r14+0x20],r8
  13:	4d 01 46 28          	add    QWORD PTR [r14+0x28],r8
  17:	4d 01 46 30          	add    QWORD PTR [r14+0x30],r8
  1b:	4d 01 46 38          	add    QWORD PTR [r14+0x38],r8

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.2
- Reference cycles: 8.65
- UOPS_EXECUTED.THREAD: 33.02
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.77
- UOPS_PORT_1: 3.86
- UOPS_PORT_2: 5.51
- UOPS_PORT_3: 5.78
- UOPS_PORT_4: 8.01
- UOPS_PORT_5: 4.04
- UOPS_PORT_6: 4.67
- UOPS_PORT_7: 4.74
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	4d 01 06             	add    QWORD PTR [r14],r8
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	40                   	rex
  28:	4d 01 46 20          	add    QWORD PTR [r14+0x20],r8
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	4d 01 46 28          	add    QWORD PTR [r14+0x28],r8
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	40                   	rex
  3a:	4d 01 46 30          	add    QWORD PTR [r14+0x30],r8
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	4d 01 46 38          	add    QWORD PTR [r14+0x38],r8

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.23
- Reference cycles: 8.66
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.78
- UOPS_PORT_1: 3.9
- UOPS_PORT_2: 5.46
- UOPS_PORT_3: 5.81
- UOPS_PORT_4: 8.01
- UOPS_PORT_5: 4.05
- UOPS_PORT_6: 4.72
- UOPS_PORT_7: 4.75
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8
   3:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
   7:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
   b:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8
   f:	4d 01 46 20          	add    QWORD PTR [r14+0x20],r8
  13:	4d 01 46 28          	add    QWORD PTR [r14+0x28],r8
  17:	4d 01 46 30          	add    QWORD PTR [r14+0x30],r8
  1b:	4d 01 46 38          	add    QWORD PTR [r14+0x38],r8

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.18
- Reference cycles: 8.61
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.79
- UOPS_PORT_1: 3.85
- UOPS_PORT_2: 5.69
- UOPS_PORT_3: 5.89
- UOPS_PORT_4: 8.01
- UOPS_PORT_5: 3.87
- UOPS_PORT_6: 4.0
- UOPS_PORT_7: 4.44
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	4d 01 06             	add    QWORD PTR [r14],r8
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	40                   	rex
  28:	4d 01 46 20          	add    QWORD PTR [r14+0x20],r8
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	4d 01 46 28          	add    QWORD PTR [r14+0x28],r8
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	40                   	rex
  3a:	4d 01 46 30          	add    QWORD PTR [r14+0x30],r8
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	4d 01 46 38          	add    QWORD PTR [r14+0x38],r8

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.18
- Reference cycles: 8.61
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.79
- UOPS_PORT_1: 3.85
- UOPS_PORT_2: 5.69
- UOPS_PORT_3: 5.89
- UOPS_PORT_4: 8.01
- UOPS_PORT_5: 3.87
- UOPS_PORT_6: 4.0
- UOPS_PORT_7: 4.44
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8
   3:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
   7:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
   b:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8
   f:	4d 01 46 20          	add    QWORD PTR [r14+0x20],r8
  13:	4d 01 46 28          	add    QWORD PTR [r14+0x28],r8
  17:	4d 01 46 30          	add    QWORD PTR [r14+0x30],r8
  1b:	4d 01 46 38          	add    QWORD PTR [r14+0x38],r8
  1f:	4d 01 46 40          	add    QWORD PTR [r14+0x40],r8
  23:	4d 01 46 48          	add    QWORD PTR [r14+0x48],r8
  27:	4d 01 46 50          	add    QWORD PTR [r14+0x50],r8
  2b:	4d 01 46 58          	add    QWORD PTR [r14+0x58],r8
  2f:	4d 01 46 60          	add    QWORD PTR [r14+0x60],r8
  33:	4d 01 46 68          	add    QWORD PTR [r14+0x68],r8
  37:	4d 01 46 70          	add    QWORD PTR [r14+0x70],r8
  3b:	4d 01 46 78          	add    QWORD PTR [r14+0x78],r8

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.19
- Reference cycles: 17.0
- UOPS_EXECUTED.THREAD: 64.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 7.25
- UOPS_PORT_1: 7.77
- UOPS_PORT_2: 11.13
- UOPS_PORT_3: 11.64
- UOPS_PORT_4: 16.01
- UOPS_PORT_5: 7.68
- UOPS_PORT_6: 6.72
- UOPS_PORT_7: 9.23
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8
   3:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
   7:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
   b:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8
   f:	4d 01 46 20          	add    QWORD PTR [r14+0x20],r8
  13:	4d 01 46 28          	add    QWORD PTR [r14+0x28],r8
  17:	4d 01 46 30          	add    QWORD PTR [r14+0x30],r8
  1b:	4d 01 46 38          	add    QWORD PTR [r14+0x38],r8
  1f:	4d 01 46 40          	add    QWORD PTR [r14+0x40],r8
  23:	4d 01 46 48          	add    QWORD PTR [r14+0x48],r8
  27:	4d 01 46 50          	add    QWORD PTR [r14+0x50],r8
  2b:	4d 01 46 58          	add    QWORD PTR [r14+0x58],r8
  2f:	4d 01 46 60          	add    QWORD PTR [r14+0x60],r8
  33:	4d 01 46 68          	add    QWORD PTR [r14+0x68],r8
  37:	4d 01 46 70          	add    QWORD PTR [r14+0x70],r8
  3b:	4d 01 46 78          	add    QWORD PTR [r14+0x78],r8

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.14
- Reference cycles: 17.0
- UOPS_EXECUTED.THREAD: 65.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.79
- UOPS_PORT_1: 7.47
- UOPS_PORT_2: 11.63
- UOPS_PORT_3: 11.64
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 7.77
- UOPS_PORT_6: 8.24
- UOPS_PORT_7: 8.74
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	4d 01 06             	add    QWORD PTR [r14],r8
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	40                   	rex
  28:	4d 01 46 20          	add    QWORD PTR [r14+0x20],r8
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	4d 01 46 28          	add    QWORD PTR [r14+0x28],r8
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	40                   	rex
  3a:	4d 01 46 30          	add    QWORD PTR [r14+0x30],r8
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	4d 01 46 38          	add    QWORD PTR [r14+0x38],r8
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	4d 01 46 40          	add    QWORD PTR [r14+0x40],r8
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	40                   	rex
  55:	4d 01 46 48          	add    QWORD PTR [r14+0x48],r8
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	40                   	rex
  5d:	40                   	rex
  5e:	4d 01 46 50          	add    QWORD PTR [r14+0x50],r8
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	40                   	rex
  67:	4d 01 46 58          	add    QWORD PTR [r14+0x58],r8
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	40                   	rex
  6f:	40                   	rex
  70:	4d 01 46 60          	add    QWORD PTR [r14+0x60],r8
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	40                   	rex
  79:	4d 01 46 68          	add    QWORD PTR [r14+0x68],r8
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	40                   	rex
  81:	40                   	rex
  82:	4d 01 46 70          	add    QWORD PTR [r14+0x70],r8
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	40                   	rex
  8b:	4d 01 46 78          	add    QWORD PTR [r14+0x78],r8

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.14
- Reference cycles: 17.0
- UOPS_EXECUTED.THREAD: 65.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.81
- UOPS_PORT_1: 7.49
- UOPS_PORT_2: 11.61
- UOPS_PORT_3: 12.03
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 7.72
- UOPS_PORT_6: 8.22
- UOPS_PORT_7: 8.37
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	4d 01 06             	add    QWORD PTR [r14],r8
   3:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
   7:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
   b:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8
   f:	4d 01 46 20          	add    QWORD PTR [r14+0x20],r8
  13:	4d 01 46 28          	add    QWORD PTR [r14+0x28],r8
  17:	4d 01 46 30          	add    QWORD PTR [r14+0x30],r8
  1b:	4d 01 46 38          	add    QWORD PTR [r14+0x38],r8
  1f:	4d 01 46 40          	add    QWORD PTR [r14+0x40],r8
  23:	4d 01 46 48          	add    QWORD PTR [r14+0x48],r8
  27:	4d 01 46 50          	add    QWORD PTR [r14+0x50],r8
  2b:	4d 01 46 58          	add    QWORD PTR [r14+0x58],r8
  2f:	4d 01 46 60          	add    QWORD PTR [r14+0x60],r8
  33:	4d 01 46 68          	add    QWORD PTR [r14+0x68],r8
  37:	4d 01 46 70          	add    QWORD PTR [r14+0x70],r8
  3b:	4d 01 46 78          	add    QWORD PTR [r14+0x78],r8

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.11
- Reference cycles: 16.96
- UOPS_EXECUTED.THREAD: 64.12
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 7.08
- UOPS_PORT_1: 7.62
- UOPS_PORT_2: 11.48
- UOPS_PORT_3: 11.83
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 7.63
- UOPS_PORT_6: 7.19
- UOPS_PORT_7: 8.71
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	4d 01 06             	add    QWORD PTR [r14],r8
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	4d 01 46 08          	add    QWORD PTR [r14+0x8],r8
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	4d 01 46 10          	add    QWORD PTR [r14+0x10],r8
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	4d 01 46 18          	add    QWORD PTR [r14+0x18],r8
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	40                   	rex
  28:	4d 01 46 20          	add    QWORD PTR [r14+0x20],r8
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	4d 01 46 28          	add    QWORD PTR [r14+0x28],r8
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	40                   	rex
  3a:	4d 01 46 30          	add    QWORD PTR [r14+0x30],r8
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	4d 01 46 38          	add    QWORD PTR [r14+0x38],r8
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	4d 01 46 40          	add    QWORD PTR [r14+0x40],r8
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	40                   	rex
  55:	4d 01 46 48          	add    QWORD PTR [r14+0x48],r8
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	40                   	rex
  5d:	40                   	rex
  5e:	4d 01 46 50          	add    QWORD PTR [r14+0x50],r8
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	40                   	rex
  67:	4d 01 46 58          	add    QWORD PTR [r14+0x58],r8
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	40                   	rex
  6f:	40                   	rex
  70:	4d 01 46 60          	add    QWORD PTR [r14+0x60],r8
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	40                   	rex
  79:	4d 01 46 68          	add    QWORD PTR [r14+0x68],r8
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	40                   	rex
  81:	40                   	rex
  82:	4d 01 46 70          	add    QWORD PTR [r14+0x70],r8
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	40                   	rex
  8b:	4d 01 46 78          	add    QWORD PTR [r14+0x78],r8

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.11
- Reference cycles: 16.96
- UOPS_EXECUTED.THREAD: 64.12
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 7.07
- UOPS_PORT_1: 7.61
- UOPS_PORT_2: 11.55
- UOPS_PORT_3: 11.82
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 7.63
- UOPS_PORT_6: 7.19
- UOPS_PORT_7: 8.71
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 6.0
- Reference cycles: 6.31
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.82
- UOPS_PORT_1: 1.81
- UOPS_PORT_2: 0.95
- UOPS_PORT_3: 1.05
- UOPS_PORT_4: 5.51
- UOPS_PORT_5: 1.84
- UOPS_PORT_6: 1.02
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8
   4:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.02
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.66
- UOPS_PORT_1: 1.67
- UOPS_PORT_2: 0.93
- UOPS_PORT_3: 1.07
- UOPS_PORT_4: 5.35
- UOPS_PORT_5: 1.67
- UOPS_PORT_6: 0.97
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8
   4:	90                   	nop
   5:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.02
- Reference cycles: 6.34
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.72
- UOPS_PORT_1: 1.73
- UOPS_PORT_2: 0.92
- UOPS_PORT_3: 1.08
- UOPS_PORT_4: 5.92
- UOPS_PORT_5: 1.72
- UOPS_PORT_6: 1.72
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.0
- Reference cycles: 6.33
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.87
- UOPS_PORT_1: 1.89
- UOPS_PORT_2: 0.93
- UOPS_PORT_3: 1.07
- UOPS_PORT_4: 6.0
- UOPS_PORT_5: 1.89
- UOPS_PORT_6: 1.36
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.0
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.81
- UOPS_PORT_1: 1.81
- UOPS_PORT_2: 0.94
- UOPS_PORT_3: 1.06
- UOPS_PORT_4: 5.5
- UOPS_PORT_5: 1.82
- UOPS_PORT_6: 1.15
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.0
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.81
- UOPS_PORT_1: 1.81
- UOPS_PORT_2: 0.94
- UOPS_PORT_3: 1.06
- UOPS_PORT_4: 5.49
- UOPS_PORT_5: 1.81
- UOPS_PORT_6: 1.07
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8
   4:	4f 01 44 2e 08       	add    QWORD PTR [r14+r13*1+0x8],r8
   9:	4f 01 44 2e 10       	add    QWORD PTR [r14+r13*1+0x10],r8
   e:	4f 01 44 2e 18       	add    QWORD PTR [r14+r13*1+0x18],r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.11
- Reference cycles: 6.43
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.31
- UOPS_PORT_1: 2.45
- UOPS_PORT_2: 3.94
- UOPS_PORT_3: 4.06
- UOPS_PORT_4: 4.98
- UOPS_PORT_5: 2.2
- UOPS_PORT_6: 1.95
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8
   4:	4f 01 44 2e 08       	add    QWORD PTR [r14+r13*1+0x8],r8
   9:	4f 01 44 2e 10       	add    QWORD PTR [r14+r13*1+0x10],r8
   e:	4f 01 44 2e 18       	add    QWORD PTR [r14+r13*1+0x18],r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 6.01
- Reference cycles: 6.33
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.26
- UOPS_PORT_1: 2.1
- UOPS_PORT_2: 3.94
- UOPS_PORT_3: 4.06
- UOPS_PORT_4: 4.86
- UOPS_PORT_5: 2.21
- UOPS_PORT_6: 2.64
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8
   4:	4f 01 44 2e 08       	add    QWORD PTR [r14+r13*1+0x8],r8
   9:	4f 01 44 2e 10       	add    QWORD PTR [r14+r13*1+0x10],r8
   e:	4f 01 44 2e 18       	add    QWORD PTR [r14+r13*1+0x18],r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 6.01
- Reference cycles: 6.33
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.26
- UOPS_PORT_1: 2.33
- UOPS_PORT_2: 3.95
- UOPS_PORT_3: 4.06
- UOPS_PORT_4: 4.73
- UOPS_PORT_5: 2.25
- UOPS_PORT_6: 1.85
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8
   4:	4f 01 44 2e 08       	add    QWORD PTR [r14+r13*1+0x8],r8
   9:	4f 01 44 2e 10       	add    QWORD PTR [r14+r13*1+0x10],r8
   e:	4f 01 44 2e 18       	add    QWORD PTR [r14+r13*1+0x18],r8
  13:	4f 01 44 2e 20       	add    QWORD PTR [r14+r13*1+0x20],r8
  18:	4f 01 44 2e 28       	add    QWORD PTR [r14+r13*1+0x28],r8
  1d:	4f 01 44 2e 30       	add    QWORD PTR [r14+r13*1+0x30],r8
  22:	4f 01 44 2e 38       	add    QWORD PTR [r14+r13*1+0x38],r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 8.4
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.29
- UOPS_PORT_1: 2.37
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 2.67
- UOPS_PORT_6: 0.67
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8
   4:	4f 01 44 2e 08       	add    QWORD PTR [r14+r13*1+0x8],r8
   9:	4f 01 44 2e 10       	add    QWORD PTR [r14+r13*1+0x10],r8
   e:	4f 01 44 2e 18       	add    QWORD PTR [r14+r13*1+0x18],r8
  13:	4f 01 44 2e 20       	add    QWORD PTR [r14+r13*1+0x20],r8
  18:	4f 01 44 2e 28       	add    QWORD PTR [r14+r13*1+0x28],r8
  1d:	4f 01 44 2e 30       	add    QWORD PTR [r14+r13*1+0x30],r8
  22:	4f 01 44 2e 38       	add    QWORD PTR [r14+r13*1+0x38],r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.03
- Reference cycles: 8.46
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.4
- UOPS_PORT_1: 2.4
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 2.6
- UOPS_PORT_6: 1.6
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8
   4:	4f 01 44 2e 08       	add    QWORD PTR [r14+r13*1+0x8],r8
   9:	4f 01 44 2e 10       	add    QWORD PTR [r14+r13*1+0x10],r8
   e:	4f 01 44 2e 18       	add    QWORD PTR [r14+r13*1+0x18],r8
  13:	4f 01 44 2e 20       	add    QWORD PTR [r14+r13*1+0x20],r8
  18:	4f 01 44 2e 28       	add    QWORD PTR [r14+r13*1+0x28],r8
  1d:	4f 01 44 2e 30       	add    QWORD PTR [r14+r13*1+0x30],r8
  22:	4f 01 44 2e 38       	add    QWORD PTR [r14+r13*1+0x38],r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.03
- Reference cycles: 8.45
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.29
- UOPS_PORT_1: 2.41
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 2.64
- UOPS_PORT_6: 0.76
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8
   4:	4f 01 44 2e 08       	add    QWORD PTR [r14+r13*1+0x8],r8
   9:	4f 01 44 2e 10       	add    QWORD PTR [r14+r13*1+0x10],r8
   e:	4f 01 44 2e 18       	add    QWORD PTR [r14+r13*1+0x18],r8
  13:	4f 01 44 2e 20       	add    QWORD PTR [r14+r13*1+0x20],r8
  18:	4f 01 44 2e 28       	add    QWORD PTR [r14+r13*1+0x28],r8
  1d:	4f 01 44 2e 30       	add    QWORD PTR [r14+r13*1+0x30],r8
  22:	4f 01 44 2e 38       	add    QWORD PTR [r14+r13*1+0x38],r8
  27:	4f 01 44 2e 40       	add    QWORD PTR [r14+r13*1+0x40],r8
  2c:	4f 01 44 2e 48       	add    QWORD PTR [r14+r13*1+0x48],r8
  31:	4f 01 44 2e 50       	add    QWORD PTR [r14+r13*1+0x50],r8
  36:	4f 01 44 2e 58       	add    QWORD PTR [r14+r13*1+0x58],r8
  3b:	4f 01 44 2e 60       	add    QWORD PTR [r14+r13*1+0x60],r8
  40:	4f 01 44 2e 68       	add    QWORD PTR [r14+r13*1+0x68],r8
  45:	4f 01 44 2e 70       	add    QWORD PTR [r14+r13*1+0x70],r8
  4a:	4f 01 44 2e 78       	add    QWORD PTR [r14+r13*1+0x78],r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 16.8
- UOPS_EXECUTED.THREAD: 64.0
- RETIRE_SLOTS: 48.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.57
- UOPS_PORT_1: 4.77
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 16.0
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 5.33
- UOPS_PORT_6: 1.33
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8
   4:	4f 01 44 2e 08       	add    QWORD PTR [r14+r13*1+0x8],r8
   9:	4f 01 44 2e 10       	add    QWORD PTR [r14+r13*1+0x10],r8
   e:	4f 01 44 2e 18       	add    QWORD PTR [r14+r13*1+0x18],r8
  13:	4f 01 44 2e 20       	add    QWORD PTR [r14+r13*1+0x20],r8
  18:	4f 01 44 2e 28       	add    QWORD PTR [r14+r13*1+0x28],r8
  1d:	4f 01 44 2e 30       	add    QWORD PTR [r14+r13*1+0x30],r8
  22:	4f 01 44 2e 38       	add    QWORD PTR [r14+r13*1+0x38],r8
  27:	4f 01 44 2e 40       	add    QWORD PTR [r14+r13*1+0x40],r8
  2c:	4f 01 44 2e 48       	add    QWORD PTR [r14+r13*1+0x48],r8
  31:	4f 01 44 2e 50       	add    QWORD PTR [r14+r13*1+0x50],r8
  36:	4f 01 44 2e 58       	add    QWORD PTR [r14+r13*1+0x58],r8
  3b:	4f 01 44 2e 60       	add    QWORD PTR [r14+r13*1+0x60],r8
  40:	4f 01 44 2e 68       	add    QWORD PTR [r14+r13*1+0x68],r8
  45:	4f 01 44 2e 70       	add    QWORD PTR [r14+r13*1+0x70],r8
  4a:	4f 01 44 2e 78       	add    QWORD PTR [r14+r13*1+0x78],r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.03
- Reference cycles: 16.87
- UOPS_EXECUTED.THREAD: 65.01
- RETIRE_SLOTS: 49.0
- UOPS_MITE: 0.07
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.6
- UOPS_PORT_1: 4.9
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 16.01
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 5.25
- UOPS_PORT_6: 2.25
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With loop_count=100 and unroll_count=10

Code:

   0:	4f 01 04 2e          	add    QWORD PTR [r14+r13*1],r8
   4:	4f 01 44 2e 08       	add    QWORD PTR [r14+r13*1+0x8],r8
   9:	4f 01 44 2e 10       	add    QWORD PTR [r14+r13*1+0x10],r8
   e:	4f 01 44 2e 18       	add    QWORD PTR [r14+r13*1+0x18],r8
  13:	4f 01 44 2e 20       	add    QWORD PTR [r14+r13*1+0x20],r8
  18:	4f 01 44 2e 28       	add    QWORD PTR [r14+r13*1+0x28],r8
  1d:	4f 01 44 2e 30       	add    QWORD PTR [r14+r13*1+0x30],r8
  22:	4f 01 44 2e 38       	add    QWORD PTR [r14+r13*1+0x38],r8
  27:	4f 01 44 2e 40       	add    QWORD PTR [r14+r13*1+0x40],r8
  2c:	4f 01 44 2e 48       	add    QWORD PTR [r14+r13*1+0x48],r8
  31:	4f 01 44 2e 50       	add    QWORD PTR [r14+r13*1+0x50],r8
  36:	4f 01 44 2e 58       	add    QWORD PTR [r14+r13*1+0x58],r8
  3b:	4f 01 44 2e 60       	add    QWORD PTR [r14+r13*1+0x60],r8
  40:	4f 01 44 2e 68       	add    QWORD PTR [r14+r13*1+0x68],r8
  45:	4f 01 44 2e 70       	add    QWORD PTR [r14+r13*1+0x70],r8
  4a:	4f 01 44 2e 78       	add    QWORD PTR [r14+r13*1+0x78],r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.02
- Reference cycles: 16.86
- UOPS_EXECUTED.THREAD: 64.11
- RETIRE_SLOTS: 48.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.58
- UOPS_PORT_1: 4.8
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 16.01
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 5.3
- UOPS_PORT_6: 1.42
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

ADD (M64, R64) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10