ADD (M64, I32)

With unroll_count=500 and no inner loop

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 6.01
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.83
- UOPS_PORT_1: 1.83
- UOPS_PORT_2: 0.57
- UOPS_PORT_3: 0.92
- UOPS_PORT_4: 5.57
- UOPS_PORT_5: 1.99
- UOPS_PORT_6: 1.47
- UOPS_PORT_7: 0.51
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   7:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.42
- Reference cycles: 6.76
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.72
- UOPS_PORT_1: 1.75
- UOPS_PORT_2: 0.71
- UOPS_PORT_3: 0.78
- UOPS_PORT_4: 4.22
- UOPS_PORT_5: 1.79
- UOPS_PORT_6: 1.78
- UOPS_PORT_7: 0.51
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   7:	90                   	nop
   8:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 7.42
- Reference cycles: 7.81
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.95
- UOPS_PORT_1: 1.96
- UOPS_PORT_2: 0.71
- UOPS_PORT_3: 0.74
- UOPS_PORT_4: 1.63
- UOPS_PORT_5: 2.25
- UOPS_PORT_6: 1.3
- UOPS_PORT_7: 0.55
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.01
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.67
- UOPS_PORT_1: 1.75
- UOPS_PORT_2: 0.72
- UOPS_PORT_3: 0.75
- UOPS_PORT_4: 5.91
- UOPS_PORT_5: 1.73
- UOPS_PORT_6: 1.75
- UOPS_PORT_7: 0.54
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.0
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.77
- UOPS_PORT_1: 1.81
- UOPS_PORT_2: 0.99
- UOPS_PORT_3: 0.98
- UOPS_PORT_4: 5.89
- UOPS_PORT_5: 1.83
- UOPS_PORT_6: 1.89
- UOPS_PORT_7: 0.03
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.0
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.82
- UOPS_PORT_1: 1.84
- UOPS_PORT_2: 0.99
- UOPS_PORT_3: 0.99
- UOPS_PORT_4: 5.95
- UOPS_PORT_5: 1.85
- UOPS_PORT_6: 1.94
- UOPS_PORT_7: 0.03
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.0
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.77
- UOPS_PORT_1: 1.78
- UOPS_PORT_2: 0.78
- UOPS_PORT_3: 0.94
- UOPS_PORT_4: 5.65
- UOPS_PORT_5: 1.79
- UOPS_PORT_6: 1.77
- UOPS_PORT_7: 0.28
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.01
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.72
- UOPS_PORT_1: 1.73
- UOPS_PORT_2: 0.78
- UOPS_PORT_3: 0.94
- UOPS_PORT_4: 5.47
- UOPS_PORT_5: 1.73
- UOPS_PORT_6: 1.73
- UOPS_PORT_7: 0.28
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   7:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
   e:	01 
   f:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  16:	01 
  17:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  1e:	01

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.39
- Reference cycles: 6.73
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.77
- UOPS_PORT_1: 2.9
- UOPS_PORT_2: 2.87
- UOPS_PORT_3: 2.92
- UOPS_PORT_4: 5.8
- UOPS_PORT_5: 2.76
- UOPS_PORT_6: 2.27
- UOPS_PORT_7: 2.22
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   7:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
   e:	01 
   f:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  16:	01 
  17:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  1e:	01

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 6.01
- Reference cycles: 6.33
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.29
- UOPS_PORT_1: 2.38
- UOPS_PORT_2: 3.06
- UOPS_PORT_3: 3.06
- UOPS_PORT_4: 5.65
- UOPS_PORT_5: 2.55
- UOPS_PORT_6: 2.82
- UOPS_PORT_7: 1.89
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   8:	40                   	rex
   9:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
  10:	01 
  11:	40                   	rex
  12:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  19:	01 
  1a:	40                   	rex
  1b:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  22:	01

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 6.01
- Reference cycles: 6.33
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.34
- UOPS_PORT_1: 2.43
- UOPS_PORT_2: 3.05
- UOPS_PORT_3: 3.05
- UOPS_PORT_4: 5.8
- UOPS_PORT_5: 2.62
- UOPS_PORT_6: 2.91
- UOPS_PORT_7: 1.9
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   7:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
   e:	01 
   f:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  16:	01 
  17:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  1e:	01

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 6.17
- Reference cycles: 6.5
- UOPS_EXECUTED.THREAD: 16.06
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.51
- UOPS_PORT_1: 2.56
- UOPS_PORT_2: 2.97
- UOPS_PORT_3: 2.89
- UOPS_PORT_4: 5.86
- UOPS_PORT_5: 2.64
- UOPS_PORT_6: 2.64
- UOPS_PORT_7: 2.15
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   8:	40                   	rex
   9:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
  10:	01 
  11:	40                   	rex
  12:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  19:	01 
  1a:	40                   	rex
  1b:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  22:	01

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 6.17
- Reference cycles: 6.5
- UOPS_EXECUTED.THREAD: 16.06
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.51
- UOPS_PORT_1: 2.56
- UOPS_PORT_2: 2.97
- UOPS_PORT_3: 2.89
- UOPS_PORT_4: 5.86
- UOPS_PORT_5: 2.64
- UOPS_PORT_6: 2.64
- UOPS_PORT_7: 2.15
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   7:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
   e:	01 
   f:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  16:	01 
  17:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  1e:	01 
  1f:	49 81 46 20 00 00 00 	add    QWORD PTR [r14+0x20],0x1000000
  26:	01 
  27:	49 81 46 28 00 00 00 	add    QWORD PTR [r14+0x28],0x1000000
  2e:	01 
  2f:	49 81 46 30 00 00 00 	add    QWORD PTR [r14+0x30],0x1000000
  36:	01 
  37:	49 81 46 38 00 00 00 	add    QWORD PTR [r14+0x38],0x1000000
  3e:	01

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.3
- Reference cycles: 8.77
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.93
- UOPS_PORT_1: 4.23
- UOPS_PORT_2: 5.54
- UOPS_PORT_3: 5.59
- UOPS_PORT_4: 8.01
- UOPS_PORT_5: 4.4
- UOPS_PORT_6: 2.98
- UOPS_PORT_7: 4.87
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   7:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
   e:	01 
   f:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  16:	01 
  17:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  1e:	01 
  1f:	49 81 46 20 00 00 00 	add    QWORD PTR [r14+0x20],0x1000000
  26:	01 
  27:	49 81 46 28 00 00 00 	add    QWORD PTR [r14+0x28],0x1000000
  2e:	01 
  2f:	49 81 46 30 00 00 00 	add    QWORD PTR [r14+0x30],0x1000000
  36:	01 
  37:	49 81 46 38 00 00 00 	add    QWORD PTR [r14+0x38],0x1000000
  3e:	01

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.12
- Reference cycles: 8.54
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.79
- UOPS_PORT_1: 3.83
- UOPS_PORT_2: 5.76
- UOPS_PORT_3: 5.75
- UOPS_PORT_4: 8.01
- UOPS_PORT_5: 3.94
- UOPS_PORT_6: 4.73
- UOPS_PORT_7: 4.51
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   8:	40                   	rex
   9:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
  10:	01 
  11:	40                   	rex
  12:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  19:	01 
  1a:	40                   	rex
  1b:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  22:	01 
  23:	40                   	rex
  24:	49 81 46 20 00 00 00 	add    QWORD PTR [r14+0x20],0x1000000
  2b:	01 
  2c:	40                   	rex
  2d:	49 81 46 28 00 00 00 	add    QWORD PTR [r14+0x28],0x1000000
  34:	01 
  35:	40                   	rex
  36:	49 81 46 30 00 00 00 	add    QWORD PTR [r14+0x30],0x1000000
  3d:	01 
  3e:	40                   	rex
  3f:	49 81 46 38 00 00 00 	add    QWORD PTR [r14+0x38],0x1000000
  46:	01

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.15
- Reference cycles: 8.57
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.79
- UOPS_PORT_1: 3.83
- UOPS_PORT_2: 5.64
- UOPS_PORT_3: 5.75
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 3.94
- UOPS_PORT_6: 4.71
- UOPS_PORT_7: 4.62
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   7:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
   e:	01 
   f:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  16:	01 
  17:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  1e:	01 
  1f:	49 81 46 20 00 00 00 	add    QWORD PTR [r14+0x20],0x1000000
  26:	01 
  27:	49 81 46 28 00 00 00 	add    QWORD PTR [r14+0x28],0x1000000
  2e:	01 
  2f:	49 81 46 30 00 00 00 	add    QWORD PTR [r14+0x30],0x1000000
  36:	01 
  37:	49 81 46 38 00 00 00 	add    QWORD PTR [r14+0x38],0x1000000
  3e:	01

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.17
- Reference cycles: 8.6
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.75
- UOPS_PORT_1: 3.82
- UOPS_PORT_2: 5.7
- UOPS_PORT_3: 5.84
- UOPS_PORT_4: 8.01
- UOPS_PORT_5: 3.89
- UOPS_PORT_6: 4.04
- UOPS_PORT_7: 4.47
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   8:	40                   	rex
   9:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
  10:	01 
  11:	40                   	rex
  12:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  19:	01 
  1a:	40                   	rex
  1b:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  22:	01 
  23:	40                   	rex
  24:	49 81 46 20 00 00 00 	add    QWORD PTR [r14+0x20],0x1000000
  2b:	01 
  2c:	40                   	rex
  2d:	49 81 46 28 00 00 00 	add    QWORD PTR [r14+0x28],0x1000000
  34:	01 
  35:	40                   	rex
  36:	49 81 46 30 00 00 00 	add    QWORD PTR [r14+0x30],0x1000000
  3d:	01 
  3e:	40                   	rex
  3f:	49 81 46 38 00 00 00 	add    QWORD PTR [r14+0x38],0x1000000
  46:	01

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.17
- Reference cycles: 8.6
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.75
- UOPS_PORT_1: 3.82
- UOPS_PORT_2: 5.7
- UOPS_PORT_3: 5.84
- UOPS_PORT_4: 8.01
- UOPS_PORT_5: 3.89
- UOPS_PORT_6: 4.04
- UOPS_PORT_7: 4.47
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   7:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
   e:	01 
   f:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  16:	01 
  17:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  1e:	01 
  1f:	49 81 46 20 00 00 00 	add    QWORD PTR [r14+0x20],0x1000000
  26:	01 
  27:	49 81 46 28 00 00 00 	add    QWORD PTR [r14+0x28],0x1000000
  2e:	01 
  2f:	49 81 46 30 00 00 00 	add    QWORD PTR [r14+0x30],0x1000000
  36:	01 
  37:	49 81 46 38 00 00 00 	add    QWORD PTR [r14+0x38],0x1000000
  3e:	01 
  3f:	49 81 46 40 00 00 00 	add    QWORD PTR [r14+0x40],0x1000000
  46:	01 
  47:	49 81 46 48 00 00 00 	add    QWORD PTR [r14+0x48],0x1000000
  4e:	01 
  4f:	49 81 46 50 00 00 00 	add    QWORD PTR [r14+0x50],0x1000000
  56:	01 
  57:	49 81 46 58 00 00 00 	add    QWORD PTR [r14+0x58],0x1000000
  5e:	01 
  5f:	49 81 46 60 00 00 00 	add    QWORD PTR [r14+0x60],0x1000000
  66:	01 
  67:	49 81 46 68 00 00 00 	add    QWORD PTR [r14+0x68],0x1000000
  6e:	01 
  6f:	49 81 46 70 00 00 00 	add    QWORD PTR [r14+0x70],0x1000000
  76:	01 
  77:	49 81 46 78 00 00 00 	add    QWORD PTR [r14+0x78],0x1000000
  7e:	01

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.13
- Reference cycles: 17.07
- UOPS_EXECUTED.THREAD: 64.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 7.66
- UOPS_PORT_1: 7.71
- UOPS_PORT_2: 11.02
- UOPS_PORT_3: 11.16
- UOPS_PORT_4: 16.01
- UOPS_PORT_5: 7.54
- UOPS_PORT_6: 6.41
- UOPS_PORT_7: 9.82
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   7:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
   e:	01 
   f:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  16:	01 
  17:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  1e:	01 
  1f:	49 81 46 20 00 00 00 	add    QWORD PTR [r14+0x20],0x1000000
  26:	01 
  27:	49 81 46 28 00 00 00 	add    QWORD PTR [r14+0x28],0x1000000
  2e:	01 
  2f:	49 81 46 30 00 00 00 	add    QWORD PTR [r14+0x30],0x1000000
  36:	01 
  37:	49 81 46 38 00 00 00 	add    QWORD PTR [r14+0x38],0x1000000
  3e:	01 
  3f:	49 81 46 40 00 00 00 	add    QWORD PTR [r14+0x40],0x1000000
  46:	01 
  47:	49 81 46 48 00 00 00 	add    QWORD PTR [r14+0x48],0x1000000
  4e:	01 
  4f:	49 81 46 50 00 00 00 	add    QWORD PTR [r14+0x50],0x1000000
  56:	01 
  57:	49 81 46 58 00 00 00 	add    QWORD PTR [r14+0x58],0x1000000
  5e:	01 
  5f:	49 81 46 60 00 00 00 	add    QWORD PTR [r14+0x60],0x1000000
  66:	01 
  67:	49 81 46 68 00 00 00 	add    QWORD PTR [r14+0x68],0x1000000
  6e:	01 
  6f:	49 81 46 70 00 00 00 	add    QWORD PTR [r14+0x70],0x1000000
  76:	01 
  77:	49 81 46 78 00 00 00 	add    QWORD PTR [r14+0x78],0x1000000
  7e:	01

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 16.85
- UOPS_EXECUTED.THREAD: 65.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.78
- UOPS_PORT_1: 7.45
- UOPS_PORT_2: 11.71
- UOPS_PORT_3: 12.35
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 7.67
- UOPS_PORT_6: 8.2
- UOPS_PORT_7: 8.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   8:	40                   	rex
   9:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
  10:	01 
  11:	40                   	rex
  12:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  19:	01 
  1a:	40                   	rex
  1b:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  22:	01 
  23:	40                   	rex
  24:	49 81 46 20 00 00 00 	add    QWORD PTR [r14+0x20],0x1000000
  2b:	01 
  2c:	40                   	rex
  2d:	49 81 46 28 00 00 00 	add    QWORD PTR [r14+0x28],0x1000000
  34:	01 
  35:	40                   	rex
  36:	49 81 46 30 00 00 00 	add    QWORD PTR [r14+0x30],0x1000000
  3d:	01 
  3e:	40                   	rex
  3f:	49 81 46 38 00 00 00 	add    QWORD PTR [r14+0x38],0x1000000
  46:	01 
  47:	40                   	rex
  48:	49 81 46 40 00 00 00 	add    QWORD PTR [r14+0x40],0x1000000
  4f:	01 
  50:	40                   	rex
  51:	49 81 46 48 00 00 00 	add    QWORD PTR [r14+0x48],0x1000000
  58:	01 
  59:	40                   	rex
  5a:	49 81 46 50 00 00 00 	add    QWORD PTR [r14+0x50],0x1000000
  61:	01 
  62:	40                   	rex
  63:	49 81 46 58 00 00 00 	add    QWORD PTR [r14+0x58],0x1000000
  6a:	01 
  6b:	40                   	rex
  6c:	49 81 46 60 00 00 00 	add    QWORD PTR [r14+0x60],0x1000000
  73:	01 
  74:	40                   	rex
  75:	49 81 46 68 00 00 00 	add    QWORD PTR [r14+0x68],0x1000000
  7c:	01 
  7d:	40                   	rex
  7e:	49 81 46 70 00 00 00 	add    QWORD PTR [r14+0x70],0x1000000
  85:	01 
  86:	40                   	rex
  87:	49 81 46 78 00 00 00 	add    QWORD PTR [r14+0x78],0x1000000
  8e:	01

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 16.86
- UOPS_EXECUTED.THREAD: 65.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.78
- UOPS_PORT_1: 7.45
- UOPS_PORT_2: 11.71
- UOPS_PORT_3: 12.35
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 7.67
- UOPS_PORT_6: 8.2
- UOPS_PORT_7: 7.96
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   7:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
   e:	01 
   f:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  16:	01 
  17:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  1e:	01 
  1f:	49 81 46 20 00 00 00 	add    QWORD PTR [r14+0x20],0x1000000
  26:	01 
  27:	49 81 46 28 00 00 00 	add    QWORD PTR [r14+0x28],0x1000000
  2e:	01 
  2f:	49 81 46 30 00 00 00 	add    QWORD PTR [r14+0x30],0x1000000
  36:	01 
  37:	49 81 46 38 00 00 00 	add    QWORD PTR [r14+0x38],0x1000000
  3e:	01 
  3f:	49 81 46 40 00 00 00 	add    QWORD PTR [r14+0x40],0x1000000
  46:	01 
  47:	49 81 46 48 00 00 00 	add    QWORD PTR [r14+0x48],0x1000000
  4e:	01 
  4f:	49 81 46 50 00 00 00 	add    QWORD PTR [r14+0x50],0x1000000
  56:	01 
  57:	49 81 46 58 00 00 00 	add    QWORD PTR [r14+0x58],0x1000000
  5e:	01 
  5f:	49 81 46 60 00 00 00 	add    QWORD PTR [r14+0x60],0x1000000
  66:	01 
  67:	49 81 46 68 00 00 00 	add    QWORD PTR [r14+0x68],0x1000000
  6e:	01 
  6f:	49 81 46 70 00 00 00 	add    QWORD PTR [r14+0x70],0x1000000
  76:	01 
  77:	49 81 46 78 00 00 00 	add    QWORD PTR [r14+0x78],0x1000000
  7e:	01

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.1
- Reference cycles: 16.95
- UOPS_EXECUTED.THREAD: 64.11
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.42
- UOPS_PORT_1: 5.51
- UOPS_PORT_2: 10.11
- UOPS_PORT_3: 11.9
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 4.3
- UOPS_PORT_6: 4.23
- UOPS_PORT_7: 10.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	49 81 06 00 00 00 01 	add    QWORD PTR [r14],0x1000000
   8:	40                   	rex
   9:	49 81 46 08 00 00 00 	add    QWORD PTR [r14+0x8],0x1000000
  10:	01 
  11:	40                   	rex
  12:	49 81 46 10 00 00 00 	add    QWORD PTR [r14+0x10],0x1000000
  19:	01 
  1a:	40                   	rex
  1b:	49 81 46 18 00 00 00 	add    QWORD PTR [r14+0x18],0x1000000
  22:	01 
  23:	40                   	rex
  24:	49 81 46 20 00 00 00 	add    QWORD PTR [r14+0x20],0x1000000
  2b:	01 
  2c:	40                   	rex
  2d:	49 81 46 28 00 00 00 	add    QWORD PTR [r14+0x28],0x1000000
  34:	01 
  35:	40                   	rex
  36:	49 81 46 30 00 00 00 	add    QWORD PTR [r14+0x30],0x1000000
  3d:	01 
  3e:	40                   	rex
  3f:	49 81 46 38 00 00 00 	add    QWORD PTR [r14+0x38],0x1000000
  46:	01 
  47:	40                   	rex
  48:	49 81 46 40 00 00 00 	add    QWORD PTR [r14+0x40],0x1000000
  4f:	01 
  50:	40                   	rex
  51:	49 81 46 48 00 00 00 	add    QWORD PTR [r14+0x48],0x1000000
  58:	01 
  59:	40                   	rex
  5a:	49 81 46 50 00 00 00 	add    QWORD PTR [r14+0x50],0x1000000
  61:	01 
  62:	40                   	rex
  63:	49 81 46 58 00 00 00 	add    QWORD PTR [r14+0x58],0x1000000
  6a:	01 
  6b:	40                   	rex
  6c:	49 81 46 60 00 00 00 	add    QWORD PTR [r14+0x60],0x1000000
  73:	01 
  74:	40                   	rex
  75:	49 81 46 68 00 00 00 	add    QWORD PTR [r14+0x68],0x1000000
  7c:	01 
  7d:	40                   	rex
  7e:	49 81 46 70 00 00 00 	add    QWORD PTR [r14+0x70],0x1000000
  85:	01 
  86:	40                   	rex
  87:	49 81 46 78 00 00 00 	add    QWORD PTR [r14+0x78],0x1000000
  8e:	01

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.1
- Reference cycles: 16.95
- UOPS_EXECUTED.THREAD: 64.11
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.42
- UOPS_PORT_1: 5.51
- UOPS_PORT_2: 10.11
- UOPS_PORT_3: 11.9
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 4.3
- UOPS_PORT_6: 4.23
- UOPS_PORT_7: 10.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 6.0
- Reference cycles: 6.31
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.82
- UOPS_PORT_1: 1.81
- UOPS_PORT_2: 0.95
- UOPS_PORT_3: 1.05
- UOPS_PORT_4: 5.51
- UOPS_PORT_5: 1.84
- UOPS_PORT_6: 1.09
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.02
- Reference cycles: 6.34
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.66
- UOPS_PORT_1: 1.67
- UOPS_PORT_2: 0.93
- UOPS_PORT_3: 1.07
- UOPS_PORT_4: 5.35
- UOPS_PORT_5: 1.67
- UOPS_PORT_6: 0.97
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	90                   	nop
   9:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.02
- Reference cycles: 6.33
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.72
- UOPS_PORT_1: 1.73
- UOPS_PORT_2: 0.92
- UOPS_PORT_3: 1.08
- UOPS_PORT_4: 5.92
- UOPS_PORT_5: 1.72
- UOPS_PORT_6: 1.73
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.0
- Reference cycles: 6.31
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.87
- UOPS_PORT_1: 1.89
- UOPS_PORT_2: 0.93
- UOPS_PORT_3: 1.07
- UOPS_PORT_4: 6.0
- UOPS_PORT_5: 1.89
- UOPS_PORT_6: 1.36
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.0
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.81
- UOPS_PORT_1: 1.81
- UOPS_PORT_2: 0.94
- UOPS_PORT_3: 1.06
- UOPS_PORT_4: 5.18
- UOPS_PORT_5: 1.75
- UOPS_PORT_6: 1.15
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   8:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.0
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.81
- UOPS_PORT_1: 1.81
- UOPS_PORT_2: 0.94
- UOPS_PORT_3: 1.06
- UOPS_PORT_4: 5.5
- UOPS_PORT_5: 1.82
- UOPS_PORT_6: 1.15
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.0
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.81
- UOPS_PORT_1: 1.81
- UOPS_PORT_2: 0.94
- UOPS_PORT_3: 1.06
- UOPS_PORT_4: 5.49
- UOPS_PORT_5: 1.81
- UOPS_PORT_6: 1.07
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   8:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.0
- Reference cycles: 6.32
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.81
- UOPS_PORT_1: 1.81
- UOPS_PORT_2: 0.94
- UOPS_PORT_3: 1.06
- UOPS_PORT_4: 5.49
- UOPS_PORT_5: 1.81
- UOPS_PORT_6: 1.07
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
   f:	00 01 
  11:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  18:	00 01 
  1a:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  21:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.11
- Reference cycles: 6.45
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.31
- UOPS_PORT_1: 2.45
- UOPS_PORT_2: 3.94
- UOPS_PORT_3: 4.06
- UOPS_PORT_4: 4.98
- UOPS_PORT_5: 2.2
- UOPS_PORT_6: 1.95
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
   f:	00 01 
  11:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  18:	00 01 
  1a:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  21:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 6.01
- Reference cycles: 6.33
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.26
- UOPS_PORT_1: 2.1
- UOPS_PORT_2: 3.94
- UOPS_PORT_3: 4.06
- UOPS_PORT_4: 4.86
- UOPS_PORT_5: 2.21
- UOPS_PORT_6: 2.64
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   8:	01 
   9:	40                   	rex
   a:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
  11:	00 01 
  13:	40                   	rex
  14:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  1b:	00 01 
  1d:	40                   	rex
  1e:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  25:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 6.01
- Reference cycles: 6.33
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.26
- UOPS_PORT_1: 2.1
- UOPS_PORT_2: 3.94
- UOPS_PORT_3: 4.06
- UOPS_PORT_4: 4.86
- UOPS_PORT_5: 2.21
- UOPS_PORT_6: 2.64
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
   f:	00 01 
  11:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  18:	00 01 
  1a:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  21:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 6.02
- Reference cycles: 6.34
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.26
- UOPS_PORT_1: 2.33
- UOPS_PORT_2: 3.95
- UOPS_PORT_3: 4.06
- UOPS_PORT_4: 4.73
- UOPS_PORT_5: 2.25
- UOPS_PORT_6: 1.85
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   8:	01 
   9:	40                   	rex
   a:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
  11:	00 01 
  13:	40                   	rex
  14:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  1b:	00 01 
  1d:	40                   	rex
  1e:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  25:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 6.02
- Reference cycles: 6.34
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.24
- UOPS_PORT_1: 2.3
- UOPS_PORT_2: 3.94
- UOPS_PORT_3: 4.06
- UOPS_PORT_4: 4.6
- UOPS_PORT_5: 2.21
- UOPS_PORT_6: 1.81
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
   f:	00 01 
  11:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  18:	00 01 
  1a:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  21:	00 01 
  23:	4b 81 44 2e 20 00 00 	add    QWORD PTR [r14+r13*1+0x20],0x1000000
  2a:	00 01 
  2c:	4b 81 44 2e 28 00 00 	add    QWORD PTR [r14+r13*1+0x28],0x1000000
  33:	00 01 
  35:	4b 81 44 2e 30 00 00 	add    QWORD PTR [r14+r13*1+0x30],0x1000000
  3c:	00 01 
  3e:	4b 81 44 2e 38 00 00 	add    QWORD PTR [r14+r13*1+0x38],0x1000000
  45:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 8.4
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.29
- UOPS_PORT_1: 2.37
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 2.67
- UOPS_PORT_6: 0.67
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
   f:	00 01 
  11:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  18:	00 01 
  1a:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  21:	00 01 
  23:	4b 81 44 2e 20 00 00 	add    QWORD PTR [r14+r13*1+0x20],0x1000000
  2a:	00 01 
  2c:	4b 81 44 2e 28 00 00 	add    QWORD PTR [r14+r13*1+0x28],0x1000000
  33:	00 01 
  35:	4b 81 44 2e 30 00 00 	add    QWORD PTR [r14+r13*1+0x30],0x1000000
  3c:	00 01 
  3e:	4b 81 44 2e 38 00 00 	add    QWORD PTR [r14+r13*1+0x38],0x1000000
  45:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.22
- Reference cycles: 8.66
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.73
- UOPS_PORT_1: 2.86
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 1.87
- UOPS_PORT_6: 3.34
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   8:	01 
   9:	40                   	rex
   a:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
  11:	00 01 
  13:	40                   	rex
  14:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  1b:	00 01 
  1d:	40                   	rex
  1e:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  25:	00 01 
  27:	40                   	rex
  28:	4b 81 44 2e 20 00 00 	add    QWORD PTR [r14+r13*1+0x20],0x1000000
  2f:	00 01 
  31:	40                   	rex
  32:	4b 81 44 2e 28 00 00 	add    QWORD PTR [r14+r13*1+0x28],0x1000000
  39:	00 01 
  3b:	40                   	rex
  3c:	4b 81 44 2e 30 00 00 	add    QWORD PTR [r14+r13*1+0x30],0x1000000
  43:	00 01 
  45:	40                   	rex
  46:	4b 81 44 2e 38 00 00 	add    QWORD PTR [r14+r13*1+0x38],0x1000000
  4d:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.02
- Reference cycles: 8.44
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.4
- UOPS_PORT_1: 2.4
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 2.6
- UOPS_PORT_6: 1.6
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
   f:	00 01 
  11:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  18:	00 01 
  1a:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  21:	00 01 
  23:	4b 81 44 2e 20 00 00 	add    QWORD PTR [r14+r13*1+0x20],0x1000000
  2a:	00 01 
  2c:	4b 81 44 2e 28 00 00 	add    QWORD PTR [r14+r13*1+0x28],0x1000000
  33:	00 01 
  35:	4b 81 44 2e 30 00 00 	add    QWORD PTR [r14+r13*1+0x30],0x1000000
  3c:	00 01 
  3e:	4b 81 44 2e 38 00 00 	add    QWORD PTR [r14+r13*1+0x38],0x1000000
  45:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.37
- Reference cycles: 8.81
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.28
- UOPS_PORT_1: 3.48
- UOPS_PORT_2: 7.99
- UOPS_PORT_3: 8.02
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 3.26
- UOPS_PORT_6: 2.27
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   8:	01 
   9:	40                   	rex
   a:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
  11:	00 01 
  13:	40                   	rex
  14:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  1b:	00 01 
  1d:	40                   	rex
  1e:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  25:	00 01 
  27:	40                   	rex
  28:	4b 81 44 2e 20 00 00 	add    QWORD PTR [r14+r13*1+0x20],0x1000000
  2f:	00 01 
  31:	40                   	rex
  32:	4b 81 44 2e 28 00 00 	add    QWORD PTR [r14+r13*1+0x28],0x1000000
  39:	00 01 
  3b:	40                   	rex
  3c:	4b 81 44 2e 30 00 00 	add    QWORD PTR [r14+r13*1+0x30],0x1000000
  43:	00 01 
  45:	40                   	rex
  46:	4b 81 44 2e 38 00 00 	add    QWORD PTR [r14+r13*1+0x38],0x1000000
  4d:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.47
- Reference cycles: 8.92
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.28
- UOPS_PORT_1: 3.48
- UOPS_PORT_2: 7.99
- UOPS_PORT_3: 8.02
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 3.26
- UOPS_PORT_6: 2.27
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
   f:	00 01 
  11:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  18:	00 01 
  1a:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  21:	00 01 
  23:	4b 81 44 2e 20 00 00 	add    QWORD PTR [r14+r13*1+0x20],0x1000000
  2a:	00 01 
  2c:	4b 81 44 2e 28 00 00 	add    QWORD PTR [r14+r13*1+0x28],0x1000000
  33:	00 01 
  35:	4b 81 44 2e 30 00 00 	add    QWORD PTR [r14+r13*1+0x30],0x1000000
  3c:	00 01 
  3e:	4b 81 44 2e 38 00 00 	add    QWORD PTR [r14+r13*1+0x38],0x1000000
  45:	00 01 
  47:	4b 81 44 2e 40 00 00 	add    QWORD PTR [r14+r13*1+0x40],0x1000000
  4e:	00 01 
  50:	4b 81 44 2e 48 00 00 	add    QWORD PTR [r14+r13*1+0x48],0x1000000
  57:	00 01 
  59:	4b 81 44 2e 50 00 00 	add    QWORD PTR [r14+r13*1+0x50],0x1000000
  60:	00 01 
  62:	4b 81 44 2e 58 00 00 	add    QWORD PTR [r14+r13*1+0x58],0x1000000
  69:	00 01 
  6b:	4b 81 44 2e 60 00 00 	add    QWORD PTR [r14+r13*1+0x60],0x1000000
  72:	00 01 
  74:	4b 81 44 2e 68 00 00 	add    QWORD PTR [r14+r13*1+0x68],0x1000000
  7b:	00 01 
  7d:	4b 81 44 2e 70 00 00 	add    QWORD PTR [r14+r13*1+0x70],0x1000000
  84:	00 01 
  86:	4b 81 44 2e 78 00 00 	add    QWORD PTR [r14+r13*1+0x78],0x1000000
  8d:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 16.8
- UOPS_EXECUTED.THREAD: 64.0
- RETIRE_SLOTS: 48.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.57
- UOPS_PORT_1: 4.77
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 16.0
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 5.33
- UOPS_PORT_6: 1.33
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
   f:	00 01 
  11:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  18:	00 01 
  1a:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  21:	00 01 
  23:	4b 81 44 2e 20 00 00 	add    QWORD PTR [r14+r13*1+0x20],0x1000000
  2a:	00 01 
  2c:	4b 81 44 2e 28 00 00 	add    QWORD PTR [r14+r13*1+0x28],0x1000000
  33:	00 01 
  35:	4b 81 44 2e 30 00 00 	add    QWORD PTR [r14+r13*1+0x30],0x1000000
  3c:	00 01 
  3e:	4b 81 44 2e 38 00 00 	add    QWORD PTR [r14+r13*1+0x38],0x1000000
  45:	00 01 
  47:	4b 81 44 2e 40 00 00 	add    QWORD PTR [r14+r13*1+0x40],0x1000000
  4e:	00 01 
  50:	4b 81 44 2e 48 00 00 	add    QWORD PTR [r14+r13*1+0x48],0x1000000
  57:	00 01 
  59:	4b 81 44 2e 50 00 00 	add    QWORD PTR [r14+r13*1+0x50],0x1000000
  60:	00 01 
  62:	4b 81 44 2e 58 00 00 	add    QWORD PTR [r14+r13*1+0x58],0x1000000
  69:	00 01 
  6b:	4b 81 44 2e 60 00 00 	add    QWORD PTR [r14+r13*1+0x60],0x1000000
  72:	00 01 
  74:	4b 81 44 2e 68 00 00 	add    QWORD PTR [r14+r13*1+0x68],0x1000000
  7b:	00 01 
  7d:	4b 81 44 2e 70 00 00 	add    QWORD PTR [r14+r13*1+0x70],0x1000000
  84:	00 01 
  86:	4b 81 44 2e 78 00 00 	add    QWORD PTR [r14+r13*1+0x78],0x1000000
  8d:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.02
- Reference cycles: 16.86
- UOPS_EXECUTED.THREAD: 65.01
- RETIRE_SLOTS: 49.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.6
- UOPS_PORT_1: 4.9
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 16.01
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 5.25
- UOPS_PORT_6: 2.25
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   8:	01 
   9:	40                   	rex
   a:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
  11:	00 01 
  13:	40                   	rex
  14:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  1b:	00 01 
  1d:	40                   	rex
  1e:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  25:	00 01 
  27:	40                   	rex
  28:	4b 81 44 2e 20 00 00 	add    QWORD PTR [r14+r13*1+0x20],0x1000000
  2f:	00 01 
  31:	40                   	rex
  32:	4b 81 44 2e 28 00 00 	add    QWORD PTR [r14+r13*1+0x28],0x1000000
  39:	00 01 
  3b:	40                   	rex
  3c:	4b 81 44 2e 30 00 00 	add    QWORD PTR [r14+r13*1+0x30],0x1000000
  43:	00 01 
  45:	40                   	rex
  46:	4b 81 44 2e 38 00 00 	add    QWORD PTR [r14+r13*1+0x38],0x1000000
  4d:	00 01 
  4f:	40                   	rex
  50:	4b 81 44 2e 40 00 00 	add    QWORD PTR [r14+r13*1+0x40],0x1000000
  57:	00 01 
  59:	40                   	rex
  5a:	4b 81 44 2e 48 00 00 	add    QWORD PTR [r14+r13*1+0x48],0x1000000
  61:	00 01 
  63:	40                   	rex
  64:	4b 81 44 2e 50 00 00 	add    QWORD PTR [r14+r13*1+0x50],0x1000000
  6b:	00 01 
  6d:	40                   	rex
  6e:	4b 81 44 2e 58 00 00 	add    QWORD PTR [r14+r13*1+0x58],0x1000000
  75:	00 01 
  77:	40                   	rex
  78:	4b 81 44 2e 60 00 00 	add    QWORD PTR [r14+r13*1+0x60],0x1000000
  7f:	00 01 
  81:	40                   	rex
  82:	4b 81 44 2e 68 00 00 	add    QWORD PTR [r14+r13*1+0x68],0x1000000
  89:	00 01 
  8b:	40                   	rex
  8c:	4b 81 44 2e 70 00 00 	add    QWORD PTR [r14+r13*1+0x70],0x1000000
  93:	00 01 
  95:	40                   	rex
  96:	4b 81 44 2e 78 00 00 	add    QWORD PTR [r14+r13*1+0x78],0x1000000
  9d:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.03
- Reference cycles: 16.87
- UOPS_EXECUTED.THREAD: 65.01
- RETIRE_SLOTS: 49.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.6
- UOPS_PORT_1: 4.9
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 16.01
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 5.25
- UOPS_PORT_6: 2.25
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
   f:	00 01 
  11:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  18:	00 01 
  1a:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  21:	00 01 
  23:	4b 81 44 2e 20 00 00 	add    QWORD PTR [r14+r13*1+0x20],0x1000000
  2a:	00 01 
  2c:	4b 81 44 2e 28 00 00 	add    QWORD PTR [r14+r13*1+0x28],0x1000000
  33:	00 01 
  35:	4b 81 44 2e 30 00 00 	add    QWORD PTR [r14+r13*1+0x30],0x1000000
  3c:	00 01 
  3e:	4b 81 44 2e 38 00 00 	add    QWORD PTR [r14+r13*1+0x38],0x1000000
  45:	00 01 
  47:	4b 81 44 2e 40 00 00 	add    QWORD PTR [r14+r13*1+0x40],0x1000000
  4e:	00 01 
  50:	4b 81 44 2e 48 00 00 	add    QWORD PTR [r14+r13*1+0x48],0x1000000
  57:	00 01 
  59:	4b 81 44 2e 50 00 00 	add    QWORD PTR [r14+r13*1+0x50],0x1000000
  60:	00 01 
  62:	4b 81 44 2e 58 00 00 	add    QWORD PTR [r14+r13*1+0x58],0x1000000
  69:	00 01 
  6b:	4b 81 44 2e 60 00 00 	add    QWORD PTR [r14+r13*1+0x60],0x1000000
  72:	00 01 
  74:	4b 81 44 2e 68 00 00 	add    QWORD PTR [r14+r13*1+0x68],0x1000000
  7b:	00 01 
  7d:	4b 81 44 2e 70 00 00 	add    QWORD PTR [r14+r13*1+0x70],0x1000000
  84:	00 01 
  86:	4b 81 44 2e 78 00 00 	add    QWORD PTR [r14+r13*1+0x78],0x1000000
  8d:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.11
- Reference cycles: 16.96
- UOPS_EXECUTED.THREAD: 64.11
- RETIRE_SLOTS: 48.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.22
- UOPS_PORT_1: 5.58
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 16.01
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 5.84
- UOPS_PORT_6: 5.59
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	4b 81 04 2e 00 00 00 	add    QWORD PTR [r14+r13*1],0x1000000
   8:	01 
   9:	40                   	rex
   a:	4b 81 44 2e 08 00 00 	add    QWORD PTR [r14+r13*1+0x8],0x1000000
  11:	00 01 
  13:	40                   	rex
  14:	4b 81 44 2e 10 00 00 	add    QWORD PTR [r14+r13*1+0x10],0x1000000
  1b:	00 01 
  1d:	40                   	rex
  1e:	4b 81 44 2e 18 00 00 	add    QWORD PTR [r14+r13*1+0x18],0x1000000
  25:	00 01 
  27:	40                   	rex
  28:	4b 81 44 2e 20 00 00 	add    QWORD PTR [r14+r13*1+0x20],0x1000000
  2f:	00 01 
  31:	40                   	rex
  32:	4b 81 44 2e 28 00 00 	add    QWORD PTR [r14+r13*1+0x28],0x1000000
  39:	00 01 
  3b:	40                   	rex
  3c:	4b 81 44 2e 30 00 00 	add    QWORD PTR [r14+r13*1+0x30],0x1000000
  43:	00 01 
  45:	40                   	rex
  46:	4b 81 44 2e 38 00 00 	add    QWORD PTR [r14+r13*1+0x38],0x1000000
  4d:	00 01 
  4f:	40                   	rex
  50:	4b 81 44 2e 40 00 00 	add    QWORD PTR [r14+r13*1+0x40],0x1000000
  57:	00 01 
  59:	40                   	rex
  5a:	4b 81 44 2e 48 00 00 	add    QWORD PTR [r14+r13*1+0x48],0x1000000
  61:	00 01 
  63:	40                   	rex
  64:	4b 81 44 2e 50 00 00 	add    QWORD PTR [r14+r13*1+0x50],0x1000000
  6b:	00 01 
  6d:	40                   	rex
  6e:	4b 81 44 2e 58 00 00 	add    QWORD PTR [r14+r13*1+0x58],0x1000000
  75:	00 01 
  77:	40                   	rex
  78:	4b 81 44 2e 60 00 00 	add    QWORD PTR [r14+r13*1+0x60],0x1000000
  7f:	00 01 
  81:	40                   	rex
  82:	4b 81 44 2e 68 00 00 	add    QWORD PTR [r14+r13*1+0x68],0x1000000
  89:	00 01 
  8b:	40                   	rex
  8c:	4b 81 44 2e 70 00 00 	add    QWORD PTR [r14+r13*1+0x70],0x1000000
  93:	00 01 
  95:	40                   	rex
  96:	4b 81 44 2e 78 00 00 	add    QWORD PTR [r14+r13*1+0x78],0x1000000
  9d:	00 01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.11
- Reference cycles: 16.96
- UOPS_EXECUTED.THREAD: 64.11
- RETIRE_SLOTS: 48.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.22
- UOPS_PORT_1: 5.58
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 16.01
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 5.84
- UOPS_PORT_6: 5.59
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

ADD (M64, I32) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)