ADD (M8, I8)

With unroll_count=500 and no inner loop

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.02
- Reference cycles: 0.77
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.99
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.03
- UOPS_DISPATCHED.ALU: 1.02
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.03
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.98
- Reference cycles: 0.74
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 2.99
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 0.99
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	90                   	nop
   5:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 0.71
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 3.99
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.0
- Reference cycles: 0.71
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.01

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.0
- Reference cycles: 0.74
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 5 NOPs

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 1.02
- Reference cycles: 0.71
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With unroll_count=500, no inner loop, and 6 NOPs

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 1.01
- Reference cycles: 0.67
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 7.98
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With unroll_count=500, no inner loop, and 7 NOPs

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 2.0
- Reference cycles: 1.45
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 9.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.71
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.1
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.71
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.01
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.01
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	41 80 46 01 02       	add    BYTE PTR [r14+0x1],0x2
   9:	41 80 46 02 02       	add    BYTE PTR [r14+0x2],0x2
   e:	41 80 46 03 02       	add    BYTE PTR [r14+0x3],0x2

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.69
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 3.48
- UOPS_DISPATCHED.ALU: 4.02
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 4.02
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 4.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	41 80 46 01 02       	add    BYTE PTR [r14+0x1],0x2
   9:	41 80 46 02 02       	add    BYTE PTR [r14+0x2],0x2
   e:	41 80 46 03 02       	add    BYTE PTR [r14+0x3],0x2

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.03
- Reference cycles: 1.44
- UOPS_EXECUTED.THREAD: 16.52
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.02
- UOPS_DISPATCHED.INT_EU_ALL: 4.51
- UOPS_DISPATCHED.ALU: 4.01
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 4.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.5
- UOPS_DISPATCHED.STA: 4.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	41 80 46 01 02       	add    BYTE PTR [r14+0x1],0x2
   9:	41 80 46 02 02       	add    BYTE PTR [r14+0x2],0x2
   e:	41 80 46 03 02       	add    BYTE PTR [r14+0x3],0x2

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.64
- Reference cycles: 1.84
- UOPS_EXECUTED.THREAD: 16.06
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.07
- UOPS_MS: 0.02
- UOPS_DISPATCHED.INT_EU_ALL: 5.31
- UOPS_DISPATCHED.ALU: 5.27
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 4.42
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.05
- UOPS_DISPATCHED.STA: 4.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	41 80 46 01 02       	add    BYTE PTR [r14+0x1],0x2
   9:	41 80 46 02 02       	add    BYTE PTR [r14+0x2],0x2
   e:	41 80 46 03 02       	add    BYTE PTR [r14+0x3],0x2
  13:	41 80 46 04 02       	add    BYTE PTR [r14+0x4],0x2
  18:	41 80 46 05 02       	add    BYTE PTR [r14+0x5],0x2
  1d:	41 80 46 06 02       	add    BYTE PTR [r14+0x6],0x2
  22:	41 80 46 07 02       	add    BYTE PTR [r14+0x7],0x2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 7.37
- Reference cycles: 5.05
- UOPS_EXECUTED.THREAD: 32.2
- RETIRE_SLOTS: 16.04
- UOPS_MITE: 15.92
- UOPS_MS: 0.37
- UOPS_DISPATCHED.INT_EU_ALL: 10.03
- UOPS_DISPATCHED.ALU: 9.72
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 8.92
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 8.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.69

With loop_count=1000 and unroll_count=1

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	41 80 46 01 02       	add    BYTE PTR [r14+0x1],0x2
   9:	41 80 46 02 02       	add    BYTE PTR [r14+0x2],0x2
   e:	41 80 46 03 02       	add    BYTE PTR [r14+0x3],0x2
  13:	41 80 46 04 02       	add    BYTE PTR [r14+0x4],0x2
  18:	41 80 46 05 02       	add    BYTE PTR [r14+0x5],0x2
  1d:	41 80 46 06 02       	add    BYTE PTR [r14+0x6],0x2
  22:	41 80 46 07 02       	add    BYTE PTR [r14+0x7],0x2

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.04
- Reference cycles: 2.88
- UOPS_EXECUTED.THREAD: 33.03
- RETIRE_SLOTS: 17.01
- UOPS_MITE: 0.0
- UOPS_MS: 0.06
- UOPS_DISPATCHED.INT_EU_ALL: 9.02
- UOPS_DISPATCHED.ALU: 8.02
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 8.01
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 1.0
- UOPS_DISPATCHED.STA: 8.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	41 80 46 01 02       	add    BYTE PTR [r14+0x1],0x2
   9:	41 80 46 02 02       	add    BYTE PTR [r14+0x2],0x2
   e:	41 80 46 03 02       	add    BYTE PTR [r14+0x3],0x2
  13:	41 80 46 04 02       	add    BYTE PTR [r14+0x4],0x2
  18:	41 80 46 05 02       	add    BYTE PTR [r14+0x5],0x2
  1d:	41 80 46 06 02       	add    BYTE PTR [r14+0x6],0x2
  22:	41 80 46 07 02       	add    BYTE PTR [r14+0x7],0x2

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.77
- Reference cycles: 3.38
- UOPS_EXECUTED.THREAD: 32.12
- RETIRE_SLOTS: 16.11
- UOPS_MITE: 0.15
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 12.09
- UOPS_DISPATCHED.ALU: 11.93
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 8.4
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 8.02
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.06

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	41 80 46 01 02       	add    BYTE PTR [r14+0x1],0x2
   9:	41 80 46 02 02       	add    BYTE PTR [r14+0x2],0x2
   e:	41 80 46 03 02       	add    BYTE PTR [r14+0x3],0x2
  13:	41 80 46 04 02       	add    BYTE PTR [r14+0x4],0x2
  18:	41 80 46 05 02       	add    BYTE PTR [r14+0x5],0x2
  1d:	41 80 46 06 02       	add    BYTE PTR [r14+0x6],0x2
  22:	41 80 46 07 02       	add    BYTE PTR [r14+0x7],0x2
  27:	41 80 46 08 02       	add    BYTE PTR [r14+0x8],0x2
  2c:	41 80 46 09 02       	add    BYTE PTR [r14+0x9],0x2
  31:	41 80 46 0a 02       	add    BYTE PTR [r14+0xa],0x2
  36:	41 80 46 0b 02       	add    BYTE PTR [r14+0xb],0x2
  3b:	41 80 46 0c 02       	add    BYTE PTR [r14+0xc],0x2
  40:	41 80 46 0d 02       	add    BYTE PTR [r14+0xd],0x2
  45:	41 80 46 0e 02       	add    BYTE PTR [r14+0xe],0x2
  4a:	41 80 46 0f 02       	add    BYTE PTR [r14+0xf],0x2

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 13.84
- Reference cycles: 9.43
- UOPS_EXECUTED.THREAD: 67.43
- RETIRE_SLOTS: 32.16
- UOPS_MITE: 20.53
- UOPS_MS: 0.4
- UOPS_DISPATCHED.INT_EU_ALL: 22.47
- UOPS_DISPATCHED.ALU: 20.99
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 18.66
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 17.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 12.61

With loop_count=1000 and unroll_count=1

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	41 80 46 01 02       	add    BYTE PTR [r14+0x1],0x2
   9:	41 80 46 02 02       	add    BYTE PTR [r14+0x2],0x2
   e:	41 80 46 03 02       	add    BYTE PTR [r14+0x3],0x2
  13:	41 80 46 04 02       	add    BYTE PTR [r14+0x4],0x2
  18:	41 80 46 05 02       	add    BYTE PTR [r14+0x5],0x2
  1d:	41 80 46 06 02       	add    BYTE PTR [r14+0x6],0x2
  22:	41 80 46 07 02       	add    BYTE PTR [r14+0x7],0x2
  27:	41 80 46 08 02       	add    BYTE PTR [r14+0x8],0x2
  2c:	41 80 46 09 02       	add    BYTE PTR [r14+0x9],0x2
  31:	41 80 46 0a 02       	add    BYTE PTR [r14+0xa],0x2
  36:	41 80 46 0b 02       	add    BYTE PTR [r14+0xb],0x2
  3b:	41 80 46 0c 02       	add    BYTE PTR [r14+0xc],0x2
  40:	41 80 46 0d 02       	add    BYTE PTR [r14+0xd],0x2
  45:	41 80 46 0e 02       	add    BYTE PTR [r14+0xe],0x2
  4a:	41 80 46 0f 02       	add    BYTE PTR [r14+0xf],0x2

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.02
- Reference cycles: 5.64
- UOPS_EXECUTED.THREAD: 65.02
- RETIRE_SLOTS: 33.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 17.03
- UOPS_DISPATCHED.ALU: 16.03
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 16.01
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 1.0
- UOPS_DISPATCHED.STA: 16.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	41 80 46 01 02       	add    BYTE PTR [r14+0x1],0x2
   9:	41 80 46 02 02       	add    BYTE PTR [r14+0x2],0x2
   e:	41 80 46 03 02       	add    BYTE PTR [r14+0x3],0x2
  13:	41 80 46 04 02       	add    BYTE PTR [r14+0x4],0x2
  18:	41 80 46 05 02       	add    BYTE PTR [r14+0x5],0x2
  1d:	41 80 46 06 02       	add    BYTE PTR [r14+0x6],0x2
  22:	41 80 46 07 02       	add    BYTE PTR [r14+0x7],0x2
  27:	41 80 46 08 02       	add    BYTE PTR [r14+0x8],0x2
  2c:	41 80 46 09 02       	add    BYTE PTR [r14+0x9],0x2
  31:	41 80 46 0a 02       	add    BYTE PTR [r14+0xa],0x2
  36:	41 80 46 0b 02       	add    BYTE PTR [r14+0xb],0x2
  3b:	41 80 46 0c 02       	add    BYTE PTR [r14+0xc],0x2
  40:	41 80 46 0d 02       	add    BYTE PTR [r14+0xd],0x2
  45:	41 80 46 0e 02       	add    BYTE PTR [r14+0xe],0x2
  4a:	41 80 46 0f 02       	add    BYTE PTR [r14+0xf],0x2

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.76
- Reference cycles: 6.16
- UOPS_EXECUTED.THREAD: 64.58
- RETIRE_SLOTS: 32.11
- UOPS_MITE: 0.31
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 23.72
- UOPS_DISPATCHED.ALU: 23.56
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 16.15
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 16.1
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.13

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 6.58
- Reference cycles: 4.61
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.01
- UOPS_MS: 0.07
- UOPS_DISPATCHED.INT_EU_ALL: 12.17
- UOPS_DISPATCHED.ALU: 12.28
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 9.88
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.96

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.16
- Reference cycles: 4.38
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.01
- UOPS_MS: 0.11
- UOPS_DISPATCHED.INT_EU_ALL: 13.5
- UOPS_DISPATCHED.ALU: 13.64
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.94
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.98

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	90                   	nop
   6:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.69
- Reference cycles: 4.71
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.11
- UOPS_DISPATCHED.INT_EU_ALL: 12.62
- UOPS_DISPATCHED.ALU: 12.12
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 9.7
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.98

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.52
- Reference cycles: 4.58
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.07
- UOPS_DISPATCHED.INT_EU_ALL: 12.07
- UOPS_DISPATCHED.ALU: 12.27
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 9.81
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.97

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 6.5
- Reference cycles: 4.58
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.08
- UOPS_DISPATCHED.INT_EU_ALL: 11.97
- UOPS_DISPATCHED.ALU: 12.17
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 9.95
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 5 NOPs

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.29
- Reference cycles: 5.12
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.07
- UOPS_DISPATCHED.INT_EU_ALL: 11.92
- UOPS_DISPATCHED.ALU: 11.01
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 9.92
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 6 NOPs

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 6.65
- Reference cycles: 4.68
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 9.0
- UOPS_MS: 0.11
- UOPS_DISPATCHED.INT_EU_ALL: 11.13
- UOPS_DISPATCHED.ALU: 11.18
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 9.4
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.97

With loop_count=1000 and unroll_count=10

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.15
- Reference cycles: 4.34
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.01
- UOPS_DISPATCHED.INT_EU_ALL: 12.59
- UOPS_DISPATCHED.ALU: 12.5
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.59
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.22
- Reference cycles: 4.38
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 12.55
- UOPS_DISPATCHED.ALU: 12.46
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.22
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.43
- Reference cycles: 4.53
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 3.01
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 12.81
- UOPS_DISPATCHED.ALU: 12.83
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.17
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.01
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.31
- Reference cycles: 4.45
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 12.52
- UOPS_DISPATCHED.ALU: 12.56
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.06
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.01
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
   b:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  11:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 7.64
- Reference cycles: 5.39
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.19
- UOPS_DISPATCHED.INT_EU_ALL: 18.02
- UOPS_DISPATCHED.ALU: 18.47
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.67
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 4.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.89

With loop_count=1000 and unroll_count=2

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
   b:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  11:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 7.47
- Reference cycles: 5.26
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.22
- UOPS_MS: 0.02
- UOPS_DISPATCHED.INT_EU_ALL: 18.64
- UOPS_DISPATCHED.ALU: 18.17
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.54
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.5
- UOPS_DISPATCHED.STA: 4.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.06

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 7.45
- Reference cycles: 5.25
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.02
- UOPS_MS: 0.02
- UOPS_DISPATCHED.INT_EU_ALL: 18.73
- UOPS_DISPATCHED.ALU: 18.05
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.49
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.5
- UOPS_DISPATCHED.STA: 4.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
   b:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  11:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 7.43
- Reference cycles: 5.23
- UOPS_EXECUTED.THREAD: 16.07
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.13
- UOPS_MS: 0.02
- UOPS_DISPATCHED.INT_EU_ALL: 18.51
- UOPS_DISPATCHED.ALU: 18.53
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.54
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.05
- UOPS_DISPATCHED.STA: 4.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 7.42
- Reference cycles: 5.24
- UOPS_EXECUTED.THREAD: 16.06
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.12
- UOPS_MS: 0.03
- UOPS_DISPATCHED.INT_EU_ALL: 18.33
- UOPS_DISPATCHED.ALU: 18.28
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.56
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.05
- UOPS_DISPATCHED.STA: 4.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
   b:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  11:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2
  17:	43 80 44 2e 04 02    	add    BYTE PTR [r14+r13*1+0x4],0x2
  1d:	43 80 44 2e 05 02    	add    BYTE PTR [r14+r13*1+0x5],0x2
  23:	43 80 44 2e 06 02    	add    BYTE PTR [r14+r13*1+0x6],0x2
  29:	43 80 44 2e 07 02    	add    BYTE PTR [r14+r13*1+0x7],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.26
- Reference cycles: 5.72
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 24.01
- UOPS_MITE: 24.01
- UOPS_MS: 0.37
- UOPS_DISPATCHED.INT_EU_ALL: 23.0
- UOPS_DISPATCHED.ALU: 22.89
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 12.02
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 8.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.77

With loop_count=1000 and unroll_count=1

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
   b:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  11:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2
  17:	43 80 44 2e 04 02    	add    BYTE PTR [r14+r13*1+0x4],0x2
  1d:	43 80 44 2e 05 02    	add    BYTE PTR [r14+r13*1+0x5],0x2
  23:	43 80 44 2e 06 02    	add    BYTE PTR [r14+r13*1+0x6],0x2
  29:	43 80 44 2e 07 02    	add    BYTE PTR [r14+r13*1+0x7],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 7.89
- Reference cycles: 5.57
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 25.01
- UOPS_MITE: 0.52
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 23.78
- UOPS_DISPATCHED.ALU: 22.73
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 11.83
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 1.0
- UOPS_DISPATCHED.STA: 8.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	43 80 44 2e 04 02    	add    BYTE PTR [r14+r13*1+0x4],0x2
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	43 80 44 2e 05 02    	add    BYTE PTR [r14+r13*1+0x5],0x2
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	43 80 44 2e 06 02    	add    BYTE PTR [r14+r13*1+0x6],0x2
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	43 80 44 2e 07 02    	add    BYTE PTR [r14+r13*1+0x7],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 7.92
- Reference cycles: 5.61
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 23.8
- UOPS_DISPATCHED.ALU: 22.82
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 11.84
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 1.0
- UOPS_DISPATCHED.STA: 8.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
   b:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  11:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2
  17:	43 80 44 2e 04 02    	add    BYTE PTR [r14+r13*1+0x4],0x2
  1d:	43 80 44 2e 05 02    	add    BYTE PTR [r14+r13*1+0x5],0x2
  23:	43 80 44 2e 06 02    	add    BYTE PTR [r14+r13*1+0x6],0x2
  29:	43 80 44 2e 07 02    	add    BYTE PTR [r14+r13*1+0x7],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.02
- Reference cycles: 5.67
- UOPS_EXECUTED.THREAD: 32.15
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.25
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 22.96
- UOPS_DISPATCHED.ALU: 22.89
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 11.85
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 8.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	43 80 44 2e 04 02    	add    BYTE PTR [r14+r13*1+0x4],0x2
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	43 80 44 2e 05 02    	add    BYTE PTR [r14+r13*1+0x5],0x2
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	43 80 44 2e 06 02    	add    BYTE PTR [r14+r13*1+0x6],0x2
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	43 80 44 2e 07 02    	add    BYTE PTR [r14+r13*1+0x7],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 5.66
- UOPS_EXECUTED.THREAD: 32.16
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.24
- UOPS_MS: 0.06
- UOPS_DISPATCHED.INT_EU_ALL: 22.91
- UOPS_DISPATCHED.ALU: 22.77
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 11.9
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 8.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
   b:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  11:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2
  17:	43 80 44 2e 04 02    	add    BYTE PTR [r14+r13*1+0x4],0x2
  1d:	43 80 44 2e 05 02    	add    BYTE PTR [r14+r13*1+0x5],0x2
  23:	43 80 44 2e 06 02    	add    BYTE PTR [r14+r13*1+0x6],0x2
  29:	43 80 44 2e 07 02    	add    BYTE PTR [r14+r13*1+0x7],0x2
  2f:	43 80 44 2e 08 02    	add    BYTE PTR [r14+r13*1+0x8],0x2
  35:	43 80 44 2e 09 02    	add    BYTE PTR [r14+r13*1+0x9],0x2
  3b:	43 80 44 2e 0a 02    	add    BYTE PTR [r14+r13*1+0xa],0x2
  41:	43 80 44 2e 0b 02    	add    BYTE PTR [r14+r13*1+0xb],0x2
  47:	43 80 44 2e 0c 02    	add    BYTE PTR [r14+r13*1+0xc],0x2
  4d:	43 80 44 2e 0d 02    	add    BYTE PTR [r14+r13*1+0xd],0x2
  53:	43 80 44 2e 0e 02    	add    BYTE PTR [r14+r13*1+0xe],0x2
  59:	43 80 44 2e 0f 02    	add    BYTE PTR [r14+r13*1+0xf],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 20.3
- Reference cycles: 14.31
- UOPS_EXECUTED.THREAD: 69.9
- RETIRE_SLOTS: 48.52
- UOPS_MITE: 47.55
- UOPS_MS: 0.49
- UOPS_DISPATCHED.INT_EU_ALL: 33.41
- UOPS_DISPATCHED.ALU: 34.22
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 23.72
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 18.26
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.81

With loop_count=1000 and unroll_count=1

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
   b:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  11:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2
  17:	43 80 44 2e 04 02    	add    BYTE PTR [r14+r13*1+0x4],0x2
  1d:	43 80 44 2e 05 02    	add    BYTE PTR [r14+r13*1+0x5],0x2
  23:	43 80 44 2e 06 02    	add    BYTE PTR [r14+r13*1+0x6],0x2
  29:	43 80 44 2e 07 02    	add    BYTE PTR [r14+r13*1+0x7],0x2
  2f:	43 80 44 2e 08 02    	add    BYTE PTR [r14+r13*1+0x8],0x2
  35:	43 80 44 2e 09 02    	add    BYTE PTR [r14+r13*1+0x9],0x2
  3b:	43 80 44 2e 0a 02    	add    BYTE PTR [r14+r13*1+0xa],0x2
  41:	43 80 44 2e 0b 02    	add    BYTE PTR [r14+r13*1+0xb],0x2
  47:	43 80 44 2e 0c 02    	add    BYTE PTR [r14+r13*1+0xc],0x2
  4d:	43 80 44 2e 0d 02    	add    BYTE PTR [r14+r13*1+0xd],0x2
  53:	43 80 44 2e 0e 02    	add    BYTE PTR [r14+r13*1+0xe],0x2
  59:	43 80 44 2e 0f 02    	add    BYTE PTR [r14+r13*1+0xf],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 11.16
- Reference cycles: 7.88
- UOPS_EXECUTED.THREAD: 65.02
- RETIRE_SLOTS: 49.01
- UOPS_MITE: 0.27
- UOPS_MS: 0.06
- UOPS_DISPATCHED.INT_EU_ALL: 28.25
- UOPS_DISPATCHED.ALU: 27.25
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 16.25
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 1.0
- UOPS_DISPATCHED.STA: 16.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	43 80 44 2e 04 02    	add    BYTE PTR [r14+r13*1+0x4],0x2
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	43 80 44 2e 05 02    	add    BYTE PTR [r14+r13*1+0x5],0x2
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	43 80 44 2e 06 02    	add    BYTE PTR [r14+r13*1+0x6],0x2
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	43 80 44 2e 07 02    	add    BYTE PTR [r14+r13*1+0x7],0x2
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	43 80 44 2e 08 02    	add    BYTE PTR [r14+r13*1+0x8],0x2
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	43 80 44 2e 09 02    	add    BYTE PTR [r14+r13*1+0x9],0x2
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	43 80 44 2e 0a 02    	add    BYTE PTR [r14+r13*1+0xa],0x2
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	43 80 44 2e 0b 02    	add    BYTE PTR [r14+r13*1+0xb],0x2
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	43 80 44 2e 0c 02    	add    BYTE PTR [r14+r13*1+0xc],0x2
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	43 80 44 2e 0d 02    	add    BYTE PTR [r14+r13*1+0xd],0x2
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	43 80 44 2e 0e 02    	add    BYTE PTR [r14+r13*1+0xe],0x2
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	43 80 44 2e 0f 02    	add    BYTE PTR [r14+r13*1+0xf],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 9.31
- Reference cycles: 6.57
- UOPS_EXECUTED.THREAD: 65.02
- RETIRE_SLOTS: 49.01
- UOPS_MITE: 0.04
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 28.32
- UOPS_DISPATCHED.ALU: 27.31
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 16.23
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 1.0
- UOPS_DISPATCHED.STA: 16.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
   b:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  11:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2
  17:	43 80 44 2e 04 02    	add    BYTE PTR [r14+r13*1+0x4],0x2
  1d:	43 80 44 2e 05 02    	add    BYTE PTR [r14+r13*1+0x5],0x2
  23:	43 80 44 2e 06 02    	add    BYTE PTR [r14+r13*1+0x6],0x2
  29:	43 80 44 2e 07 02    	add    BYTE PTR [r14+r13*1+0x7],0x2
  2f:	43 80 44 2e 08 02    	add    BYTE PTR [r14+r13*1+0x8],0x2
  35:	43 80 44 2e 09 02    	add    BYTE PTR [r14+r13*1+0x9],0x2
  3b:	43 80 44 2e 0a 02    	add    BYTE PTR [r14+r13*1+0xa],0x2
  41:	43 80 44 2e 0b 02    	add    BYTE PTR [r14+r13*1+0xb],0x2
  47:	43 80 44 2e 0c 02    	add    BYTE PTR [r14+r13*1+0xc],0x2
  4d:	43 80 44 2e 0d 02    	add    BYTE PTR [r14+r13*1+0xd],0x2
  53:	43 80 44 2e 0e 02    	add    BYTE PTR [r14+r13*1+0xe],0x2
  59:	43 80 44 2e 0f 02    	add    BYTE PTR [r14+r13*1+0xf],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 9.62
- Reference cycles: 6.77
- UOPS_EXECUTED.THREAD: 64.23
- RETIRE_SLOTS: 48.11
- UOPS_MITE: 0.47
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 27.46
- UOPS_DISPATCHED.ALU: 27.35
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 16.28
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 16.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.14

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 80 44 2e 01 02    	add    BYTE PTR [r14+r13*1+0x1],0x2
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 80 44 2e 02 02    	add    BYTE PTR [r14+r13*1+0x2],0x2
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 80 44 2e 03 02    	add    BYTE PTR [r14+r13*1+0x3],0x2
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	43 80 44 2e 04 02    	add    BYTE PTR [r14+r13*1+0x4],0x2
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	43 80 44 2e 05 02    	add    BYTE PTR [r14+r13*1+0x5],0x2
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	43 80 44 2e 06 02    	add    BYTE PTR [r14+r13*1+0x6],0x2
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	43 80 44 2e 07 02    	add    BYTE PTR [r14+r13*1+0x7],0x2
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	43 80 44 2e 08 02    	add    BYTE PTR [r14+r13*1+0x8],0x2
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	43 80 44 2e 09 02    	add    BYTE PTR [r14+r13*1+0x9],0x2
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	43 80 44 2e 0a 02    	add    BYTE PTR [r14+r13*1+0xa],0x2
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	43 80 44 2e 0b 02    	add    BYTE PTR [r14+r13*1+0xb],0x2
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	43 80 44 2e 0c 02    	add    BYTE PTR [r14+r13*1+0xc],0x2
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	43 80 44 2e 0d 02    	add    BYTE PTR [r14+r13*1+0xd],0x2
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	43 80 44 2e 0e 02    	add    BYTE PTR [r14+r13*1+0xe],0x2
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	43 80 44 2e 0f 02    	add    BYTE PTR [r14+r13*1+0xf],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 9.61
- Reference cycles: 6.78
- UOPS_EXECUTED.THREAD: 64.23
- RETIRE_SLOTS: 48.11
- UOPS_MITE: 0.47
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 27.45
- UOPS_DISPATCHED.ALU: 27.37
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 16.27
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 16.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.14

ADD (M8, I8) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With unroll_count=500, no inner loop, and 5 NOPs

With unroll_count=500, no inner loop, and 6 NOPs

With unroll_count=500, no inner loop, and 7 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With unroll_count=500, no inner loop, and 5 NOPs

With unroll_count=500, no inner loop, and 6 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)