ADD (M32, I8)

With unroll_count=500 and no inner loop

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.02
- Reference cycles: 0.74
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.99
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.09
- UOPS_DISPATCHED.ALU: 1.06
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.03
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.98
- Reference cycles: 0.74
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 2.99
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 0.99
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	90                   	nop
   5:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 0.67
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 3.99
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.0
- Reference cycles: 0.74
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.01

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.0
- Reference cycles: 0.74
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 5 NOPs

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 1.02
- Reference cycles: 0.77
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With unroll_count=500, no inner loop, and 6 NOPs

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 1.01
- Reference cycles: 0.71
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 7.98
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.02

With unroll_count=500, no inner loop, and 7 NOPs

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 2.0
- Reference cycles: 1.38
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 9.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.71
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.1
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.7
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 1.01
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.01
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	41 83 46 04 02       	add    DWORD PTR [r14+0x4],0x2
   9:	41 83 46 08 02       	add    DWORD PTR [r14+0x8],0x2
   e:	41 83 46 0c 02       	add    DWORD PTR [r14+0xc],0x2

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.78
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 4.08
- UOPS_DISPATCHED.ALU: 4.02
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 4.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 4.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	41 83 46 04 02       	add    DWORD PTR [r14+0x4],0x2
   9:	41 83 46 08 02       	add    DWORD PTR [r14+0x8],0x2
   e:	41 83 46 0c 02       	add    DWORD PTR [r14+0xc],0x2

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.02
- Reference cycles: 1.42
- UOPS_EXECUTED.THREAD: 16.51
- RETIRE_SLOTS: 8.51
- UOPS_MITE: 0.0
- UOPS_MS: 0.02
- UOPS_DISPATCHED.INT_EU_ALL: 4.5
- UOPS_DISPATCHED.ALU: 4.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 4.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.5
- UOPS_DISPATCHED.STA: 4.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	41 83 46 04 02       	add    DWORD PTR [r14+0x4],0x2
   9:	41 83 46 08 02       	add    DWORD PTR [r14+0x8],0x2
   e:	41 83 46 0c 02       	add    DWORD PTR [r14+0xc],0x2

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 3.18
- Reference cycles: 2.26
- UOPS_EXECUTED.THREAD: 16.09
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.02
- UOPS_DISPATCHED.INT_EU_ALL: 6.93
- UOPS_DISPATCHED.ALU: 6.92
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 4.89
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.05
- UOPS_DISPATCHED.STA: 4.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	41 83 46 04 02       	add    DWORD PTR [r14+0x4],0x2
   9:	41 83 46 08 02       	add    DWORD PTR [r14+0x8],0x2
   e:	41 83 46 0c 02       	add    DWORD PTR [r14+0xc],0x2
  13:	41 83 46 10 02       	add    DWORD PTR [r14+0x10],0x2
  18:	41 83 46 14 02       	add    DWORD PTR [r14+0x14],0x2
  1d:	41 83 46 18 02       	add    DWORD PTR [r14+0x18],0x2
  22:	41 83 46 1c 02       	add    DWORD PTR [r14+0x1c],0x2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 7.36
- Reference cycles: 5.72
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 16.04
- UOPS_MITE: 15.81
- UOPS_MS: 0.57
- UOPS_DISPATCHED.INT_EU_ALL: 9.16
- UOPS_DISPATCHED.ALU: 9.15
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 8.71
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 8.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.67

With loop_count=1000 and unroll_count=1

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	41 83 46 04 02       	add    DWORD PTR [r14+0x4],0x2
   9:	41 83 46 08 02       	add    DWORD PTR [r14+0x8],0x2
   e:	41 83 46 0c 02       	add    DWORD PTR [r14+0xc],0x2
  13:	41 83 46 10 02       	add    DWORD PTR [r14+0x10],0x2
  18:	41 83 46 14 02       	add    DWORD PTR [r14+0x14],0x2
  1d:	41 83 46 18 02       	add    DWORD PTR [r14+0x18],0x2
  22:	41 83 46 1c 02       	add    DWORD PTR [r14+0x1c],0x2

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.04
- Reference cycles: 2.86
- UOPS_EXECUTED.THREAD: 33.03
- RETIRE_SLOTS: 17.01
- UOPS_MITE: 0.0
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 9.01
- UOPS_DISPATCHED.ALU: 8.01
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 8.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 1.0
- UOPS_DISPATCHED.STA: 8.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	41 83 46 04 02       	add    DWORD PTR [r14+0x4],0x2
   9:	41 83 46 08 02       	add    DWORD PTR [r14+0x8],0x2
   e:	41 83 46 0c 02       	add    DWORD PTR [r14+0xc],0x2
  13:	41 83 46 10 02       	add    DWORD PTR [r14+0x10],0x2
  18:	41 83 46 14 02       	add    DWORD PTR [r14+0x14],0x2
  1d:	41 83 46 18 02       	add    DWORD PTR [r14+0x18],0x2
  22:	41 83 46 1c 02       	add    DWORD PTR [r14+0x1c],0x2

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.47
- Reference cycles: 3.16
- UOPS_EXECUTED.THREAD: 32.12
- RETIRE_SLOTS: 16.11
- UOPS_MITE: 0.15
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 11.61
- UOPS_DISPATCHED.ALU: 11.24
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 8.18
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 8.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.06

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	41 83 46 04 02       	add    DWORD PTR [r14+0x4],0x2
   9:	41 83 46 08 02       	add    DWORD PTR [r14+0x8],0x2
   e:	41 83 46 0c 02       	add    DWORD PTR [r14+0xc],0x2
  13:	41 83 46 10 02       	add    DWORD PTR [r14+0x10],0x2
  18:	41 83 46 14 02       	add    DWORD PTR [r14+0x14],0x2
  1d:	41 83 46 18 02       	add    DWORD PTR [r14+0x18],0x2
  22:	41 83 46 1c 02       	add    DWORD PTR [r14+0x1c],0x2
  27:	41 83 46 20 02       	add    DWORD PTR [r14+0x20],0x2
  2c:	41 83 46 24 02       	add    DWORD PTR [r14+0x24],0x2
  31:	41 83 46 28 02       	add    DWORD PTR [r14+0x28],0x2
  36:	41 83 46 2c 02       	add    DWORD PTR [r14+0x2c],0x2
  3b:	41 83 46 30 02       	add    DWORD PTR [r14+0x30],0x2
  40:	41 83 46 34 02       	add    DWORD PTR [r14+0x34],0x2
  45:	41 83 46 38 02       	add    DWORD PTR [r14+0x38],0x2
  4a:	41 83 46 3c 02       	add    DWORD PTR [r14+0x3c],0x2

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 15.35
- Reference cycles: 10.94
- UOPS_EXECUTED.THREAD: 64.0
- RETIRE_SLOTS: 32.04
- UOPS_MITE: 31.92
- UOPS_MS: 0.37
- UOPS_DISPATCHED.INT_EU_ALL: 16.55
- UOPS_DISPATCHED.ALU: 16.31
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 16.01
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 16.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 15.67

With loop_count=1000 and unroll_count=1

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	41 83 46 04 02       	add    DWORD PTR [r14+0x4],0x2
   9:	41 83 46 08 02       	add    DWORD PTR [r14+0x8],0x2
   e:	41 83 46 0c 02       	add    DWORD PTR [r14+0xc],0x2
  13:	41 83 46 10 02       	add    DWORD PTR [r14+0x10],0x2
  18:	41 83 46 14 02       	add    DWORD PTR [r14+0x14],0x2
  1d:	41 83 46 18 02       	add    DWORD PTR [r14+0x18],0x2
  22:	41 83 46 1c 02       	add    DWORD PTR [r14+0x1c],0x2
  27:	41 83 46 20 02       	add    DWORD PTR [r14+0x20],0x2
  2c:	41 83 46 24 02       	add    DWORD PTR [r14+0x24],0x2
  31:	41 83 46 28 02       	add    DWORD PTR [r14+0x28],0x2
  36:	41 83 46 2c 02       	add    DWORD PTR [r14+0x2c],0x2
  3b:	41 83 46 30 02       	add    DWORD PTR [r14+0x30],0x2
  40:	41 83 46 34 02       	add    DWORD PTR [r14+0x34],0x2
  45:	41 83 46 38 02       	add    DWORD PTR [r14+0x38],0x2
  4a:	41 83 46 3c 02       	add    DWORD PTR [r14+0x3c],0x2

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.01
- Reference cycles: 5.64
- UOPS_EXECUTED.THREAD: 65.02
- RETIRE_SLOTS: 33.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 17.01
- UOPS_DISPATCHED.ALU: 16.01
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 16.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 1.0
- UOPS_DISPATCHED.STA: 16.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	41 83 06 02          	add    DWORD PTR [r14],0x2
   4:	41 83 46 04 02       	add    DWORD PTR [r14+0x4],0x2
   9:	41 83 46 08 02       	add    DWORD PTR [r14+0x8],0x2
   e:	41 83 46 0c 02       	add    DWORD PTR [r14+0xc],0x2
  13:	41 83 46 10 02       	add    DWORD PTR [r14+0x10],0x2
  18:	41 83 46 14 02       	add    DWORD PTR [r14+0x14],0x2
  1d:	41 83 46 18 02       	add    DWORD PTR [r14+0x18],0x2
  22:	41 83 46 1c 02       	add    DWORD PTR [r14+0x1c],0x2
  27:	41 83 46 20 02       	add    DWORD PTR [r14+0x20],0x2
  2c:	41 83 46 24 02       	add    DWORD PTR [r14+0x24],0x2
  31:	41 83 46 28 02       	add    DWORD PTR [r14+0x28],0x2
  36:	41 83 46 2c 02       	add    DWORD PTR [r14+0x2c],0x2
  3b:	41 83 46 30 02       	add    DWORD PTR [r14+0x30],0x2
  40:	41 83 46 34 02       	add    DWORD PTR [r14+0x34],0x2
  45:	41 83 46 38 02       	add    DWORD PTR [r14+0x38],0x2
  4a:	41 83 46 3c 02       	add    DWORD PTR [r14+0x3c],0x2

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.77
- Reference cycles: 6.21
- UOPS_EXECUTED.THREAD: 64.12
- RETIRE_SLOTS: 32.11
- UOPS_MITE: 0.31
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 23.56
- UOPS_DISPATCHED.ALU: 23.47
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 16.09
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 16.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.13

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 6.52
- Reference cycles: 4.51
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.01
- UOPS_MS: 0.07
- UOPS_DISPATCHED.INT_EU_ALL: 12.73
- UOPS_DISPATCHED.ALU: 12.72
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 9.87
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.96

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.48
- Reference cycles: 4.58
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.01
- UOPS_MS: 0.07
- UOPS_DISPATCHED.INT_EU_ALL: 13.2
- UOPS_DISPATCHED.ALU: 13.35
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 11.27
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.97

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	90                   	nop
   6:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.68
- Reference cycles: 4.71
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.07
- UOPS_DISPATCHED.INT_EU_ALL: 11.85
- UOPS_DISPATCHED.ALU: 11.97
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 9.99
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.98

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.49
- Reference cycles: 4.58
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.11
- UOPS_DISPATCHED.INT_EU_ALL: 12.36
- UOPS_DISPATCHED.ALU: 11.98
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 9.98
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.97

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 6.5
- Reference cycles: 4.58
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.11
- UOPS_DISPATCHED.INT_EU_ALL: 12.16
- UOPS_DISPATCHED.ALU: 12.24
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 9.92
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 5 NOPs

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.21
- Reference cycles: 5.02
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 8.01
- UOPS_MITE: 8.0
- UOPS_MS: 0.07
- UOPS_DISPATCHED.INT_EU_ALL: 12.72
- UOPS_DISPATCHED.ALU: 12.72
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 11.44
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 6 NOPs

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 6.5
- Reference cycles: 4.58
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 9.0
- UOPS_MS: 0.07
- UOPS_DISPATCHED.INT_EU_ALL: 11.2
- UOPS_DISPATCHED.ALU: 11.13
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 9.22
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.97

With loop_count=1000 and unroll_count=10

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.25
- Reference cycles: 4.41
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 12.55
- UOPS_DISPATCHED.ALU: 12.45
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.57
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.3
- Reference cycles: 4.44
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 12.61
- UOPS_DISPATCHED.ALU: 12.47
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.24
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.45
- Reference cycles: 4.55
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 3.01
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 12.81
- UOPS_DISPATCHED.ALU: 12.83
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.16
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.01
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.42
- Reference cycles: 4.53
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 12.72
- UOPS_DISPATCHED.ALU: 12.74
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.1
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.01
- UOPS_DISPATCHED.STA: 1.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
   b:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  11:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 7.46
- Reference cycles: 5.22
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.04
- UOPS_MS: 0.19
- UOPS_DISPATCHED.INT_EU_ALL: 17.65
- UOPS_DISPATCHED.ALU: 17.54
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.55
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 4.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.94

With loop_count=1000 and unroll_count=2

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
   b:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  11:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 7.47
- Reference cycles: 5.26
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.27
- UOPS_MS: 0.02
- UOPS_DISPATCHED.INT_EU_ALL: 17.11
- UOPS_DISPATCHED.ALU: 17.15
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.24
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.5
- UOPS_DISPATCHED.STA: 4.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 7.44
- Reference cycles: 5.25
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.02
- UOPS_MS: 0.02
- UOPS_DISPATCHED.INT_EU_ALL: 17.96
- UOPS_DISPATCHED.ALU: 17.17
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.39
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.5
- UOPS_DISPATCHED.STA: 4.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
   b:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  11:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 7.44
- Reference cycles: 5.24
- UOPS_EXECUTED.THREAD: 16.06
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.13
- UOPS_MS: 0.02
- UOPS_DISPATCHED.INT_EU_ALL: 17.57
- UOPS_DISPATCHED.ALU: 17.35
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.5
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.05
- UOPS_DISPATCHED.STA: 4.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 7.41
- Reference cycles: 5.22
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.13
- UOPS_MS: 0.02
- UOPS_DISPATCHED.INT_EU_ALL: 17.27
- UOPS_DISPATCHED.ALU: 17.52
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 10.48
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.05
- UOPS_DISPATCHED.STA: 4.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
   b:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  11:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2
  17:	43 83 44 2e 10 02    	add    DWORD PTR [r14+r13*1+0x10],0x2
  1d:	43 83 44 2e 14 02    	add    DWORD PTR [r14+r13*1+0x14],0x2
  23:	43 83 44 2e 18 02    	add    DWORD PTR [r14+r13*1+0x18],0x2
  29:	43 83 44 2e 1c 02    	add    DWORD PTR [r14+r13*1+0x1c],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.12
- Reference cycles: 5.56
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 24.02
- UOPS_MITE: 24.0
- UOPS_MS: 0.37
- UOPS_DISPATCHED.INT_EU_ALL: 22.36
- UOPS_DISPATCHED.ALU: 22.56
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 11.82
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 8.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.79

With loop_count=1000 and unroll_count=1

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
   b:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  11:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2
  17:	43 83 44 2e 10 02    	add    DWORD PTR [r14+r13*1+0x10],0x2
  1d:	43 83 44 2e 14 02    	add    DWORD PTR [r14+r13*1+0x14],0x2
  23:	43 83 44 2e 18 02    	add    DWORD PTR [r14+r13*1+0x18],0x2
  29:	43 83 44 2e 1c 02    	add    DWORD PTR [r14+r13*1+0x1c],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 7.85
- Reference cycles: 5.52
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.42
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 23.29
- UOPS_DISPATCHED.ALU: 22.11
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 11.86
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 1.0
- UOPS_DISPATCHED.STA: 8.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	43 83 44 2e 10 02    	add    DWORD PTR [r14+r13*1+0x10],0x2
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	43 83 44 2e 14 02    	add    DWORD PTR [r14+r13*1+0x14],0x2
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	43 83 44 2e 18 02    	add    DWORD PTR [r14+r13*1+0x18],0x2
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	43 83 44 2e 1c 02    	add    DWORD PTR [r14+r13*1+0x1c],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 7.86
- Reference cycles: 5.52
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 23.39
- UOPS_DISPATCHED.ALU: 22.41
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 11.89
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 1.0
- UOPS_DISPATCHED.STA: 8.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
   b:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  11:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2
  17:	43 83 44 2e 10 02    	add    DWORD PTR [r14+r13*1+0x10],0x2
  1d:	43 83 44 2e 14 02    	add    DWORD PTR [r14+r13*1+0x14],0x2
  23:	43 83 44 2e 18 02    	add    DWORD PTR [r14+r13*1+0x18],0x2
  29:	43 83 44 2e 1c 02    	add    DWORD PTR [r14+r13*1+0x1c],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 7.83
- Reference cycles: 5.52
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.25
- UOPS_MS: 0.06
- UOPS_DISPATCHED.INT_EU_ALL: 22.34
- UOPS_DISPATCHED.ALU: 22.3
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 11.83
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 8.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	43 83 44 2e 10 02    	add    DWORD PTR [r14+r13*1+0x10],0x2
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	43 83 44 2e 14 02    	add    DWORD PTR [r14+r13*1+0x14],0x2
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	43 83 44 2e 18 02    	add    DWORD PTR [r14+r13*1+0x18],0x2
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	43 83 44 2e 1c 02    	add    DWORD PTR [r14+r13*1+0x1c],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 7.85
- Reference cycles: 5.5
- UOPS_EXECUTED.THREAD: 32.11
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.24
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 22.26
- UOPS_DISPATCHED.ALU: 22.27
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 11.79
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 8.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
   b:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  11:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2
  17:	43 83 44 2e 10 02    	add    DWORD PTR [r14+r13*1+0x10],0x2
  1d:	43 83 44 2e 14 02    	add    DWORD PTR [r14+r13*1+0x14],0x2
  23:	43 83 44 2e 18 02    	add    DWORD PTR [r14+r13*1+0x18],0x2
  29:	43 83 44 2e 1c 02    	add    DWORD PTR [r14+r13*1+0x1c],0x2
  2f:	43 83 44 2e 20 02    	add    DWORD PTR [r14+r13*1+0x20],0x2
  35:	43 83 44 2e 24 02    	add    DWORD PTR [r14+r13*1+0x24],0x2
  3b:	43 83 44 2e 28 02    	add    DWORD PTR [r14+r13*1+0x28],0x2
  41:	43 83 44 2e 2c 02    	add    DWORD PTR [r14+r13*1+0x2c],0x2
  47:	43 83 44 2e 30 02    	add    DWORD PTR [r14+r13*1+0x30],0x2
  4d:	43 83 44 2e 34 02    	add    DWORD PTR [r14+r13*1+0x34],0x2
  53:	43 83 44 2e 38 02    	add    DWORD PTR [r14+r13*1+0x38],0x2
  59:	43 83 44 2e 3c 02    	add    DWORD PTR [r14+r13*1+0x3c],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 11.45
- UOPS_EXECUTED.THREAD: 64.0
- RETIRE_SLOTS: 48.0
- UOPS_MITE: 48.0
- UOPS_MS: 0.0
- UOPS_DISPATCHED.INT_EU_ALL: 16.02
- UOPS_DISPATCHED.ALU: 16.01
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 16.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 16.0
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
   b:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  11:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2
  17:	43 83 44 2e 10 02    	add    DWORD PTR [r14+r13*1+0x10],0x2
  1d:	43 83 44 2e 14 02    	add    DWORD PTR [r14+r13*1+0x14],0x2
  23:	43 83 44 2e 18 02    	add    DWORD PTR [r14+r13*1+0x18],0x2
  29:	43 83 44 2e 1c 02    	add    DWORD PTR [r14+r13*1+0x1c],0x2
  2f:	43 83 44 2e 20 02    	add    DWORD PTR [r14+r13*1+0x20],0x2
  35:	43 83 44 2e 24 02    	add    DWORD PTR [r14+r13*1+0x24],0x2
  3b:	43 83 44 2e 28 02    	add    DWORD PTR [r14+r13*1+0x28],0x2
  41:	43 83 44 2e 2c 02    	add    DWORD PTR [r14+r13*1+0x2c],0x2
  47:	43 83 44 2e 30 02    	add    DWORD PTR [r14+r13*1+0x30],0x2
  4d:	43 83 44 2e 34 02    	add    DWORD PTR [r14+r13*1+0x34],0x2
  53:	43 83 44 2e 38 02    	add    DWORD PTR [r14+r13*1+0x38],0x2
  59:	43 83 44 2e 3c 02    	add    DWORD PTR [r14+r13*1+0x3c],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 9.28
- Reference cycles: 6.55
- UOPS_EXECUTED.THREAD: 65.02
- RETIRE_SLOTS: 49.01
- UOPS_MITE: 0.27
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 28.09
- UOPS_DISPATCHED.ALU: 27.11
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 16.23
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 1.0
- UOPS_DISPATCHED.STA: 16.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	43 83 44 2e 10 02    	add    DWORD PTR [r14+r13*1+0x10],0x2
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	43 83 44 2e 14 02    	add    DWORD PTR [r14+r13*1+0x14],0x2
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	43 83 44 2e 18 02    	add    DWORD PTR [r14+r13*1+0x18],0x2
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	43 83 44 2e 1c 02    	add    DWORD PTR [r14+r13*1+0x1c],0x2
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	43 83 44 2e 20 02    	add    DWORD PTR [r14+r13*1+0x20],0x2
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	43 83 44 2e 24 02    	add    DWORD PTR [r14+r13*1+0x24],0x2
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	43 83 44 2e 28 02    	add    DWORD PTR [r14+r13*1+0x28],0x2
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	43 83 44 2e 2c 02    	add    DWORD PTR [r14+r13*1+0x2c],0x2
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	43 83 44 2e 30 02    	add    DWORD PTR [r14+r13*1+0x30],0x2
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	43 83 44 2e 34 02    	add    DWORD PTR [r14+r13*1+0x34],0x2
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	43 83 44 2e 38 02    	add    DWORD PTR [r14+r13*1+0x38],0x2
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	43 83 44 2e 3c 02    	add    DWORD PTR [r14+r13*1+0x3c],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 9.26
- Reference cycles: 6.51
- UOPS_EXECUTED.THREAD: 65.02
- RETIRE_SLOTS: 49.01
- UOPS_MITE: 0.04
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 28.12
- UOPS_DISPATCHED.ALU: 27.14
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 16.22
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 1.0
- UOPS_DISPATCHED.STA: 16.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   5:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
   b:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  11:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2
  17:	43 83 44 2e 10 02    	add    DWORD PTR [r14+r13*1+0x10],0x2
  1d:	43 83 44 2e 14 02    	add    DWORD PTR [r14+r13*1+0x14],0x2
  23:	43 83 44 2e 18 02    	add    DWORD PTR [r14+r13*1+0x18],0x2
  29:	43 83 44 2e 1c 02    	add    DWORD PTR [r14+r13*1+0x1c],0x2
  2f:	43 83 44 2e 20 02    	add    DWORD PTR [r14+r13*1+0x20],0x2
  35:	43 83 44 2e 24 02    	add    DWORD PTR [r14+r13*1+0x24],0x2
  3b:	43 83 44 2e 28 02    	add    DWORD PTR [r14+r13*1+0x28],0x2
  41:	43 83 44 2e 2c 02    	add    DWORD PTR [r14+r13*1+0x2c],0x2
  47:	43 83 44 2e 30 02    	add    DWORD PTR [r14+r13*1+0x30],0x2
  4d:	43 83 44 2e 34 02    	add    DWORD PTR [r14+r13*1+0x34],0x2
  53:	43 83 44 2e 38 02    	add    DWORD PTR [r14+r13*1+0x38],0x2
  59:	43 83 44 2e 3c 02    	add    DWORD PTR [r14+r13*1+0x3c],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 9.37
- Reference cycles: 6.65
- UOPS_EXECUTED.THREAD: 64.12
- RETIRE_SLOTS: 48.11
- UOPS_MITE: 0.47
- UOPS_MS: 0.06
- UOPS_DISPATCHED.INT_EU_ALL: 27.18
- UOPS_DISPATCHED.ALU: 27.05
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 16.22
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 16.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.14

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 83 04 2e 02       	add    DWORD PTR [r14+r13*1],0x2
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 83 44 2e 04 02    	add    DWORD PTR [r14+r13*1+0x4],0x2
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 83 44 2e 08 02    	add    DWORD PTR [r14+r13*1+0x8],0x2
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 83 44 2e 0c 02    	add    DWORD PTR [r14+r13*1+0xc],0x2
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	43 83 44 2e 10 02    	add    DWORD PTR [r14+r13*1+0x10],0x2
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	43 83 44 2e 14 02    	add    DWORD PTR [r14+r13*1+0x14],0x2
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	43 83 44 2e 18 02    	add    DWORD PTR [r14+r13*1+0x18],0x2
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	43 83 44 2e 1c 02    	add    DWORD PTR [r14+r13*1+0x1c],0x2
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	43 83 44 2e 20 02    	add    DWORD PTR [r14+r13*1+0x20],0x2
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	43 83 44 2e 24 02    	add    DWORD PTR [r14+r13*1+0x24],0x2
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	43 83 44 2e 28 02    	add    DWORD PTR [r14+r13*1+0x28],0x2
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	43 83 44 2e 2c 02    	add    DWORD PTR [r14+r13*1+0x2c],0x2
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	43 83 44 2e 30 02    	add    DWORD PTR [r14+r13*1+0x30],0x2
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	43 83 44 2e 34 02    	add    DWORD PTR [r14+r13*1+0x34],0x2
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	43 83 44 2e 38 02    	add    DWORD PTR [r14+r13*1+0x38],0x2
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	43 83 44 2e 3c 02    	add    DWORD PTR [r14+r13*1+0x3c],0x2

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 9.3
- Reference cycles: 6.53
- UOPS_EXECUTED.THREAD: 64.12
- RETIRE_SLOTS: 48.11
- UOPS_MITE: 0.47
- UOPS_MS: 0.04
- UOPS_DISPATCHED.INT_EU_ALL: 27.19
- UOPS_DISPATCHED.ALU: 27.03
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 16.22
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.1
- UOPS_DISPATCHED.STA: 16.01
- UOPS_DISPATCHED.V0: 0.0
- UOPS_DISPATCHED.V1: 0.0
- UOPS_DISPATCHED.V2: 0.0
- UOPS_DISPATCHED.V3: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.14

ADD (M32, I8) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With unroll_count=500, no inner loop, and 5 NOPs

With unroll_count=500, no inner loop, and 6 NOPs

With unroll_count=500, no inner loop, and 7 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With unroll_count=500, no inner loop, and 5 NOPs

With unroll_count=500, no inner loop, and 6 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)