VPMULUDQ (ZMM, ZMM, ZMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.77
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.18

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.2
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.72

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 3.02
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.03
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 3.02
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.03
- UOPS_MS: 0.02
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2
  18:	62 f1 f5 48 f4 f2    	vpmuludq zmm6,zmm1,zmm2
  1e:	62 f1 f5 48 f4 fa    	vpmuludq zmm7,zmm1,zmm2
  24:	62 71 f5 48 f4 c2    	vpmuludq zmm8,zmm1,zmm2
  2a:	62 71 f5 48 f4 ca    	vpmuludq zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 6.56
- UOPS_EXECUTED.THREAD: 8.04
- RETIRE_SLOTS: 8.01
- UOPS_MITE: 7.86
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.44

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2
  18:	62 f1 f5 48 f4 f2    	vpmuludq zmm6,zmm1,zmm2
  1e:	62 f1 f5 48 f4 fa    	vpmuludq zmm7,zmm1,zmm2
  24:	62 71 f5 48 f4 c2    	vpmuludq zmm8,zmm1,zmm2
  2a:	62 71 f5 48 f4 ca    	vpmuludq zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 6.0
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: -0.01
- UOPS_MS: 0.05
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2
  18:	62 f1 f5 48 f4 f2    	vpmuludq zmm6,zmm1,zmm2
  1e:	62 f1 f5 48 f4 fa    	vpmuludq zmm7,zmm1,zmm2
  24:	62 71 f5 48 f4 c2    	vpmuludq zmm8,zmm1,zmm2
  2a:	62 71 f5 48 f4 ca    	vpmuludq zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 5.98
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.11
- UOPS_MITE: 0.06
- UOPS_MS: 0.05
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2
  18:	62 f1 f5 48 f4 f2    	vpmuludq zmm6,zmm1,zmm2
  1e:	62 f1 f5 48 f4 fa    	vpmuludq zmm7,zmm1,zmm2
  24:	62 71 f5 48 f4 c2    	vpmuludq zmm8,zmm1,zmm2
  2a:	62 71 f5 48 f4 ca    	vpmuludq zmm9,zmm1,zmm2
  30:	62 71 f5 48 f4 d2    	vpmuludq zmm10,zmm1,zmm2
  36:	62 71 f5 48 f4 da    	vpmuludq zmm11,zmm1,zmm2
  3c:	62 71 f5 48 f4 e2    	vpmuludq zmm12,zmm1,zmm2
  42:	62 e1 f5 48 f4 c2    	vpmuludq zmm16,zmm1,zmm2
  48:	62 e1 f5 48 f4 ca    	vpmuludq zmm17,zmm1,zmm2
  4e:	62 e1 f5 48 f4 d2    	vpmuludq zmm18,zmm1,zmm2
  54:	62 e1 f5 48 f4 da    	vpmuludq zmm19,zmm1,zmm2
  5a:	62 e1 f5 48 f4 e2    	vpmuludq zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 12.16
- UOPS_EXECUTED.THREAD: 15.99
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.01
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.89

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2
  18:	62 f1 f5 48 f4 f2    	vpmuludq zmm6,zmm1,zmm2
  1e:	62 f1 f5 48 f4 fa    	vpmuludq zmm7,zmm1,zmm2
  24:	62 71 f5 48 f4 c2    	vpmuludq zmm8,zmm1,zmm2
  2a:	62 71 f5 48 f4 ca    	vpmuludq zmm9,zmm1,zmm2
  30:	62 71 f5 48 f4 d2    	vpmuludq zmm10,zmm1,zmm2
  36:	62 71 f5 48 f4 da    	vpmuludq zmm11,zmm1,zmm2
  3c:	62 71 f5 48 f4 e2    	vpmuludq zmm12,zmm1,zmm2
  42:	62 e1 f5 48 f4 c2    	vpmuludq zmm16,zmm1,zmm2
  48:	62 e1 f5 48 f4 ca    	vpmuludq zmm17,zmm1,zmm2
  4e:	62 e1 f5 48 f4 d2    	vpmuludq zmm18,zmm1,zmm2
  54:	62 e1 f5 48 f4 da    	vpmuludq zmm19,zmm1,zmm2
  5a:	62 e1 f5 48 f4 e2    	vpmuludq zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 12.02
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.01
- UOPS_MITE: 0.0
- UOPS_MS: 0.05
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 f5 48 f4 c2    	vpmuludq zmm0,zmm1,zmm2
   6:	62 f1 f5 48 f4 da    	vpmuludq zmm3,zmm1,zmm2
   c:	62 f1 f5 48 f4 e2    	vpmuludq zmm4,zmm1,zmm2
  12:	62 f1 f5 48 f4 ea    	vpmuludq zmm5,zmm1,zmm2
  18:	62 f1 f5 48 f4 f2    	vpmuludq zmm6,zmm1,zmm2
  1e:	62 f1 f5 48 f4 fa    	vpmuludq zmm7,zmm1,zmm2
  24:	62 71 f5 48 f4 c2    	vpmuludq zmm8,zmm1,zmm2
  2a:	62 71 f5 48 f4 ca    	vpmuludq zmm9,zmm1,zmm2
  30:	62 71 f5 48 f4 d2    	vpmuludq zmm10,zmm1,zmm2
  36:	62 71 f5 48 f4 da    	vpmuludq zmm11,zmm1,zmm2
  3c:	62 71 f5 48 f4 e2    	vpmuludq zmm12,zmm1,zmm2
  42:	62 e1 f5 48 f4 c2    	vpmuludq zmm16,zmm1,zmm2
  48:	62 e1 f5 48 f4 ca    	vpmuludq zmm17,zmm1,zmm2
  4e:	62 e1 f5 48 f4 d2    	vpmuludq zmm18,zmm1,zmm2
  54:	62 e1 f5 48 f4 da    	vpmuludq zmm19,zmm1,zmm2
  5a:	62 e1 f5 48 f4 e2    	vpmuludq zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.01
- Reference cycles: 12.0
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.12
- UOPS_MS: 0.06
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With the same register for for different operands

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 5.0
- Reference cycles: 3.74
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.19

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 5.0
- Reference cycles: 3.76
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 fd 48 f4 c0    	vpmuludq zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 5.0
- Reference cycles: 3.76
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

VPMULUDQ (ZMM, ZMM, ZMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100