VMOVDQU (XMM, M128)

With unroll_count=500 and no inner loop

Code:

   0:	c4 c1 7a 6f 06       	vmovdqu xmm0,XMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.5
- Reference cycles: 0.38
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 0.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.17

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 c1 7a 6f 06       	vmovdqu xmm0,XMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.5
- Reference cycles: 0.38
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 c1 7a 6f 06       	vmovdqu xmm0,XMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.5
- Reference cycles: 0.38
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 c1 7a 6f 06       	vmovdqu xmm0,XMMWORD PTR [r14]
   5:	c4 c1 7a 6f 4e 10    	vmovdqu xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 7a 6f 56 20    	vmovdqu xmm2,XMMWORD PTR [r14+0x20]
  11:	c4 c1 7a 6f 5e 30    	vmovdqu xmm3,XMMWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.34
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.71

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 c1 7a 6f 06       	vmovdqu xmm0,XMMWORD PTR [r14]
   5:	c4 c1 7a 6f 4e 10    	vmovdqu xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 7a 6f 56 20    	vmovdqu xmm2,XMMWORD PTR [r14+0x20]
  11:	c4 c1 7a 6f 5e 30    	vmovdqu xmm3,XMMWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.34
- Reference cycles: 1.01
- UOPS_EXECUTED.THREAD: 4.51
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 c1 7a 6f 06       	vmovdqu xmm0,XMMWORD PTR [r14]
   5:	c4 c1 7a 6f 4e 10    	vmovdqu xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 7a 6f 56 20    	vmovdqu xmm2,XMMWORD PTR [r14+0x20]
  11:	c4 c1 7a 6f 5e 30    	vmovdqu xmm3,XMMWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 1.34
- Reference cycles: 1.01
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c1 7a 6f 06       	vmovdqu xmm0,XMMWORD PTR [r14]
   5:	c4 c1 7a 6f 4e 10    	vmovdqu xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 7a 6f 56 20    	vmovdqu xmm2,XMMWORD PTR [r14+0x20]
  11:	c4 c1 7a 6f 5e 30    	vmovdqu xmm3,XMMWORD PTR [r14+0x30]
  17:	c4 c1 7a 6f 66 40    	vmovdqu xmm4,XMMWORD PTR [r14+0x40]
  1d:	c4 c1 7a 6f 6e 50    	vmovdqu xmm5,XMMWORD PTR [r14+0x50]
  23:	c4 c1 7a 6f 76 60    	vmovdqu xmm6,XMMWORD PTR [r14+0x60]
  29:	c4 c1 7a 6f 7e 70    	vmovdqu xmm7,XMMWORD PTR [r14+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 2.69
- Reference cycles: 2.24
- UOPS_EXECUTED.THREAD: 8.02
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.02
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.4

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c1 7a 6f 06       	vmovdqu xmm0,XMMWORD PTR [r14]
   5:	c4 c1 7a 6f 4e 10    	vmovdqu xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 7a 6f 56 20    	vmovdqu xmm2,XMMWORD PTR [r14+0x20]
  11:	c4 c1 7a 6f 5e 30    	vmovdqu xmm3,XMMWORD PTR [r14+0x30]
  17:	c4 c1 7a 6f 66 40    	vmovdqu xmm4,XMMWORD PTR [r14+0x40]
  1d:	c4 c1 7a 6f 6e 50    	vmovdqu xmm5,XMMWORD PTR [r14+0x50]
  23:	c4 c1 7a 6f 76 60    	vmovdqu xmm6,XMMWORD PTR [r14+0x60]
  29:	c4 c1 7a 6f 7e 70    	vmovdqu xmm7,XMMWORD PTR [r14+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 2.69
- Reference cycles: 2.02
- UOPS_EXECUTED.THREAD: 9.01
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.0
- UOPS_MS: 0.05
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c1 7a 6f 06       	vmovdqu xmm0,XMMWORD PTR [r14]
   5:	c4 c1 7a 6f 4e 10    	vmovdqu xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 7a 6f 56 20    	vmovdqu xmm2,XMMWORD PTR [r14+0x20]
  11:	c4 c1 7a 6f 5e 30    	vmovdqu xmm3,XMMWORD PTR [r14+0x30]
  17:	c4 c1 7a 6f 66 40    	vmovdqu xmm4,XMMWORD PTR [r14+0x40]
  1d:	c4 c1 7a 6f 6e 50    	vmovdqu xmm5,XMMWORD PTR [r14+0x50]
  23:	c4 c1 7a 6f 76 60    	vmovdqu xmm6,XMMWORD PTR [r14+0x60]
  29:	c4 c1 7a 6f 7e 70    	vmovdqu xmm7,XMMWORD PTR [r14+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 2.68
- Reference cycles: 2.02
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.06
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c1 7a 6f 06       	vmovdqu xmm0,XMMWORD PTR [r14]
   5:	c4 c1 7a 6f 4e 10    	vmovdqu xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 7a 6f 56 20    	vmovdqu xmm2,XMMWORD PTR [r14+0x20]
  11:	c4 c1 7a 6f 5e 30    	vmovdqu xmm3,XMMWORD PTR [r14+0x30]
  17:	c4 c1 7a 6f 66 40    	vmovdqu xmm4,XMMWORD PTR [r14+0x40]
  1d:	c4 c1 7a 6f 6e 50    	vmovdqu xmm5,XMMWORD PTR [r14+0x50]
  23:	c4 c1 7a 6f 76 60    	vmovdqu xmm6,XMMWORD PTR [r14+0x60]
  29:	c4 c1 7a 6f 7e 70    	vmovdqu xmm7,XMMWORD PTR [r14+0x70]
  2f:	c4 41 7a 6f 86 80 00 	vmovdqu xmm8,XMMWORD PTR [r14+0x80]
  36:	00 00 
  38:	c4 41 7a 6f 8e 90 00 	vmovdqu xmm9,XMMWORD PTR [r14+0x90]
  3f:	00 00 
  41:	c4 41 7a 6f 96 a0 00 	vmovdqu xmm10,XMMWORD PTR [r14+0xa0]
  48:	00 00 
  4a:	c4 41 7a 6f 9e b0 00 	vmovdqu xmm11,XMMWORD PTR [r14+0xb0]
  51:	00 00 
  53:	c4 41 7a 6f a6 c0 00 	vmovdqu xmm12,XMMWORD PTR [r14+0xc0]
  5a:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 4.44
- Reference cycles: 3.04
- UOPS_EXECUTED.THREAD: 12.98
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 12.74
- UOPS_MS: 0.56
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 13.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.51

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c1 7a 6f 06       	vmovdqu xmm0,XMMWORD PTR [r14]
   5:	c4 c1 7a 6f 4e 10    	vmovdqu xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 7a 6f 56 20    	vmovdqu xmm2,XMMWORD PTR [r14+0x20]
  11:	c4 c1 7a 6f 5e 30    	vmovdqu xmm3,XMMWORD PTR [r14+0x30]
  17:	c4 c1 7a 6f 66 40    	vmovdqu xmm4,XMMWORD PTR [r14+0x40]
  1d:	c4 c1 7a 6f 6e 50    	vmovdqu xmm5,XMMWORD PTR [r14+0x50]
  23:	c4 c1 7a 6f 76 60    	vmovdqu xmm6,XMMWORD PTR [r14+0x60]
  29:	c4 c1 7a 6f 7e 70    	vmovdqu xmm7,XMMWORD PTR [r14+0x70]
  2f:	c4 41 7a 6f 86 80 00 	vmovdqu xmm8,XMMWORD PTR [r14+0x80]
  36:	00 00 
  38:	c4 41 7a 6f 8e 90 00 	vmovdqu xmm9,XMMWORD PTR [r14+0x90]
  3f:	00 00 
  41:	c4 41 7a 6f 96 a0 00 	vmovdqu xmm10,XMMWORD PTR [r14+0xa0]
  48:	00 00 
  4a:	c4 41 7a 6f 9e b0 00 	vmovdqu xmm11,XMMWORD PTR [r14+0xb0]
  51:	00 00 
  53:	c4 41 7a 6f a6 c0 00 	vmovdqu xmm12,XMMWORD PTR [r14+0xc0]
  5a:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 4.36
- Reference cycles: 3.26
- UOPS_EXECUTED.THREAD: 14.01
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.06
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 13.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c1 7a 6f 06       	vmovdqu xmm0,XMMWORD PTR [r14]
   5:	c4 c1 7a 6f 4e 10    	vmovdqu xmm1,XMMWORD PTR [r14+0x10]
   b:	c4 c1 7a 6f 56 20    	vmovdqu xmm2,XMMWORD PTR [r14+0x20]
  11:	c4 c1 7a 6f 5e 30    	vmovdqu xmm3,XMMWORD PTR [r14+0x30]
  17:	c4 c1 7a 6f 66 40    	vmovdqu xmm4,XMMWORD PTR [r14+0x40]
  1d:	c4 c1 7a 6f 6e 50    	vmovdqu xmm5,XMMWORD PTR [r14+0x50]
  23:	c4 c1 7a 6f 76 60    	vmovdqu xmm6,XMMWORD PTR [r14+0x60]
  29:	c4 c1 7a 6f 7e 70    	vmovdqu xmm7,XMMWORD PTR [r14+0x70]
  2f:	c4 41 7a 6f 86 80 00 	vmovdqu xmm8,XMMWORD PTR [r14+0x80]
  36:	00 00 
  38:	c4 41 7a 6f 8e 90 00 	vmovdqu xmm9,XMMWORD PTR [r14+0x90]
  3f:	00 00 
  41:	c4 41 7a 6f 96 a0 00 	vmovdqu xmm10,XMMWORD PTR [r14+0xa0]
  48:	00 00 
  4a:	c4 41 7a 6f 9e b0 00 	vmovdqu xmm11,XMMWORD PTR [r14+0xb0]
  51:	00 00 
  53:	c4 41 7a 6f a6 c0 00 	vmovdqu xmm12,XMMWORD PTR [r14+0xc0]
  5a:	00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 4.35
- Reference cycles: 3.26
- UOPS_EXECUTED.THREAD: 13.11
- RETIRE_SLOTS: 13.1
- UOPS_MITE: 0.13
- UOPS_MS: 0.06
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 13.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 81 7a 6f 04 2e    	vmovdqu xmm0,XMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.51
- Reference cycles: 0.38
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.18

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 81 7a 6f 04 2e    	vmovdqu xmm0,XMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.5
- Reference cycles: 0.38
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 81 7a 6f 04 2e    	vmovdqu xmm0,XMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.5
- Reference cycles: 0.38
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 81 7a 6f 04 2e    	vmovdqu xmm0,XMMWORD PTR [r14+r13*1]
   6:	c4 81 7a 6f 4c 2e 10 	vmovdqu xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 7a 6f 54 2e 20 	vmovdqu xmm2,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 7a 6f 5c 2e 30 	vmovdqu xmm3,XMMWORD PTR [r14+r13*1+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.32
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 3.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.77

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 81 7a 6f 04 2e    	vmovdqu xmm0,XMMWORD PTR [r14+r13*1]
   6:	c4 81 7a 6f 4c 2e 10 	vmovdqu xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 7a 6f 54 2e 20 	vmovdqu xmm2,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 7a 6f 5c 2e 30 	vmovdqu xmm3,XMMWORD PTR [r14+r13*1+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.34
- Reference cycles: 1.01
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 81 7a 6f 04 2e    	vmovdqu xmm0,XMMWORD PTR [r14+r13*1]
   6:	c4 81 7a 6f 4c 2e 10 	vmovdqu xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 7a 6f 54 2e 20 	vmovdqu xmm2,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 7a 6f 5c 2e 30 	vmovdqu xmm3,XMMWORD PTR [r14+r13*1+0x30]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 1.34
- Reference cycles: 1.01
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 81 7a 6f 04 2e    	vmovdqu xmm0,XMMWORD PTR [r14+r13*1]
   6:	c4 81 7a 6f 4c 2e 10 	vmovdqu xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 7a 6f 54 2e 20 	vmovdqu xmm2,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 7a 6f 5c 2e 30 	vmovdqu xmm3,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 81 7a 6f 64 2e 40 	vmovdqu xmm4,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 81 7a 6f 6c 2e 50 	vmovdqu xmm5,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 81 7a 6f 74 2e 60 	vmovdqu xmm6,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 81 7a 6f 7c 2e 70 	vmovdqu xmm7,XMMWORD PTR [r14+r13*1+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 2.68
- Reference cycles: 1.92
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 7.9
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.53

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 81 7a 6f 04 2e    	vmovdqu xmm0,XMMWORD PTR [r14+r13*1]
   6:	c4 81 7a 6f 4c 2e 10 	vmovdqu xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 7a 6f 54 2e 20 	vmovdqu xmm2,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 7a 6f 5c 2e 30 	vmovdqu xmm3,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 81 7a 6f 64 2e 40 	vmovdqu xmm4,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 81 7a 6f 6c 2e 50 	vmovdqu xmm5,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 81 7a 6f 74 2e 60 	vmovdqu xmm6,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 81 7a 6f 7c 2e 70 	vmovdqu xmm7,XMMWORD PTR [r14+r13*1+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 2.69
- Reference cycles: 2.02
- UOPS_EXECUTED.THREAD: 9.01
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.0
- UOPS_MS: 0.06
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 81 7a 6f 04 2e    	vmovdqu xmm0,XMMWORD PTR [r14+r13*1]
   6:	c4 81 7a 6f 4c 2e 10 	vmovdqu xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 7a 6f 54 2e 20 	vmovdqu xmm2,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 7a 6f 5c 2e 30 	vmovdqu xmm3,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 81 7a 6f 64 2e 40 	vmovdqu xmm4,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 81 7a 6f 6c 2e 50 	vmovdqu xmm5,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 81 7a 6f 74 2e 60 	vmovdqu xmm6,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 81 7a 6f 7c 2e 70 	vmovdqu xmm7,XMMWORD PTR [r14+r13*1+0x70]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 2.69
- Reference cycles: 2.02
- UOPS_EXECUTED.THREAD: 8.11
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.06
- UOPS_MS: 0.05
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 13 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 81 7a 6f 04 2e    	vmovdqu xmm0,XMMWORD PTR [r14+r13*1]
   6:	c4 81 7a 6f 4c 2e 10 	vmovdqu xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 7a 6f 54 2e 20 	vmovdqu xmm2,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 7a 6f 5c 2e 30 	vmovdqu xmm3,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 81 7a 6f 64 2e 40 	vmovdqu xmm4,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 81 7a 6f 6c 2e 50 	vmovdqu xmm5,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 81 7a 6f 74 2e 60 	vmovdqu xmm6,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 81 7a 6f 7c 2e 70 	vmovdqu xmm7,XMMWORD PTR [r14+r13*1+0x70]
  37:	c4 01 7a 6f 84 2e 80 	vmovdqu xmm8,XMMWORD PTR [r14+r13*1+0x80]
  3e:	00 00 00 
  41:	c4 01 7a 6f 8c 2e 90 	vmovdqu xmm9,XMMWORD PTR [r14+r13*1+0x90]
  48:	00 00 00 
  4b:	c4 01 7a 6f 94 2e a0 	vmovdqu xmm10,XMMWORD PTR [r14+r13*1+0xa0]
  52:	00 00 00 
  55:	c4 01 7a 6f 9c 2e b0 	vmovdqu xmm11,XMMWORD PTR [r14+r13*1+0xb0]
  5c:	00 00 00 
  5f:	c4 01 7a 6f a4 2e c0 	vmovdqu xmm12,XMMWORD PTR [r14+r13*1+0xc0]
  66:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 4.43
- Reference cycles: 3.36
- UOPS_EXECUTED.THREAD: 12.98
- RETIRE_SLOTS: 13.0
- UOPS_MITE: 12.82
- UOPS_MS: 0.56
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 13.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.78

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 81 7a 6f 04 2e    	vmovdqu xmm0,XMMWORD PTR [r14+r13*1]
   6:	c4 81 7a 6f 4c 2e 10 	vmovdqu xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 7a 6f 54 2e 20 	vmovdqu xmm2,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 7a 6f 5c 2e 30 	vmovdqu xmm3,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 81 7a 6f 64 2e 40 	vmovdqu xmm4,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 81 7a 6f 6c 2e 50 	vmovdqu xmm5,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 81 7a 6f 74 2e 60 	vmovdqu xmm6,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 81 7a 6f 7c 2e 70 	vmovdqu xmm7,XMMWORD PTR [r14+r13*1+0x70]
  37:	c4 01 7a 6f 84 2e 80 	vmovdqu xmm8,XMMWORD PTR [r14+r13*1+0x80]
  3e:	00 00 00 
  41:	c4 01 7a 6f 8c 2e 90 	vmovdqu xmm9,XMMWORD PTR [r14+r13*1+0x90]
  48:	00 00 00 
  4b:	c4 01 7a 6f 94 2e a0 	vmovdqu xmm10,XMMWORD PTR [r14+r13*1+0xa0]
  52:	00 00 00 
  55:	c4 01 7a 6f 9c 2e b0 	vmovdqu xmm11,XMMWORD PTR [r14+r13*1+0xb0]
  5c:	00 00 00 
  5f:	c4 01 7a 6f a4 2e c0 	vmovdqu xmm12,XMMWORD PTR [r14+r13*1+0xc0]
  66:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 4.35
- Reference cycles: 3.26
- UOPS_EXECUTED.THREAD: 14.02
- RETIRE_SLOTS: 14.0
- UOPS_MITE: 0.0
- UOPS_MS: 0.05
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 13.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 81 7a 6f 04 2e    	vmovdqu xmm0,XMMWORD PTR [r14+r13*1]
   6:	c4 81 7a 6f 4c 2e 10 	vmovdqu xmm1,XMMWORD PTR [r14+r13*1+0x10]
   d:	c4 81 7a 6f 54 2e 20 	vmovdqu xmm2,XMMWORD PTR [r14+r13*1+0x20]
  14:	c4 81 7a 6f 5c 2e 30 	vmovdqu xmm3,XMMWORD PTR [r14+r13*1+0x30]
  1b:	c4 81 7a 6f 64 2e 40 	vmovdqu xmm4,XMMWORD PTR [r14+r13*1+0x40]
  22:	c4 81 7a 6f 6c 2e 50 	vmovdqu xmm5,XMMWORD PTR [r14+r13*1+0x50]
  29:	c4 81 7a 6f 74 2e 60 	vmovdqu xmm6,XMMWORD PTR [r14+r13*1+0x60]
  30:	c4 81 7a 6f 7c 2e 70 	vmovdqu xmm7,XMMWORD PTR [r14+r13*1+0x70]
  37:	c4 01 7a 6f 84 2e 80 	vmovdqu xmm8,XMMWORD PTR [r14+r13*1+0x80]
  3e:	00 00 00 
  41:	c4 01 7a 6f 8c 2e 90 	vmovdqu xmm9,XMMWORD PTR [r14+r13*1+0x90]
  48:	00 00 00 
  4b:	c4 01 7a 6f 94 2e a0 	vmovdqu xmm10,XMMWORD PTR [r14+r13*1+0xa0]
  52:	00 00 00 
  55:	c4 01 7a 6f 9c 2e b0 	vmovdqu xmm11,XMMWORD PTR [r14+r13*1+0xb0]
  5c:	00 00 00 
  5f:	c4 01 7a 6f a4 2e c0 	vmovdqu xmm12,XMMWORD PTR [r14+r13*1+0xc0]
  66:	00 00 00

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 13.2
- Core cycles: 4.36
- Reference cycles: 3.26
- UOPS_EXECUTED.THREAD: 13.11
- RETIRE_SLOTS: 13.1
- UOPS_MITE: 0.12
- UOPS_MS: 0.06
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 13.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

VMOVDQU (XMM, M128) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 13 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10