VINSERTI128 (YMM, YMM, M128, I8)

With unroll_count=500 and no inner loop

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.67
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.31
- UOPS_PORT_1: 0.31
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.38
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.97
- Reference cycles: 0.7
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.11
- UOPS_PORT_0: 0.31
- UOPS_PORT_1: 0.32
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.37
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 0.67
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 3.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.31
- UOPS_PORT_1: 0.31
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.38
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.0
- Reference cycles: 0.83
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.31
- UOPS_PORT_1: 0.32
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.37
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.0
- Reference cycles: 0.77
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.44
- UOPS_PORT_1: 0.44
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.12
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 5 NOPs

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 2.0
- Reference cycles: 1.47
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.25
- UOPS_PORT_1: 0.38
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.37
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.51
- Reference cycles: 0.43
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.41
- UOPS_PORT_1: 0.41
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.42
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.51
- Reference cycles: 0.39
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.41
- UOPS_PORT_1: 0.42
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.42
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c4 c3 75 38 56 10 02 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+0x10],0x2
   d:	c4 c3 75 38 5e 20 02 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+0x20],0x2
  14:	c4 c3 75 38 66 30 02 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+0x30],0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.88
- UOPS_EXECUTED.THREAD: 7.99
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 7.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.25
- UOPS_PORT_1: 1.27
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.5
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.99

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c4 c3 75 38 56 10 02 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+0x10],0x2
   d:	c4 c3 75 38 5e 20 02 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+0x20],0x2
  14:	c4 c3 75 38 66 30 02 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+0x30],0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.51
- Reference cycles: 1.29
- UOPS_EXECUTED.THREAD: 8.51
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.03
- UOPS_PORT_0: 1.31
- UOPS_PORT_1: 1.35
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.37
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c4 c3 75 38 56 10 02 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+0x10],0x2
   d:	c4 c3 75 38 5e 20 02 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+0x20],0x2
  14:	c4 c3 75 38 66 30 02 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+0x30],0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 1.37
- Reference cycles: 1.06
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.09
- UOPS_MS: 0.03
- UOPS_PORT_0: 1.33
- UOPS_PORT_1: 1.34
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.34
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c4 c3 75 38 56 10 02 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+0x10],0x2
   d:	c4 c3 75 38 5e 20 02 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+0x20],0x2
  14:	c4 c3 75 38 66 30 02 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+0x30],0x2
  1b:	c4 c3 75 38 6e 40 02 	vinserti128 ymm5,ymm1,XMMWORD PTR [r14+0x40],0x2
  22:	c4 c3 75 38 76 50 02 	vinserti128 ymm6,ymm1,XMMWORD PTR [r14+0x50],0x2
  29:	c4 c3 75 38 7e 60 02 	vinserti128 ymm7,ymm1,XMMWORD PTR [r14+0x60],0x2
  30:	c4 43 75 38 46 70 02 	vinserti128 ymm8,ymm1,XMMWORD PTR [r14+0x70],0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 7.66
- Reference cycles: 5.76
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 15.99
- UOPS_MITE: 15.93
- UOPS_MS: 0.56
- UOPS_PORT_0: 2.52
- UOPS_PORT_1: 2.55
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 2.97
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.98

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c4 c3 75 38 56 10 02 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+0x10],0x2
   d:	c4 c3 75 38 5e 20 02 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+0x20],0x2
  14:	c4 c3 75 38 66 30 02 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+0x30],0x2
  1b:	c4 c3 75 38 6e 40 02 	vinserti128 ymm5,ymm1,XMMWORD PTR [r14+0x40],0x2
  22:	c4 c3 75 38 76 50 02 	vinserti128 ymm6,ymm1,XMMWORD PTR [r14+0x50],0x2
  29:	c4 c3 75 38 7e 60 02 	vinserti128 ymm7,ymm1,XMMWORD PTR [r14+0x60],0x2
  30:	c4 43 75 38 46 70 02 	vinserti128 ymm8,ymm1,XMMWORD PTR [r14+0x70],0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 3.03
- Reference cycles: 2.53
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.06
- UOPS_PORT_0: 2.61
- UOPS_PORT_1: 2.69
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 2.73
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c4 c3 75 38 56 10 02 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+0x10],0x2
   d:	c4 c3 75 38 5e 20 02 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+0x20],0x2
  14:	c4 c3 75 38 66 30 02 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+0x30],0x2
  1b:	c4 c3 75 38 6e 40 02 	vinserti128 ymm5,ymm1,XMMWORD PTR [r14+0x40],0x2
  22:	c4 c3 75 38 76 50 02 	vinserti128 ymm6,ymm1,XMMWORD PTR [r14+0x50],0x2
  29:	c4 c3 75 38 7e 60 02 	vinserti128 ymm7,ymm1,XMMWORD PTR [r14+0x60],0x2
  30:	c4 43 75 38 46 70 02 	vinserti128 ymm8,ymm1,XMMWORD PTR [r14+0x70],0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 2.74
- Reference cycles: 2.11
- UOPS_EXECUTED.THREAD: 16.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.15
- UOPS_MS: 0.05
- UOPS_PORT_0: 2.66
- UOPS_PORT_1: 2.68
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 2.68
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 12 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c4 c3 75 38 56 10 02 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+0x10],0x2
   d:	c4 c3 75 38 5e 20 02 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+0x20],0x2
  14:	c4 c3 75 38 66 30 02 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+0x30],0x2
  1b:	c4 c3 75 38 6e 40 02 	vinserti128 ymm5,ymm1,XMMWORD PTR [r14+0x40],0x2
  22:	c4 c3 75 38 76 50 02 	vinserti128 ymm6,ymm1,XMMWORD PTR [r14+0x50],0x2
  29:	c4 c3 75 38 7e 60 02 	vinserti128 ymm7,ymm1,XMMWORD PTR [r14+0x60],0x2
  30:	c4 43 75 38 46 70 02 	vinserti128 ymm8,ymm1,XMMWORD PTR [r14+0x70],0x2
  37:	c4 43 75 38 8e 80 00 	vinserti128 ymm9,ymm1,XMMWORD PTR [r14+0x80],0x2
  3e:	00 00 02 
  41:	c4 43 75 38 96 90 00 	vinserti128 ymm10,ymm1,XMMWORD PTR [r14+0x90],0x2
  48:	00 00 02 
  4b:	c4 43 75 38 9e a0 00 	vinserti128 ymm11,ymm1,XMMWORD PTR [r14+0xa0],0x2
  52:	00 00 02 
  55:	c4 43 75 38 a6 b0 00 	vinserti128 ymm12,ymm1,XMMWORD PTR [r14+0xb0],0x2
  5c:	00 00 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 11.99
- Reference cycles: 9.28
- UOPS_EXECUTED.THREAD: 24.0
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 24.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.75
- UOPS_PORT_1: 3.75
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.5
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 12.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 12.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c4 c3 75 38 56 10 02 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+0x10],0x2
   d:	c4 c3 75 38 5e 20 02 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+0x20],0x2
  14:	c4 c3 75 38 66 30 02 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+0x30],0x2
  1b:	c4 c3 75 38 6e 40 02 	vinserti128 ymm5,ymm1,XMMWORD PTR [r14+0x40],0x2
  22:	c4 c3 75 38 76 50 02 	vinserti128 ymm6,ymm1,XMMWORD PTR [r14+0x50],0x2
  29:	c4 c3 75 38 7e 60 02 	vinserti128 ymm7,ymm1,XMMWORD PTR [r14+0x60],0x2
  30:	c4 43 75 38 46 70 02 	vinserti128 ymm8,ymm1,XMMWORD PTR [r14+0x70],0x2
  37:	c4 43 75 38 8e 80 00 	vinserti128 ymm9,ymm1,XMMWORD PTR [r14+0x80],0x2
  3e:	00 00 02 
  41:	c4 43 75 38 96 90 00 	vinserti128 ymm10,ymm1,XMMWORD PTR [r14+0x90],0x2
  48:	00 00 02 
  4b:	c4 43 75 38 9e a0 00 	vinserti128 ymm11,ymm1,XMMWORD PTR [r14+0xa0],0x2
  52:	00 00 02 
  55:	c4 43 75 38 a6 b0 00 	vinserti128 ymm12,ymm1,XMMWORD PTR [r14+0xb0],0x2
  5c:	00 00 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 4.29
- Reference cycles: 3.6
- UOPS_EXECUTED.THREAD: 25.01
- RETIRE_SLOTS: 25.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.03
- UOPS_PORT_0: 3.95
- UOPS_PORT_1: 4.02
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.09
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 12.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c4 c3 75 38 56 10 02 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+0x10],0x2
   d:	c4 c3 75 38 5e 20 02 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+0x20],0x2
  14:	c4 c3 75 38 66 30 02 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+0x30],0x2
  1b:	c4 c3 75 38 6e 40 02 	vinserti128 ymm5,ymm1,XMMWORD PTR [r14+0x40],0x2
  22:	c4 c3 75 38 76 50 02 	vinserti128 ymm6,ymm1,XMMWORD PTR [r14+0x50],0x2
  29:	c4 c3 75 38 7e 60 02 	vinserti128 ymm7,ymm1,XMMWORD PTR [r14+0x60],0x2
  30:	c4 43 75 38 46 70 02 	vinserti128 ymm8,ymm1,XMMWORD PTR [r14+0x70],0x2
  37:	c4 43 75 38 8e 80 00 	vinserti128 ymm9,ymm1,XMMWORD PTR [r14+0x80],0x2
  3e:	00 00 02 
  41:	c4 43 75 38 96 90 00 	vinserti128 ymm10,ymm1,XMMWORD PTR [r14+0x90],0x2
  48:	00 00 02 
  4b:	c4 43 75 38 9e a0 00 	vinserti128 ymm11,ymm1,XMMWORD PTR [r14+0xa0],0x2
  52:	00 00 02 
  55:	c4 43 75 38 a6 b0 00 	vinserti128 ymm12,ymm1,XMMWORD PTR [r14+0xb0],0x2
  5c:	00 00 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 4.09
- Reference cycles: 3.17
- UOPS_EXECUTED.THREAD: 24.1
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.22
- UOPS_MS: 0.05
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.01
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.02
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 12.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.12

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.86
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.31
- UOPS_PORT_1: 0.31
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.38
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.97
- Reference cycles: 0.74
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 2.98
- UOPS_MS: 0.11
- UOPS_PORT_0: 0.31
- UOPS_PORT_1: 0.32
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.37
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 0.77
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 3.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.31
- UOPS_PORT_1: 0.31
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.38
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.0
- Reference cycles: 0.83
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.31
- UOPS_PORT_1: 0.32
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.37
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.0
- Reference cycles: 0.77
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 5.97
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.44
- UOPS_PORT_1: 0.44
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.12
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 5 NOPs

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop
   b:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 2.0
- Reference cycles: 1.5
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.25
- UOPS_PORT_1: 0.38
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.37
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.51
- Reference cycles: 0.43
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.41
- UOPS_PORT_1: 0.42
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.42
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.51
- Reference cycles: 0.39
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.41
- UOPS_PORT_1: 0.42
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.42
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	c4 83 75 38 54 2e 10 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   e:	02 
   f:	c4 83 75 38 5c 2e 20 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  16:	02 
  17:	c4 83 75 38 64 2e 30 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.88
- UOPS_EXECUTED.THREAD: 8.01
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 7.84
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.26
- UOPS_PORT_1: 1.26
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.5
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	c4 83 75 38 54 2e 10 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   e:	02 
   f:	c4 83 75 38 5c 2e 20 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  16:	02 
  17:	c4 83 75 38 64 2e 30 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.52
- Reference cycles: 1.3
- UOPS_EXECUTED.THREAD: 8.51
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.03
- UOPS_PORT_0: 1.31
- UOPS_PORT_1: 1.34
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.37
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	c4 83 75 38 54 2e 10 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   e:	02 
   f:	c4 83 75 38 5c 2e 20 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  16:	02 
  17:	c4 83 75 38 64 2e 30 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 1.37
- Reference cycles: 1.06
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.03
- UOPS_PORT_0: 1.33
- UOPS_PORT_1: 1.34
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.34
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	c4 83 75 38 54 2e 10 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   e:	02 
   f:	c4 83 75 38 5c 2e 20 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  16:	02 
  17:	c4 83 75 38 64 2e 30 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  1e:	02 
  1f:	c4 83 75 38 6c 2e 40 	vinserti128 ymm5,ymm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  26:	02 
  27:	c4 83 75 38 74 2e 50 	vinserti128 ymm6,ymm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  2e:	02 
  2f:	c4 83 75 38 7c 2e 60 	vinserti128 ymm7,ymm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  36:	02 
  37:	c4 03 75 38 44 2e 70 	vinserti128 ymm8,ymm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  3e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 5.92
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.5
- UOPS_PORT_1: 2.51
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	c4 83 75 38 54 2e 10 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   e:	02 
   f:	c4 83 75 38 5c 2e 20 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  16:	02 
  17:	c4 83 75 38 64 2e 30 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  1e:	02 
  1f:	c4 83 75 38 6c 2e 40 	vinserti128 ymm5,ymm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  26:	02 
  27:	c4 83 75 38 74 2e 50 	vinserti128 ymm6,ymm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  2e:	02 
  2f:	c4 83 75 38 7c 2e 60 	vinserti128 ymm7,ymm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  36:	02 
  37:	c4 03 75 38 44 2e 70 	vinserti128 ymm8,ymm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  3e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 3.03
- Reference cycles: 2.56
- UOPS_EXECUTED.THREAD: 17.02
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.06
- UOPS_PORT_0: 2.61
- UOPS_PORT_1: 2.69
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 2.73
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	c4 83 75 38 54 2e 10 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   e:	02 
   f:	c4 83 75 38 5c 2e 20 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  16:	02 
  17:	c4 83 75 38 64 2e 30 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  1e:	02 
  1f:	c4 83 75 38 6c 2e 40 	vinserti128 ymm5,ymm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  26:	02 
  27:	c4 83 75 38 74 2e 50 	vinserti128 ymm6,ymm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  2e:	02 
  2f:	c4 83 75 38 7c 2e 60 	vinserti128 ymm7,ymm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  36:	02 
  37:	c4 03 75 38 44 2e 70 	vinserti128 ymm8,ymm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  3e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 2.73
- Reference cycles: 2.11
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.05
- UOPS_PORT_0: 2.66
- UOPS_PORT_1: 2.68
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 2.68
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 12 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	c4 83 75 38 54 2e 10 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   e:	02 
   f:	c4 83 75 38 5c 2e 20 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  16:	02 
  17:	c4 83 75 38 64 2e 30 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  1e:	02 
  1f:	c4 83 75 38 6c 2e 40 	vinserti128 ymm5,ymm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  26:	02 
  27:	c4 83 75 38 74 2e 50 	vinserti128 ymm6,ymm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  2e:	02 
  2f:	c4 83 75 38 7c 2e 60 	vinserti128 ymm7,ymm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  36:	02 
  37:	c4 03 75 38 44 2e 70 	vinserti128 ymm8,ymm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  3e:	02 
  3f:	c4 03 75 38 8c 2e 80 	vinserti128 ymm9,ymm1,XMMWORD PTR [r14+r13*1+0x80],0x2
  46:	00 00 00 02 
  4a:	c4 03 75 38 94 2e 90 	vinserti128 ymm10,ymm1,XMMWORD PTR [r14+r13*1+0x90],0x2
  51:	00 00 00 02 
  55:	c4 03 75 38 9c 2e a0 	vinserti128 ymm11,ymm1,XMMWORD PTR [r14+r13*1+0xa0],0x2
  5c:	00 00 00 02 
  60:	c4 03 75 38 a4 2e b0 	vinserti128 ymm12,ymm1,XMMWORD PTR [r14+r13*1+0xb0],0x2
  67:	00 00 00 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 11.66
- Reference cycles: 8.64
- UOPS_EXECUTED.THREAD: 23.94
- RETIRE_SLOTS: 23.99
- UOPS_MITE: 23.9
- UOPS_MS: 0.56
- UOPS_PORT_0: 3.77
- UOPS_PORT_1: 3.79
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.47
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 12.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 11.95

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	c4 83 75 38 54 2e 10 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   e:	02 
   f:	c4 83 75 38 5c 2e 20 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  16:	02 
  17:	c4 83 75 38 64 2e 30 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  1e:	02 
  1f:	c4 83 75 38 6c 2e 40 	vinserti128 ymm5,ymm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  26:	02 
  27:	c4 83 75 38 74 2e 50 	vinserti128 ymm6,ymm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  2e:	02 
  2f:	c4 83 75 38 7c 2e 60 	vinserti128 ymm7,ymm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  36:	02 
  37:	c4 03 75 38 44 2e 70 	vinserti128 ymm8,ymm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  3e:	02 
  3f:	c4 03 75 38 8c 2e 80 	vinserti128 ymm9,ymm1,XMMWORD PTR [r14+r13*1+0x80],0x2
  46:	00 00 00 02 
  4a:	c4 03 75 38 94 2e 90 	vinserti128 ymm10,ymm1,XMMWORD PTR [r14+r13*1+0x90],0x2
  51:	00 00 00 02 
  55:	c4 03 75 38 9c 2e a0 	vinserti128 ymm11,ymm1,XMMWORD PTR [r14+r13*1+0xa0],0x2
  5c:	00 00 00 02 
  60:	c4 03 75 38 a4 2e b0 	vinserti128 ymm12,ymm1,XMMWORD PTR [r14+r13*1+0xb0],0x2
  67:	00 00 00 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 4.35
- Reference cycles: 3.66
- UOPS_EXECUTED.THREAD: 25.01
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.05
- UOPS_PORT_0: 3.95
- UOPS_PORT_1: 4.02
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.09
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 12.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	c4 83 75 38 54 2e 10 	vinserti128 ymm2,ymm1,XMMWORD PTR [r14+r13*1+0x10],0x2
   e:	02 
   f:	c4 83 75 38 5c 2e 20 	vinserti128 ymm3,ymm1,XMMWORD PTR [r14+r13*1+0x20],0x2
  16:	02 
  17:	c4 83 75 38 64 2e 30 	vinserti128 ymm4,ymm1,XMMWORD PTR [r14+r13*1+0x30],0x2
  1e:	02 
  1f:	c4 83 75 38 6c 2e 40 	vinserti128 ymm5,ymm1,XMMWORD PTR [r14+r13*1+0x40],0x2
  26:	02 
  27:	c4 83 75 38 74 2e 50 	vinserti128 ymm6,ymm1,XMMWORD PTR [r14+r13*1+0x50],0x2
  2e:	02 
  2f:	c4 83 75 38 7c 2e 60 	vinserti128 ymm7,ymm1,XMMWORD PTR [r14+r13*1+0x60],0x2
  36:	02 
  37:	c4 03 75 38 44 2e 70 	vinserti128 ymm8,ymm1,XMMWORD PTR [r14+r13*1+0x70],0x2
  3e:	02 
  3f:	c4 03 75 38 8c 2e 80 	vinserti128 ymm9,ymm1,XMMWORD PTR [r14+r13*1+0x80],0x2
  46:	00 00 00 02 
  4a:	c4 03 75 38 94 2e 90 	vinserti128 ymm10,ymm1,XMMWORD PTR [r14+r13*1+0x90],0x2
  51:	00 00 00 02 
  55:	c4 03 75 38 9c 2e a0 	vinserti128 ymm11,ymm1,XMMWORD PTR [r14+r13*1+0xa0],0x2
  5c:	00 00 00 02 
  60:	c4 03 75 38 a4 2e b0 	vinserti128 ymm12,ymm1,XMMWORD PTR [r14+r13*1+0xb0],0x2
  67:	00 00 00 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 4.09
- Reference cycles: 3.17
- UOPS_EXECUTED.THREAD: 24.1
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.23
- UOPS_MS: 0.05
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.01
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.02
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 12.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.12

VINSERTI128 (YMM, YMM, M128, I8) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With unroll_count=500, no inner loop, and 5 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 12 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With unroll_count=500, no inner loop, and 5 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 12 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10