VFMADD132PS (ZMM, ZMM, ZMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f2 75 48 98 c2    	vfmadd132ps zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.19

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f2 75 48 98 c2    	vfmadd132ps zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f2 75 48 98 c2    	vfmadd132ps zmm0,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.0
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f2 75 48 98 c2    	vfmadd132ps zmm0,zmm1,zmm2
   6:	62 f2 75 48 98 da    	vfmadd132ps zmm3,zmm1,zmm2
   c:	62 f2 75 48 98 e2    	vfmadd132ps zmm4,zmm1,zmm2
  12:	62 f2 75 48 98 ea    	vfmadd132ps zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.2
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.72

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f2 75 48 98 c2    	vfmadd132ps zmm0,zmm1,zmm2
   6:	62 f2 75 48 98 da    	vfmadd132ps zmm3,zmm1,zmm2
   c:	62 f2 75 48 98 e2    	vfmadd132ps zmm4,zmm1,zmm2
  12:	62 f2 75 48 98 ea    	vfmadd132ps zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.02
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f2 75 48 98 c2    	vfmadd132ps zmm0,zmm1,zmm2
   6:	62 f2 75 48 98 da    	vfmadd132ps zmm3,zmm1,zmm2
   c:	62 f2 75 48 98 e2    	vfmadd132ps zmm4,zmm1,zmm2
  12:	62 f2 75 48 98 ea    	vfmadd132ps zmm5,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 3.02
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.02
- UOPS_MS: 0.01
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 75 48 98 c2    	vfmadd132ps zmm0,zmm1,zmm2
   6:	62 f2 75 48 98 da    	vfmadd132ps zmm3,zmm1,zmm2
   c:	62 f2 75 48 98 e2    	vfmadd132ps zmm4,zmm1,zmm2
  12:	62 f2 75 48 98 ea    	vfmadd132ps zmm5,zmm1,zmm2
  18:	62 f2 75 48 98 f2    	vfmadd132ps zmm6,zmm1,zmm2
  1e:	62 f2 75 48 98 fa    	vfmadd132ps zmm7,zmm1,zmm2
  24:	62 72 75 48 98 c2    	vfmadd132ps zmm8,zmm1,zmm2
  2a:	62 72 75 48 98 ca    	vfmadd132ps zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 7.99
- Reference cycles: 5.6
- UOPS_EXECUTED.THREAD: 7.98
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.45

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 75 48 98 c2    	vfmadd132ps zmm0,zmm1,zmm2
   6:	62 f2 75 48 98 da    	vfmadd132ps zmm3,zmm1,zmm2
   c:	62 f2 75 48 98 e2    	vfmadd132ps zmm4,zmm1,zmm2
  12:	62 f2 75 48 98 ea    	vfmadd132ps zmm5,zmm1,zmm2
  18:	62 f2 75 48 98 f2    	vfmadd132ps zmm6,zmm1,zmm2
  1e:	62 f2 75 48 98 fa    	vfmadd132ps zmm7,zmm1,zmm2
  24:	62 72 75 48 98 c2    	vfmadd132ps zmm8,zmm1,zmm2
  2a:	62 72 75 48 98 ca    	vfmadd132ps zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 6.0
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: -0.01
- UOPS_MS: 0.03
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 75 48 98 c2    	vfmadd132ps zmm0,zmm1,zmm2
   6:	62 f2 75 48 98 da    	vfmadd132ps zmm3,zmm1,zmm2
   c:	62 f2 75 48 98 e2    	vfmadd132ps zmm4,zmm1,zmm2
  12:	62 f2 75 48 98 ea    	vfmadd132ps zmm5,zmm1,zmm2
  18:	62 f2 75 48 98 f2    	vfmadd132ps zmm6,zmm1,zmm2
  1e:	62 f2 75 48 98 fa    	vfmadd132ps zmm7,zmm1,zmm2
  24:	62 72 75 48 98 c2    	vfmadd132ps zmm8,zmm1,zmm2
  2a:	62 72 75 48 98 ca    	vfmadd132ps zmm9,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 6.03
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.11
- UOPS_MITE: 0.04
- UOPS_MS: 0.03
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f2 75 48 98 c2    	vfmadd132ps zmm0,zmm1,zmm2
   6:	62 f2 75 48 98 da    	vfmadd132ps zmm3,zmm1,zmm2
   c:	62 f2 75 48 98 e2    	vfmadd132ps zmm4,zmm1,zmm2
  12:	62 f2 75 48 98 ea    	vfmadd132ps zmm5,zmm1,zmm2
  18:	62 f2 75 48 98 f2    	vfmadd132ps zmm6,zmm1,zmm2
  1e:	62 f2 75 48 98 fa    	vfmadd132ps zmm7,zmm1,zmm2
  24:	62 72 75 48 98 c2    	vfmadd132ps zmm8,zmm1,zmm2
  2a:	62 72 75 48 98 ca    	vfmadd132ps zmm9,zmm1,zmm2
  30:	62 72 75 48 98 d2    	vfmadd132ps zmm10,zmm1,zmm2
  36:	62 72 75 48 98 da    	vfmadd132ps zmm11,zmm1,zmm2
  3c:	62 72 75 48 98 e2    	vfmadd132ps zmm12,zmm1,zmm2
  42:	62 e2 75 48 98 c2    	vfmadd132ps zmm16,zmm1,zmm2
  48:	62 e2 75 48 98 ca    	vfmadd132ps zmm17,zmm1,zmm2
  4e:	62 e2 75 48 98 d2    	vfmadd132ps zmm18,zmm1,zmm2
  54:	62 e2 75 48 98 da    	vfmadd132ps zmm19,zmm1,zmm2
  5a:	62 e2 75 48 98 e2    	vfmadd132ps zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14];
VMOVUPD ZMM19, [R14];
VMOVUPD ZMM20, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 12.16
- UOPS_EXECUTED.THREAD: 16.03
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 15.52
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.88

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f2 75 48 98 c2    	vfmadd132ps zmm0,zmm1,zmm2
   6:	62 f2 75 48 98 da    	vfmadd132ps zmm3,zmm1,zmm2
   c:	62 f2 75 48 98 e2    	vfmadd132ps zmm4,zmm1,zmm2
  12:	62 f2 75 48 98 ea    	vfmadd132ps zmm5,zmm1,zmm2
  18:	62 f2 75 48 98 f2    	vfmadd132ps zmm6,zmm1,zmm2
  1e:	62 f2 75 48 98 fa    	vfmadd132ps zmm7,zmm1,zmm2
  24:	62 72 75 48 98 c2    	vfmadd132ps zmm8,zmm1,zmm2
  2a:	62 72 75 48 98 ca    	vfmadd132ps zmm9,zmm1,zmm2
  30:	62 72 75 48 98 d2    	vfmadd132ps zmm10,zmm1,zmm2
  36:	62 72 75 48 98 da    	vfmadd132ps zmm11,zmm1,zmm2
  3c:	62 72 75 48 98 e2    	vfmadd132ps zmm12,zmm1,zmm2
  42:	62 e2 75 48 98 c2    	vfmadd132ps zmm16,zmm1,zmm2
  48:	62 e2 75 48 98 ca    	vfmadd132ps zmm17,zmm1,zmm2
  4e:	62 e2 75 48 98 d2    	vfmadd132ps zmm18,zmm1,zmm2
  54:	62 e2 75 48 98 da    	vfmadd132ps zmm19,zmm1,zmm2
  5a:	62 e2 75 48 98 e2    	vfmadd132ps zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14];
VMOVUPD ZMM19, [R14];
VMOVUPD ZMM20, [R14]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 12.02
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.01
- UOPS_MITE: 0.0
- UOPS_MS: 0.03
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f2 75 48 98 c2    	vfmadd132ps zmm0,zmm1,zmm2
   6:	62 f2 75 48 98 da    	vfmadd132ps zmm3,zmm1,zmm2
   c:	62 f2 75 48 98 e2    	vfmadd132ps zmm4,zmm1,zmm2
  12:	62 f2 75 48 98 ea    	vfmadd132ps zmm5,zmm1,zmm2
  18:	62 f2 75 48 98 f2    	vfmadd132ps zmm6,zmm1,zmm2
  1e:	62 f2 75 48 98 fa    	vfmadd132ps zmm7,zmm1,zmm2
  24:	62 72 75 48 98 c2    	vfmadd132ps zmm8,zmm1,zmm2
  2a:	62 72 75 48 98 ca    	vfmadd132ps zmm9,zmm1,zmm2
  30:	62 72 75 48 98 d2    	vfmadd132ps zmm10,zmm1,zmm2
  36:	62 72 75 48 98 da    	vfmadd132ps zmm11,zmm1,zmm2
  3c:	62 72 75 48 98 e2    	vfmadd132ps zmm12,zmm1,zmm2
  42:	62 e2 75 48 98 c2    	vfmadd132ps zmm16,zmm1,zmm2
  48:	62 e2 75 48 98 ca    	vfmadd132ps zmm17,zmm1,zmm2
  4e:	62 e2 75 48 98 d2    	vfmadd132ps zmm18,zmm1,zmm2
  54:	62 e2 75 48 98 da    	vfmadd132ps zmm19,zmm1,zmm2
  5a:	62 e2 75 48 98 e2    	vfmadd132ps zmm20,zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM3, [R14];
VMOVUPD ZMM4, [R14];
VMOVUPD ZMM5, [R14];
VMOVUPD ZMM6, [R14];
VMOVUPD ZMM7, [R14];
VMOVUPD ZMM8, [R14];
VMOVUPD ZMM9, [R14];
VMOVUPD ZMM10, [R14];
VMOVUPD ZMM11, [R14];
VMOVUPD ZMM12, [R14];
VMOVUPD ZMM16, [R14];
VMOVUPD ZMM17, [R14];
VMOVUPD ZMM18, [R14];
VMOVUPD ZMM19, [R14];
VMOVUPD ZMM20, [R14]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.01
- Reference cycles: 12.06
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.12
- UOPS_MS: 0.04
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With the same register for for different operands

With unroll_count=500 and no inner loop

Code:

   0:	62 f2 7d 48 98 c0    	vfmadd132ps zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.94
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 0.96
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.19

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f2 7d 48 98 c0    	vfmadd132ps zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 f2 7d 48 98 c0    	vfmadd132ps zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.0
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

VFMADD132PS (ZMM, ZMM, ZMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100