VDPBF16PS (ZMM, ZMM, ZMM) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 8.0
  • Reference cycles: 6.02
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 8.0
  • Reference cycles: 6.11
  • UOPS_EXECUTED.THREAD: 3.99
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 5.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.01

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	90                   	nop
     7:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 8.0
  • Reference cycles: 6.05
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 6.0
  • UOPS_MITE: 6.03
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.02

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 8.0
  • Reference cycles: 6.05
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 7.0
  • UOPS_MITE: 6.99
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 8.0
  • Reference cycles: 6.02
  • UOPS_EXECUTED.THREAD: 4.1
  • RETIRE_SLOTS: 4.1
  • UOPS_MITE: 4.11
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (long NOPs)

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
     d:	0f 1f 84 00 00 00 00 
    14:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2

• Show nanoBench command
• Results:
  • Instructions retired: 2.2
  • Core cycles: 8.0
  • Reference cycles: 6.02
  • UOPS_EXECUTED.THREAD: 4.1
  • RETIRE_SLOTS: 5.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 8.0
  • Reference cycles: 6.02
  • UOPS_EXECUTED.THREAD: 4.01
  • RETIRE_SLOTS: 4.01
  • UOPS_MITE: 4.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (long NOPs)

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
     d:	0f 1f 84 00 00 00 00 
    14:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2

• Show nanoBench command
• Results:
  • Instructions retired: 2.02
  • Core cycles: 8.0
  • Reference cycles: 6.02
  • UOPS_EXECUTED.THREAD: 4.01
  • RETIRE_SLOTS: 5.01
  • UOPS_MITE: 0.05
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=200 and no inner loop

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 8.0
  • Reference cycles: 6.0
  • UOPS_EXECUTED.THREAD: 15.99
  • RETIRE_SLOTS: 16.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 8.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 8.01
  • Reference cycles: 6.01
  • UOPS_EXECUTED.THREAD: 16.5
  • RETIRE_SLOTS: 16.5
  • UOPS_MITE: 2.08
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 8.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With loop_count=1000, unroll_count=2, and padding (long NOPs)

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
    18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    1f:	0f 1f 84 00 00 00 00 
    26:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 6.0
  • Core cycles: 8.01
  • Reference cycles: 6.0
  • UOPS_EXECUTED.THREAD: 16.5
  • RETIRE_SLOTS: 17.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 8.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 8.01
  • Reference cycles: 6.02
  • UOPS_EXECUTED.THREAD: 16.05
  • RETIRE_SLOTS: 16.05
  • UOPS_MITE: 16.03
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 8.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 3.99

With loop_count=100, unroll_count=20, and padding (long NOPs)

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
    18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    1f:	0f 1f 84 00 00 00 00 
    26:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 5.1
  • Core cycles: 8.01
  • Reference cycles: 6.03
  • UOPS_EXECUTED.THREAD: 16.05
  • RETIRE_SLOTS: 17.05
  • UOPS_MITE: 0.16
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 8.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.04

With unroll_count=100 and no inner loop

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
    18:	62 f2 76 48 52 f2    	vdpbf16ps zmm6,zmm1,zmm2
    1e:	62 f2 76 48 52 fa    	vdpbf16ps zmm7,zmm1,zmm2
    24:	62 72 76 48 52 c2    	vdpbf16ps zmm8,zmm1,zmm2
    2a:	62 72 76 48 52 ca    	vdpbf16ps zmm9,zmm1,zmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14];
  VMOVUPD ZMM6, [R14];
  VMOVUPD ZMM7, [R14];
  VMOVUPD ZMM8, [R14];
  VMOVUPD ZMM9, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 16.0
  • Reference cycles: 11.84
  • UOPS_EXECUTED.THREAD: 31.99
  • RETIRE_SLOTS: 32.0
  • UOPS_MITE: 32.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 16.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 16.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
    18:	62 f2 76 48 52 f2    	vdpbf16ps zmm6,zmm1,zmm2
    1e:	62 f2 76 48 52 fa    	vdpbf16ps zmm7,zmm1,zmm2
    24:	62 72 76 48 52 c2    	vdpbf16ps zmm8,zmm1,zmm2
    2a:	62 72 76 48 52 ca    	vdpbf16ps zmm9,zmm1,zmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14];
  VMOVUPD ZMM6, [R14];
  VMOVUPD ZMM7, [R14];
  VMOVUPD ZMM8, [R14];
  VMOVUPD ZMM9, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 16.01
  • Reference cycles: 12.02
  • UOPS_EXECUTED.THREAD: 33.0
  • RETIRE_SLOTS: 33.0
  • UOPS_MITE: 4.9
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 16.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 16.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.14

With loop_count=1000, unroll_count=1, and padding (long NOPs)

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
    18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    1f:	0f 1f 84 00 00 00 00 
    26:	00 
    27:	62 f2 76 48 52 f2    	vdpbf16ps zmm6,zmm1,zmm2
    2d:	62 f2 76 48 52 fa    	vdpbf16ps zmm7,zmm1,zmm2
    33:	62 72 76 48 52 c2    	vdpbf16ps zmm8,zmm1,zmm2
    39:	62 72 76 48 52 ca    	vdpbf16ps zmm9,zmm1,zmm2
    3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    46:	0f 1f 84 00 00 00 00 
    4d:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14];
  VMOVUPD ZMM6, [R14];
  VMOVUPD ZMM7, [R14];
  VMOVUPD ZMM8, [R14];
  VMOVUPD ZMM9, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 12.0
  • Core cycles: 16.01
  • Reference cycles: 12.08
  • UOPS_EXECUTED.THREAD: 33.0
  • RETIRE_SLOTS: 35.0
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 16.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 16.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
    18:	62 f2 76 48 52 f2    	vdpbf16ps zmm6,zmm1,zmm2
    1e:	62 f2 76 48 52 fa    	vdpbf16ps zmm7,zmm1,zmm2
    24:	62 72 76 48 52 c2    	vdpbf16ps zmm8,zmm1,zmm2
    2a:	62 72 76 48 52 ca    	vdpbf16ps zmm9,zmm1,zmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14];
  VMOVUPD ZMM6, [R14];
  VMOVUPD ZMM7, [R14];
  VMOVUPD ZMM8, [R14];
  VMOVUPD ZMM9, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 16.01
  • Reference cycles: 12.05
  • UOPS_EXECUTED.THREAD: 32.1
  • RETIRE_SLOTS: 32.1
  • UOPS_MITE: 32.06
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 16.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 16.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 7.99

With loop_count=100, unroll_count=10, and padding (long NOPs)

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
    18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    1f:	0f 1f 84 00 00 00 00 
    26:	00 
    27:	62 f2 76 48 52 f2    	vdpbf16ps zmm6,zmm1,zmm2
    2d:	62 f2 76 48 52 fa    	vdpbf16ps zmm7,zmm1,zmm2
    33:	62 72 76 48 52 c2    	vdpbf16ps zmm8,zmm1,zmm2
    39:	62 72 76 48 52 ca    	vdpbf16ps zmm9,zmm1,zmm2
    3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    46:	0f 1f 84 00 00 00 00 
    4d:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14];
  VMOVUPD ZMM6, [R14];
  VMOVUPD ZMM7, [R14];
  VMOVUPD ZMM8, [R14];
  VMOVUPD ZMM9, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 10.2
  • Core cycles: 16.01
  • Reference cycles: 12.06
  • UOPS_EXECUTED.THREAD: 32.1
  • RETIRE_SLOTS: 34.1
  • UOPS_MITE: 0.31
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 16.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 16.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.07

With unroll_count=100 and no inner loop

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
    18:	62 f2 76 48 52 f2    	vdpbf16ps zmm6,zmm1,zmm2
    1e:	62 f2 76 48 52 fa    	vdpbf16ps zmm7,zmm1,zmm2
    24:	62 72 76 48 52 c2    	vdpbf16ps zmm8,zmm1,zmm2
    2a:	62 72 76 48 52 ca    	vdpbf16ps zmm9,zmm1,zmm2
    30:	62 72 76 48 52 d2    	vdpbf16ps zmm10,zmm1,zmm2
    36:	62 72 76 48 52 da    	vdpbf16ps zmm11,zmm1,zmm2
    3c:	62 72 76 48 52 e2    	vdpbf16ps zmm12,zmm1,zmm2
    42:	62 e2 76 48 52 c2    	vdpbf16ps zmm16,zmm1,zmm2
    48:	62 e2 76 48 52 ca    	vdpbf16ps zmm17,zmm1,zmm2
    4e:	62 e2 76 48 52 d2    	vdpbf16ps zmm18,zmm1,zmm2
    54:	62 e2 76 48 52 da    	vdpbf16ps zmm19,zmm1,zmm2
    5a:	62 e2 76 48 52 e2    	vdpbf16ps zmm20,zmm1,zmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14];
  VMOVUPD ZMM6, [R14];
  VMOVUPD ZMM7, [R14];
  VMOVUPD ZMM8, [R14];
  VMOVUPD ZMM9, [R14];
  VMOVUPD ZMM10, [R14];
  VMOVUPD ZMM11, [R14];
  VMOVUPD ZMM12, [R14];
  VMOVUPD ZMM16, [R14];
  VMOVUPD ZMM17, [R14];
  VMOVUPD ZMM18, [R14];
  VMOVUPD ZMM19, [R14];
  VMOVUPD ZMM20, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 32.0
  • Reference cycles: 24.32
  • UOPS_EXECUTED.THREAD: 63.98
  • RETIRE_SLOTS: 64.0
  • UOPS_MITE: 64.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 32.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 32.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
    18:	62 f2 76 48 52 f2    	vdpbf16ps zmm6,zmm1,zmm2
    1e:	62 f2 76 48 52 fa    	vdpbf16ps zmm7,zmm1,zmm2
    24:	62 72 76 48 52 c2    	vdpbf16ps zmm8,zmm1,zmm2
    2a:	62 72 76 48 52 ca    	vdpbf16ps zmm9,zmm1,zmm2
    30:	62 72 76 48 52 d2    	vdpbf16ps zmm10,zmm1,zmm2
    36:	62 72 76 48 52 da    	vdpbf16ps zmm11,zmm1,zmm2
    3c:	62 72 76 48 52 e2    	vdpbf16ps zmm12,zmm1,zmm2
    42:	62 e2 76 48 52 c2    	vdpbf16ps zmm16,zmm1,zmm2
    48:	62 e2 76 48 52 ca    	vdpbf16ps zmm17,zmm1,zmm2
    4e:	62 e2 76 48 52 d2    	vdpbf16ps zmm18,zmm1,zmm2
    54:	62 e2 76 48 52 da    	vdpbf16ps zmm19,zmm1,zmm2
    5a:	62 e2 76 48 52 e2    	vdpbf16ps zmm20,zmm1,zmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14];
  VMOVUPD ZMM6, [R14];
  VMOVUPD ZMM7, [R14];
  VMOVUPD ZMM8, [R14];
  VMOVUPD ZMM9, [R14];
  VMOVUPD ZMM10, [R14];
  VMOVUPD ZMM11, [R14];
  VMOVUPD ZMM12, [R14];
  VMOVUPD ZMM16, [R14];
  VMOVUPD ZMM17, [R14];
  VMOVUPD ZMM18, [R14];
  VMOVUPD ZMM19, [R14];
  VMOVUPD ZMM20, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 32.01
  • Reference cycles: 24.1
  • UOPS_EXECUTED.THREAD: 65.0
  • RETIRE_SLOTS: 65.01
  • UOPS_MITE: 65.1
  • UOPS_MS: 0.03
  • UOPS_PORT_0: 32.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 32.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
    18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    1f:	0f 1f 84 00 00 00 00 
    26:	00 
    27:	62 f2 76 48 52 f2    	vdpbf16ps zmm6,zmm1,zmm2
    2d:	62 f2 76 48 52 fa    	vdpbf16ps zmm7,zmm1,zmm2
    33:	62 72 76 48 52 c2    	vdpbf16ps zmm8,zmm1,zmm2
    39:	62 72 76 48 52 ca    	vdpbf16ps zmm9,zmm1,zmm2
    3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    46:	0f 1f 84 00 00 00 00 
    4d:	00 
    4e:	62 72 76 48 52 d2    	vdpbf16ps zmm10,zmm1,zmm2
    54:	62 72 76 48 52 da    	vdpbf16ps zmm11,zmm1,zmm2
    5a:	62 72 76 48 52 e2    	vdpbf16ps zmm12,zmm1,zmm2
    60:	62 e2 76 48 52 c2    	vdpbf16ps zmm16,zmm1,zmm2
    66:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    6d:	0f 1f 84 00 00 00 00 
    74:	00 
    75:	62 e2 76 48 52 ca    	vdpbf16ps zmm17,zmm1,zmm2
    7b:	62 e2 76 48 52 d2    	vdpbf16ps zmm18,zmm1,zmm2
    81:	62 e2 76 48 52 da    	vdpbf16ps zmm19,zmm1,zmm2
    87:	62 e2 76 48 52 e2    	vdpbf16ps zmm20,zmm1,zmm2
    8d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    94:	0f 1f 84 00 00 00 00 
    9b:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14];
  VMOVUPD ZMM6, [R14];
  VMOVUPD ZMM7, [R14];
  VMOVUPD ZMM8, [R14];
  VMOVUPD ZMM9, [R14];
  VMOVUPD ZMM10, [R14];
  VMOVUPD ZMM11, [R14];
  VMOVUPD ZMM12, [R14];
  VMOVUPD ZMM16, [R14];
  VMOVUPD ZMM17, [R14];
  VMOVUPD ZMM18, [R14];
  VMOVUPD ZMM19, [R14];
  VMOVUPD ZMM20, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 22.0
  • Core cycles: 32.01
  • Reference cycles: 24.1
  • UOPS_EXECUTED.THREAD: 65.0
  • RETIRE_SLOTS: 69.0
  • UOPS_MITE: 0.11
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 32.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 32.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
    18:	62 f2 76 48 52 f2    	vdpbf16ps zmm6,zmm1,zmm2
    1e:	62 f2 76 48 52 fa    	vdpbf16ps zmm7,zmm1,zmm2
    24:	62 72 76 48 52 c2    	vdpbf16ps zmm8,zmm1,zmm2
    2a:	62 72 76 48 52 ca    	vdpbf16ps zmm9,zmm1,zmm2
    30:	62 72 76 48 52 d2    	vdpbf16ps zmm10,zmm1,zmm2
    36:	62 72 76 48 52 da    	vdpbf16ps zmm11,zmm1,zmm2
    3c:	62 72 76 48 52 e2    	vdpbf16ps zmm12,zmm1,zmm2
    42:	62 e2 76 48 52 c2    	vdpbf16ps zmm16,zmm1,zmm2
    48:	62 e2 76 48 52 ca    	vdpbf16ps zmm17,zmm1,zmm2
    4e:	62 e2 76 48 52 d2    	vdpbf16ps zmm18,zmm1,zmm2
    54:	62 e2 76 48 52 da    	vdpbf16ps zmm19,zmm1,zmm2
    5a:	62 e2 76 48 52 e2    	vdpbf16ps zmm20,zmm1,zmm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14];
  VMOVUPD ZMM6, [R14];
  VMOVUPD ZMM7, [R14];
  VMOVUPD ZMM8, [R14];
  VMOVUPD ZMM9, [R14];
  VMOVUPD ZMM10, [R14];
  VMOVUPD ZMM11, [R14];
  VMOVUPD ZMM12, [R14];
  VMOVUPD ZMM16, [R14];
  VMOVUPD ZMM17, [R14];
  VMOVUPD ZMM18, [R14];
  VMOVUPD ZMM19, [R14];
  VMOVUPD ZMM20, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 32.01
  • Reference cycles: 24.1
  • UOPS_EXECUTED.THREAD: 64.1
  • RETIRE_SLOTS: 64.1
  • UOPS_MITE: 64.08
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 32.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 32.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=100, unroll_count=10, and padding (long NOPs)

• Code:

     0:	62 f2 76 48 52 c2    	vdpbf16ps zmm0,zmm1,zmm2
     6:	62 f2 76 48 52 da    	vdpbf16ps zmm3,zmm1,zmm2
     c:	62 f2 76 48 52 e2    	vdpbf16ps zmm4,zmm1,zmm2
    12:	62 f2 76 48 52 ea    	vdpbf16ps zmm5,zmm1,zmm2
    18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    1f:	0f 1f 84 00 00 00 00 
    26:	00 
    27:	62 f2 76 48 52 f2    	vdpbf16ps zmm6,zmm1,zmm2
    2d:	62 f2 76 48 52 fa    	vdpbf16ps zmm7,zmm1,zmm2
    33:	62 72 76 48 52 c2    	vdpbf16ps zmm8,zmm1,zmm2
    39:	62 72 76 48 52 ca    	vdpbf16ps zmm9,zmm1,zmm2
    3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    46:	0f 1f 84 00 00 00 00 
    4d:	00 
    4e:	62 72 76 48 52 d2    	vdpbf16ps zmm10,zmm1,zmm2
    54:	62 72 76 48 52 da    	vdpbf16ps zmm11,zmm1,zmm2
    5a:	62 72 76 48 52 e2    	vdpbf16ps zmm12,zmm1,zmm2
    60:	62 e2 76 48 52 c2    	vdpbf16ps zmm16,zmm1,zmm2
    66:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    6d:	0f 1f 84 00 00 00 00 
    74:	00 
    75:	62 e2 76 48 52 ca    	vdpbf16ps zmm17,zmm1,zmm2
    7b:	62 e2 76 48 52 d2    	vdpbf16ps zmm18,zmm1,zmm2
    81:	62 e2 76 48 52 da    	vdpbf16ps zmm19,zmm1,zmm2
    87:	62 e2 76 48 52 e2    	vdpbf16ps zmm20,zmm1,zmm2
    8d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    94:	0f 1f 84 00 00 00 00 
    9b:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VMOVUPD ZMM4, [R14];
  VMOVUPD ZMM5, [R14];
  VMOVUPD ZMM6, [R14];
  VMOVUPD ZMM7, [R14];
  VMOVUPD ZMM8, [R14];
  VMOVUPD ZMM9, [R14];
  VMOVUPD ZMM10, [R14];
  VMOVUPD ZMM11, [R14];
  VMOVUPD ZMM12, [R14];
  VMOVUPD ZMM16, [R14];
  VMOVUPD ZMM17, [R14];
  VMOVUPD ZMM18, [R14];
  VMOVUPD ZMM19, [R14];
  VMOVUPD ZMM20, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 20.2
  • Core cycles: 32.01
  • Reference cycles: 24.08
  • UOPS_EXECUTED.THREAD: 64.1
  • RETIRE_SLOTS: 68.1
  • UOPS_MITE: 0.7
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 32.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 32.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.16

With unroll_count=500 and no inner loop

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 8.0
  • Reference cycles: 6.14
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 3.97
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.01

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 8.0
  • Reference cycles: 6.11
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 5.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	90                   	nop
     7:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 8.0
  • Reference cycles: 6.02
  • UOPS_EXECUTED.THREAD: 4.01
  • RETIRE_SLOTS: 6.0
  • UOPS_MITE: 5.99
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 8.0
  • Reference cycles: 6.02
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 7.0
  • UOPS_MITE: 7.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 8.0
  • Reference cycles: 6.02
  • UOPS_EXECUTED.THREAD: 4.1
  • RETIRE_SLOTS: 4.1
  • UOPS_MITE: 4.11
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (long NOPs)

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
     d:	0f 1f 84 00 00 00 00 
    14:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 2.2
  • Core cycles: 8.0
  • Reference cycles: 6.02
  • UOPS_EXECUTED.THREAD: 4.1
  • RETIRE_SLOTS: 5.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 8.0
  • Reference cycles: 6.02
  • UOPS_EXECUTED.THREAD: 4.01
  • RETIRE_SLOTS: 4.01
  • UOPS_MITE: 4.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (long NOPs)

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
     d:	0f 1f 84 00 00 00 00 
    14:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0

• Show nanoBench command
• Results:
  • Instructions retired: 2.02
  • Core cycles: 8.0
  • Reference cycles: 6.02
  • UOPS_EXECUTED.THREAD: 4.01
  • RETIRE_SLOTS: 5.01
  • UOPS_MITE: 0.05
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=200 and no inner loop

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 8.35
  • Reference cycles: 6.4
  • UOPS_EXECUTED.THREAD: 16.0
  • RETIRE_SLOTS: 16.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 8.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 8.34
  • Reference cycles: 6.26
  • UOPS_EXECUTED.THREAD: 16.5
  • RETIRE_SLOTS: 16.5
  • UOPS_MITE: 3.2
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 8.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.44

With loop_count=1000, unroll_count=2, and padding (long NOPs)

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
    18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    1f:	0f 1f 84 00 00 00 00 
    26:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3

• Show nanoBench command
• Results:
  • Instructions retired: 6.0
  • Core cycles: 8.4
  • Reference cycles: 6.33
  • UOPS_EXECUTED.THREAD: 16.5
  • RETIRE_SLOTS: 17.5
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 8.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 8.3
  • Reference cycles: 6.22
  • UOPS_EXECUTED.THREAD: 16.05
  • RETIRE_SLOTS: 16.05
  • UOPS_MITE: 16.03
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 8.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 3.99

With loop_count=100, unroll_count=20, and padding (long NOPs)

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
    18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    1f:	0f 1f 84 00 00 00 00 
    26:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3

• Show nanoBench command
• Results:
  • Instructions retired: 5.1
  • Core cycles: 8.32
  • Reference cycles: 6.24
  • UOPS_EXECUTED.THREAD: 16.05
  • RETIRE_SLOTS: 17.05
  • UOPS_MITE: 0.15
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 8.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 8.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.03

With unroll_count=100 and no inner loop

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
    18:	62 f2 5e 48 52 e4    	vdpbf16ps zmm4,zmm4,zmm4
    1e:	62 f2 56 48 52 ed    	vdpbf16ps zmm5,zmm5,zmm5
    24:	62 f2 4e 48 52 f6    	vdpbf16ps zmm6,zmm6,zmm6
    2a:	62 f2 46 48 52 ff    	vdpbf16ps zmm7,zmm7,zmm7
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3;
  VMOVUPD ZMM4, [R14];
  VXORPS ZMM4, ZMM4, ZMM4;
  VMOVUPD ZMM5, [R14];
  VXORPS ZMM5, ZMM5, ZMM5;
  VMOVUPD ZMM6, [R14];
  VXORPS ZMM6, ZMM6, ZMM6;
  VMOVUPD ZMM7, [R14];
  VXORPS ZMM7, ZMM7, ZMM7

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 16.0
  • Reference cycles: 11.84
  • UOPS_EXECUTED.THREAD: 31.98
  • RETIRE_SLOTS: 32.0
  • UOPS_MITE: 32.48
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 16.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 16.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
    18:	62 f2 5e 48 52 e4    	vdpbf16ps zmm4,zmm4,zmm4
    1e:	62 f2 56 48 52 ed    	vdpbf16ps zmm5,zmm5,zmm5
    24:	62 f2 4e 48 52 f6    	vdpbf16ps zmm6,zmm6,zmm6
    2a:	62 f2 46 48 52 ff    	vdpbf16ps zmm7,zmm7,zmm7
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3;
  VMOVUPD ZMM4, [R14];
  VXORPS ZMM4, ZMM4, ZMM4;
  VMOVUPD ZMM5, [R14];
  VXORPS ZMM5, ZMM5, ZMM5;
  VMOVUPD ZMM6, [R14];
  VXORPS ZMM6, ZMM6, ZMM6;
  VMOVUPD ZMM7, [R14];
  VXORPS ZMM7, ZMM7, ZMM7

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 16.01
  • Reference cycles: 12.0
  • UOPS_EXECUTED.THREAD: 33.0
  • RETIRE_SLOTS: 33.0
  • UOPS_MITE: 3.03
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 16.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 16.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.14

With loop_count=1000, unroll_count=1, and padding (long NOPs)

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
    18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    1f:	0f 1f 84 00 00 00 00 
    26:	00 
    27:	62 f2 5e 48 52 e4    	vdpbf16ps zmm4,zmm4,zmm4
    2d:	62 f2 56 48 52 ed    	vdpbf16ps zmm5,zmm5,zmm5
    33:	62 f2 4e 48 52 f6    	vdpbf16ps zmm6,zmm6,zmm6
    39:	62 f2 46 48 52 ff    	vdpbf16ps zmm7,zmm7,zmm7
    3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    46:	0f 1f 84 00 00 00 00 
    4d:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3;
  VMOVUPD ZMM4, [R14];
  VXORPS ZMM4, ZMM4, ZMM4;
  VMOVUPD ZMM5, [R14];
  VXORPS ZMM5, ZMM5, ZMM5;
  VMOVUPD ZMM6, [R14];
  VXORPS ZMM6, ZMM6, ZMM6;
  VMOVUPD ZMM7, [R14];
  VXORPS ZMM7, ZMM7, ZMM7

• Show nanoBench command
• Results:
  • Instructions retired: 12.0
  • Core cycles: 16.01
  • Reference cycles: 12.06
  • UOPS_EXECUTED.THREAD: 33.0
  • RETIRE_SLOTS: 35.0
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 16.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 16.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
    18:	62 f2 5e 48 52 e4    	vdpbf16ps zmm4,zmm4,zmm4
    1e:	62 f2 56 48 52 ed    	vdpbf16ps zmm5,zmm5,zmm5
    24:	62 f2 4e 48 52 f6    	vdpbf16ps zmm6,zmm6,zmm6
    2a:	62 f2 46 48 52 ff    	vdpbf16ps zmm7,zmm7,zmm7
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3;
  VMOVUPD ZMM4, [R14];
  VXORPS ZMM4, ZMM4, ZMM4;
  VMOVUPD ZMM5, [R14];
  VXORPS ZMM5, ZMM5, ZMM5;
  VMOVUPD ZMM6, [R14];
  VXORPS ZMM6, ZMM6, ZMM6;
  VMOVUPD ZMM7, [R14];
  VXORPS ZMM7, ZMM7, ZMM7

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 16.01
  • Reference cycles: 12.0
  • UOPS_EXECUTED.THREAD: 32.1
  • RETIRE_SLOTS: 32.1
  • UOPS_MITE: 32.06
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 16.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 16.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 7.99

With loop_count=100, unroll_count=10, and padding (long NOPs)

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
    18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    1f:	0f 1f 84 00 00 00 00 
    26:	00 
    27:	62 f2 5e 48 52 e4    	vdpbf16ps zmm4,zmm4,zmm4
    2d:	62 f2 56 48 52 ed    	vdpbf16ps zmm5,zmm5,zmm5
    33:	62 f2 4e 48 52 f6    	vdpbf16ps zmm6,zmm6,zmm6
    39:	62 f2 46 48 52 ff    	vdpbf16ps zmm7,zmm7,zmm7
    3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    46:	0f 1f 84 00 00 00 00 
    4d:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3;
  VMOVUPD ZMM4, [R14];
  VXORPS ZMM4, ZMM4, ZMM4;
  VMOVUPD ZMM5, [R14];
  VXORPS ZMM5, ZMM5, ZMM5;
  VMOVUPD ZMM6, [R14];
  VXORPS ZMM6, ZMM6, ZMM6;
  VMOVUPD ZMM7, [R14];
  VXORPS ZMM7, ZMM7, ZMM7

• Show nanoBench command
• Results:
  • Instructions retired: 10.2
  • Core cycles: 16.01
  • Reference cycles: 12.02
  • UOPS_EXECUTED.THREAD: 32.1
  • RETIRE_SLOTS: 34.1
  • UOPS_MITE: 0.31
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 16.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 16.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.07

With unroll_count=100 and no inner loop

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
    18:	62 f2 5e 48 52 e4    	vdpbf16ps zmm4,zmm4,zmm4
    1e:	62 f2 56 48 52 ed    	vdpbf16ps zmm5,zmm5,zmm5
    24:	62 f2 4e 48 52 f6    	vdpbf16ps zmm6,zmm6,zmm6
    2a:	62 f2 46 48 52 ff    	vdpbf16ps zmm7,zmm7,zmm7
    30:	62 52 3e 48 52 c0    	vdpbf16ps zmm8,zmm8,zmm8
    36:	62 52 36 48 52 c9    	vdpbf16ps zmm9,zmm9,zmm9
    3c:	62 52 2e 48 52 d2    	vdpbf16ps zmm10,zmm10,zmm10
    42:	62 52 26 48 52 db    	vdpbf16ps zmm11,zmm11,zmm11
    48:	62 52 1e 48 52 e4    	vdpbf16ps zmm12,zmm12,zmm12
    4e:	62 a2 7e 40 52 c0    	vdpbf16ps zmm16,zmm16,zmm16
    54:	62 a2 76 40 52 c9    	vdpbf16ps zmm17,zmm17,zmm17
    5a:	62 a2 6e 40 52 d2    	vdpbf16ps zmm18,zmm18,zmm18
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3;
  VMOVUPD ZMM4, [R14];
  VXORPS ZMM4, ZMM4, ZMM4;
  VMOVUPD ZMM5, [R14];
  VXORPS ZMM5, ZMM5, ZMM5;
  VMOVUPD ZMM6, [R14];
  VXORPS ZMM6, ZMM6, ZMM6;
  VMOVUPD ZMM7, [R14];
  VXORPS ZMM7, ZMM7, ZMM7;
  VMOVUPD ZMM8, [R14];
  VXORPS ZMM8, ZMM8, ZMM8;
  VMOVUPD ZMM9, [R14];
  VXORPS ZMM9, ZMM9, ZMM9;
  VMOVUPD ZMM10, [R14];
  VXORPS ZMM10, ZMM10, ZMM10;
  VMOVUPD ZMM11, [R14];
  VXORPS ZMM11, ZMM11, ZMM11;
  VMOVUPD ZMM12, [R14];
  VXORPS ZMM12, ZMM12, ZMM12;
  VMOVUPD ZMM16, [R14];
  VXORPS ZMM16, ZMM16, ZMM16;
  VMOVUPD ZMM17, [R14];
  VXORPS ZMM17, ZMM17, ZMM17;
  VMOVUPD ZMM18, [R14];
  VXORPS ZMM18, ZMM18, ZMM18

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 32.0
  • Reference cycles: 24.0
  • UOPS_EXECUTED.THREAD: 64.02
  • RETIRE_SLOTS: 64.0
  • UOPS_MITE: 64.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 32.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 32.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
    18:	62 f2 5e 48 52 e4    	vdpbf16ps zmm4,zmm4,zmm4
    1e:	62 f2 56 48 52 ed    	vdpbf16ps zmm5,zmm5,zmm5
    24:	62 f2 4e 48 52 f6    	vdpbf16ps zmm6,zmm6,zmm6
    2a:	62 f2 46 48 52 ff    	vdpbf16ps zmm7,zmm7,zmm7
    30:	62 52 3e 48 52 c0    	vdpbf16ps zmm8,zmm8,zmm8
    36:	62 52 36 48 52 c9    	vdpbf16ps zmm9,zmm9,zmm9
    3c:	62 52 2e 48 52 d2    	vdpbf16ps zmm10,zmm10,zmm10
    42:	62 52 26 48 52 db    	vdpbf16ps zmm11,zmm11,zmm11
    48:	62 52 1e 48 52 e4    	vdpbf16ps zmm12,zmm12,zmm12
    4e:	62 a2 7e 40 52 c0    	vdpbf16ps zmm16,zmm16,zmm16
    54:	62 a2 76 40 52 c9    	vdpbf16ps zmm17,zmm17,zmm17
    5a:	62 a2 6e 40 52 d2    	vdpbf16ps zmm18,zmm18,zmm18
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3;
  VMOVUPD ZMM4, [R14];
  VXORPS ZMM4, ZMM4, ZMM4;
  VMOVUPD ZMM5, [R14];
  VXORPS ZMM5, ZMM5, ZMM5;
  VMOVUPD ZMM6, [R14];
  VXORPS ZMM6, ZMM6, ZMM6;
  VMOVUPD ZMM7, [R14];
  VXORPS ZMM7, ZMM7, ZMM7;
  VMOVUPD ZMM8, [R14];
  VXORPS ZMM8, ZMM8, ZMM8;
  VMOVUPD ZMM9, [R14];
  VXORPS ZMM9, ZMM9, ZMM9;
  VMOVUPD ZMM10, [R14];
  VXORPS ZMM10, ZMM10, ZMM10;
  VMOVUPD ZMM11, [R14];
  VXORPS ZMM11, ZMM11, ZMM11;
  VMOVUPD ZMM12, [R14];
  VXORPS ZMM12, ZMM12, ZMM12;
  VMOVUPD ZMM16, [R14];
  VXORPS ZMM16, ZMM16, ZMM16;
  VMOVUPD ZMM17, [R14];
  VXORPS ZMM17, ZMM17, ZMM17;
  VMOVUPD ZMM18, [R14];
  VXORPS ZMM18, ZMM18, ZMM18

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 32.01
  • Reference cycles: 24.08
  • UOPS_EXECUTED.THREAD: 65.0
  • RETIRE_SLOTS: 65.01
  • UOPS_MITE: 65.09
  • UOPS_MS: 0.03
  • UOPS_PORT_0: 32.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 32.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
    18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    1f:	0f 1f 84 00 00 00 00 
    26:	00 
    27:	62 f2 5e 48 52 e4    	vdpbf16ps zmm4,zmm4,zmm4
    2d:	62 f2 56 48 52 ed    	vdpbf16ps zmm5,zmm5,zmm5
    33:	62 f2 4e 48 52 f6    	vdpbf16ps zmm6,zmm6,zmm6
    39:	62 f2 46 48 52 ff    	vdpbf16ps zmm7,zmm7,zmm7
    3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    46:	0f 1f 84 00 00 00 00 
    4d:	00 
    4e:	62 52 3e 48 52 c0    	vdpbf16ps zmm8,zmm8,zmm8
    54:	62 52 36 48 52 c9    	vdpbf16ps zmm9,zmm9,zmm9
    5a:	62 52 2e 48 52 d2    	vdpbf16ps zmm10,zmm10,zmm10
    60:	62 52 26 48 52 db    	vdpbf16ps zmm11,zmm11,zmm11
    66:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    6d:	0f 1f 84 00 00 00 00 
    74:	00 
    75:	62 52 1e 48 52 e4    	vdpbf16ps zmm12,zmm12,zmm12
    7b:	62 a2 7e 40 52 c0    	vdpbf16ps zmm16,zmm16,zmm16
    81:	62 a2 76 40 52 c9    	vdpbf16ps zmm17,zmm17,zmm17
    87:	62 a2 6e 40 52 d2    	vdpbf16ps zmm18,zmm18,zmm18
    8d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    94:	0f 1f 84 00 00 00 00 
    9b:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3;
  VMOVUPD ZMM4, [R14];
  VXORPS ZMM4, ZMM4, ZMM4;
  VMOVUPD ZMM5, [R14];
  VXORPS ZMM5, ZMM5, ZMM5;
  VMOVUPD ZMM6, [R14];
  VXORPS ZMM6, ZMM6, ZMM6;
  VMOVUPD ZMM7, [R14];
  VXORPS ZMM7, ZMM7, ZMM7;
  VMOVUPD ZMM8, [R14];
  VXORPS ZMM8, ZMM8, ZMM8;
  VMOVUPD ZMM9, [R14];
  VXORPS ZMM9, ZMM9, ZMM9;
  VMOVUPD ZMM10, [R14];
  VXORPS ZMM10, ZMM10, ZMM10;
  VMOVUPD ZMM11, [R14];
  VXORPS ZMM11, ZMM11, ZMM11;
  VMOVUPD ZMM12, [R14];
  VXORPS ZMM12, ZMM12, ZMM12;
  VMOVUPD ZMM16, [R14];
  VXORPS ZMM16, ZMM16, ZMM16;
  VMOVUPD ZMM17, [R14];
  VXORPS ZMM17, ZMM17, ZMM17;
  VMOVUPD ZMM18, [R14];
  VXORPS ZMM18, ZMM18, ZMM18

• Show nanoBench command
• Results:
  • Instructions retired: 22.0
  • Core cycles: 32.01
  • Reference cycles: 24.08
  • UOPS_EXECUTED.THREAD: 65.0
  • RETIRE_SLOTS: 69.0
  • UOPS_MITE: 0.07
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 32.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 32.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
    18:	62 f2 5e 48 52 e4    	vdpbf16ps zmm4,zmm4,zmm4
    1e:	62 f2 56 48 52 ed    	vdpbf16ps zmm5,zmm5,zmm5
    24:	62 f2 4e 48 52 f6    	vdpbf16ps zmm6,zmm6,zmm6
    2a:	62 f2 46 48 52 ff    	vdpbf16ps zmm7,zmm7,zmm7
    30:	62 52 3e 48 52 c0    	vdpbf16ps zmm8,zmm8,zmm8
    36:	62 52 36 48 52 c9    	vdpbf16ps zmm9,zmm9,zmm9
    3c:	62 52 2e 48 52 d2    	vdpbf16ps zmm10,zmm10,zmm10
    42:	62 52 26 48 52 db    	vdpbf16ps zmm11,zmm11,zmm11
    48:	62 52 1e 48 52 e4    	vdpbf16ps zmm12,zmm12,zmm12
    4e:	62 a2 7e 40 52 c0    	vdpbf16ps zmm16,zmm16,zmm16
    54:	62 a2 76 40 52 c9    	vdpbf16ps zmm17,zmm17,zmm17
    5a:	62 a2 6e 40 52 d2    	vdpbf16ps zmm18,zmm18,zmm18
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3;
  VMOVUPD ZMM4, [R14];
  VXORPS ZMM4, ZMM4, ZMM4;
  VMOVUPD ZMM5, [R14];
  VXORPS ZMM5, ZMM5, ZMM5;
  VMOVUPD ZMM6, [R14];
  VXORPS ZMM6, ZMM6, ZMM6;
  VMOVUPD ZMM7, [R14];
  VXORPS ZMM7, ZMM7, ZMM7;
  VMOVUPD ZMM8, [R14];
  VXORPS ZMM8, ZMM8, ZMM8;
  VMOVUPD ZMM9, [R14];
  VXORPS ZMM9, ZMM9, ZMM9;
  VMOVUPD ZMM10, [R14];
  VXORPS ZMM10, ZMM10, ZMM10;
  VMOVUPD ZMM11, [R14];
  VXORPS ZMM11, ZMM11, ZMM11;
  VMOVUPD ZMM12, [R14];
  VXORPS ZMM12, ZMM12, ZMM12;
  VMOVUPD ZMM16, [R14];
  VXORPS ZMM16, ZMM16, ZMM16;
  VMOVUPD ZMM17, [R14];
  VXORPS ZMM17, ZMM17, ZMM17;
  VMOVUPD ZMM18, [R14];
  VXORPS ZMM18, ZMM18, ZMM18

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 32.01
  • Reference cycles: 24.1
  • UOPS_EXECUTED.THREAD: 64.1
  • RETIRE_SLOTS: 64.1
  • UOPS_MITE: 64.09
  • UOPS_MS: 0.06
  • UOPS_PORT_0: 32.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 32.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=100, unroll_count=10, and padding (long NOPs)

• Code:

     0:	62 f2 7e 48 52 c0    	vdpbf16ps zmm0,zmm0,zmm0
     6:	62 f2 76 48 52 c9    	vdpbf16ps zmm1,zmm1,zmm1
     c:	62 f2 6e 48 52 d2    	vdpbf16ps zmm2,zmm2,zmm2
    12:	62 f2 66 48 52 db    	vdpbf16ps zmm3,zmm3,zmm3
    18:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    1f:	0f 1f 84 00 00 00 00 
    26:	00 
    27:	62 f2 5e 48 52 e4    	vdpbf16ps zmm4,zmm4,zmm4
    2d:	62 f2 56 48 52 ed    	vdpbf16ps zmm5,zmm5,zmm5
    33:	62 f2 4e 48 52 f6    	vdpbf16ps zmm6,zmm6,zmm6
    39:	62 f2 46 48 52 ff    	vdpbf16ps zmm7,zmm7,zmm7
    3f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    46:	0f 1f 84 00 00 00 00 
    4d:	00 
    4e:	62 52 3e 48 52 c0    	vdpbf16ps zmm8,zmm8,zmm8
    54:	62 52 36 48 52 c9    	vdpbf16ps zmm9,zmm9,zmm9
    5a:	62 52 2e 48 52 d2    	vdpbf16ps zmm10,zmm10,zmm10
    60:	62 52 26 48 52 db    	vdpbf16ps zmm11,zmm11,zmm11
    66:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    6d:	0f 1f 84 00 00 00 00 
    74:	00 
    75:	62 52 1e 48 52 e4    	vdpbf16ps zmm12,zmm12,zmm12
    7b:	62 a2 7e 40 52 c0    	vdpbf16ps zmm16,zmm16,zmm16
    81:	62 a2 76 40 52 c9    	vdpbf16ps zmm17,zmm17,zmm17
    87:	62 a2 6e 40 52 d2    	vdpbf16ps zmm18,zmm18,zmm18
    8d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
    94:	0f 1f 84 00 00 00 00 
    9b:	00 
  

• Init:

  MOV R15, 10000;
  L: VADDPS ZMM0, ZMM1, ZMM1;
  VADDPS ZMM0, ZMM1, ZMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  MOV [R14+32], RAX;
  MOV [R14+40], RAX;
  MOV [R14+48], RAX;
  MOV [R14+56], RAX;
  VMOVUPD ZMM0, [R14];
  VXORPS ZMM0, ZMM0, ZMM0;
  VMOVUPD ZMM1, [R14];
  VXORPS ZMM1, ZMM1, ZMM1;
  VMOVUPD ZMM2, [R14];
  VXORPS ZMM2, ZMM2, ZMM2;
  VMOVUPD ZMM3, [R14];
  VXORPS ZMM3, ZMM3, ZMM3;
  VMOVUPD ZMM4, [R14];
  VXORPS ZMM4, ZMM4, ZMM4;
  VMOVUPD ZMM5, [R14];
  VXORPS ZMM5, ZMM5, ZMM5;
  VMOVUPD ZMM6, [R14];
  VXORPS ZMM6, ZMM6, ZMM6;
  VMOVUPD ZMM7, [R14];
  VXORPS ZMM7, ZMM7, ZMM7;
  VMOVUPD ZMM8, [R14];
  VXORPS ZMM8, ZMM8, ZMM8;
  VMOVUPD ZMM9, [R14];
  VXORPS ZMM9, ZMM9, ZMM9;
  VMOVUPD ZMM10, [R14];
  VXORPS ZMM10, ZMM10, ZMM10;
  VMOVUPD ZMM11, [R14];
  VXORPS ZMM11, ZMM11, ZMM11;
  VMOVUPD ZMM12, [R14];
  VXORPS ZMM12, ZMM12, ZMM12;
  VMOVUPD ZMM16, [R14];
  VXORPS ZMM16, ZMM16, ZMM16;
  VMOVUPD ZMM17, [R14];
  VXORPS ZMM17, ZMM17, ZMM17;
  VMOVUPD ZMM18, [R14];
  VXORPS ZMM18, ZMM18, ZMM18

• Show nanoBench command
• Results:
  • Instructions retired: 20.2
  • Core cycles: 32.01
  • Reference cycles: 24.05
  • UOPS_EXECUTED.THREAD: 64.1
  • RETIRE_SLOTS: 68.1
  • UOPS_MITE: 0.7
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 32.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 32.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.16