MUL (R32)

With unroll_count=500 and no inner loop

Code:
```
   0:	41 f7 e0             	mul    r8d
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.98
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 2.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	41 f7 e0             	mul    r8d
   3:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.02
- Reference cycles: 2.94
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.61
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.54
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.86
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	41 f7 e0             	mul    r8d
   3:	90                   	nop
   4:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.0
- Reference cycles: 3.04
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 4.94
- UOPS_MS: 0.07
- UOPS_PORT_0: 0.55
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.57
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.88
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	41 f7 e0             	mul    r8d
   3:	90                   	nop
   4:	90                   	nop
   5:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.05
- Reference cycles: 3.04
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.6
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.59
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.81
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	41 f7 e0             	mul    r8d
   3:	90                   	nop
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.56
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.57
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.88
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:
```
   0:	41 f7 e0             	mul    r8d
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 3.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.23
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.55
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.66
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.89
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	41 f7 e0             	mul    r8d

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 3.02
- UOPS_EXECUTED.THREAD: 3.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.55
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.66
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.89
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:
```
   0:	41 f7 e0             	mul    r8d
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.01
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 3.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.54
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.56
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.91
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	41 f7 e0             	mul    r8d

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.01
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.54
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.56
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.91
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 e0             	mul    r8d

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 0.7
- UOPS_EXECUTED.THREAD: 3.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.52
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.53
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.95
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 e0             	mul    r8d

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 3.1
- RETIRE_SLOTS: 4.1
- UOPS_MITE: 4.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.53
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.62
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.95
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	40                   	rex
   e:	41 f7 e0             	mul    r8d

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 1.0
- Reference cycles: 0.76
- UOPS_EXECUTED.THREAD: 3.1
- RETIRE_SLOTS: 4.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.56
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.65
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.9
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 e0             	mul    r8d

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 4.01
- UOPS_MITE: 4.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.52
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.54
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.95
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	40                   	rex
   e:	41 f7 e0             	mul    r8d

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 1.0
- Reference cycles: 0.76
- UOPS_EXECUTED.THREAD: 3.01
- RETIRE_SLOTS: 4.01
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.56
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.57
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.88
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

MUL (R32) - Throughput and Uops

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)