CVTSI2SS (XMM, R32) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 4.0
  • Reference cycles: 2.98
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.97
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.5
  • UOPS_PORT_1: 0.5
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 1.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
     5:	90                   	nop
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 2.88
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.5
  • UOPS_PORT_1: 0.5
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 1.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
     5:	90                   	nop
     6:	90                   	nop
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 4.0
  • Reference cycles: 3.04
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.52
  • UOPS_PORT_1: 0.48
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 1.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
     5:	90                   	nop
     6:	90                   	nop
     7:	90                   	nop
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 4.0
  • Reference cycles: 3.01
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 5.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.5
  • UOPS_PORT_1: 0.5
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 1.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
     5:	90                   	nop
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 4.0
  • Reference cycles: 2.88
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 6.0
  • UOPS_MITE: 5.97
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.56
  • UOPS_PORT_1: 0.44
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 1.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 5 NOPs

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
     5:	90                   	nop
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 6.0
  • Core cycles: 4.0
  • Reference cycles: 2.91
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 7.0
  • UOPS_MITE: 7.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.5
  • UOPS_PORT_1: 0.5
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 1.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 4.0
  • Reference cycles: 3.01
  • UOPS_EXECUTED.THREAD: 2.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.5
  • UOPS_PORT_1: 0.5
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 1.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 4.0
  • Reference cycles: 3.01
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.5
  • UOPS_PORT_1: 0.5
  • UOPS_PORT_6: 0.01
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 1.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=200 and no inner loop

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
     5:	f3 41 0f 2a c8       	cvtsi2ss xmm1,r8d
     a:	f3 41 0f 2a d0       	cvtsi2ss xmm2,r8d
     f:	f3 41 0f 2a d8       	cvtsi2ss xmm3,r8d
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14];
  MOVUPD XMM1, [R14];
  MOVUPD XMM2, [R14];
  MOVUPD XMM3, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 4.0
  • Reference cycles: 3.04
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.98
  • UOPS_PORT_1: 2.02
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 4.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
     5:	f3 41 0f 2a c8       	cvtsi2ss xmm1,r8d
     a:	f3 41 0f 2a d0       	cvtsi2ss xmm2,r8d
     f:	f3 41 0f 2a d8       	cvtsi2ss xmm3,r8d
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14];
  MOVUPD XMM1, [R14];
  MOVUPD XMM2, [R14];
  MOVUPD XMM3, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 4.01
  • Reference cycles: 3.02
  • UOPS_EXECUTED.THREAD: 8.5
  • RETIRE_SLOTS: 8.5
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 1.99
  • UOPS_PORT_1: 2.01
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 4.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
     5:	f3 41 0f 2a c8       	cvtsi2ss xmm1,r8d
     a:	f3 41 0f 2a d0       	cvtsi2ss xmm2,r8d
     f:	f3 41 0f 2a d8       	cvtsi2ss xmm3,r8d
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14];
  MOVUPD XMM1, [R14];
  MOVUPD XMM2, [R14];
  MOVUPD XMM3, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 4.01
  • Reference cycles: 3.0
  • UOPS_EXECUTED.THREAD: 8.05
  • RETIRE_SLOTS: 8.05
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 2.0
  • UOPS_PORT_6: 0.05
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 4.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.04

With unroll_count=100 and no inner loop

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
     5:	f3 41 0f 2a c8       	cvtsi2ss xmm1,r8d
     a:	f3 41 0f 2a d0       	cvtsi2ss xmm2,r8d
     f:	f3 41 0f 2a d8       	cvtsi2ss xmm3,r8d
    14:	f3 41 0f 2a e0       	cvtsi2ss xmm4,r8d
    19:	f3 41 0f 2a e8       	cvtsi2ss xmm5,r8d
    1e:	f3 41 0f 2a f0       	cvtsi2ss xmm6,r8d
    23:	f3 41 0f 2a f8       	cvtsi2ss xmm7,r8d
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14];
  MOVUPD XMM1, [R14];
  MOVUPD XMM2, [R14];
  MOVUPD XMM3, [R14];
  MOVUPD XMM4, [R14];
  MOVUPD XMM5, [R14];
  MOVUPD XMM6, [R14];
  MOVUPD XMM7, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 8.0
  • Reference cycles: 6.24
  • UOPS_EXECUTED.THREAD: 16.0
  • RETIRE_SLOTS: 16.0
  • UOPS_MITE: 15.67
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 3.93
  • UOPS_PORT_1: 4.08
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 8.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
     5:	f3 41 0f 2a c8       	cvtsi2ss xmm1,r8d
     a:	f3 41 0f 2a d0       	cvtsi2ss xmm2,r8d
     f:	f3 41 0f 2a d8       	cvtsi2ss xmm3,r8d
    14:	f3 41 0f 2a e0       	cvtsi2ss xmm4,r8d
    19:	f3 41 0f 2a e8       	cvtsi2ss xmm5,r8d
    1e:	f3 41 0f 2a f0       	cvtsi2ss xmm6,r8d
    23:	f3 41 0f 2a f8       	cvtsi2ss xmm7,r8d
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14];
  MOVUPD XMM1, [R14];
  MOVUPD XMM2, [R14];
  MOVUPD XMM3, [R14];
  MOVUPD XMM4, [R14];
  MOVUPD XMM5, [R14];
  MOVUPD XMM6, [R14];
  MOVUPD XMM7, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 8.01
  • Reference cycles: 5.98
  • UOPS_EXECUTED.THREAD: 17.0
  • RETIRE_SLOTS: 17.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.03
  • UOPS_PORT_0: 3.98
  • UOPS_PORT_1: 4.02
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 8.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
     5:	f3 41 0f 2a c8       	cvtsi2ss xmm1,r8d
     a:	f3 41 0f 2a d0       	cvtsi2ss xmm2,r8d
     f:	f3 41 0f 2a d8       	cvtsi2ss xmm3,r8d
    14:	f3 41 0f 2a e0       	cvtsi2ss xmm4,r8d
    19:	f3 41 0f 2a e8       	cvtsi2ss xmm5,r8d
    1e:	f3 41 0f 2a f0       	cvtsi2ss xmm6,r8d
    23:	f3 41 0f 2a f8       	cvtsi2ss xmm7,r8d
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14];
  MOVUPD XMM1, [R14];
  MOVUPD XMM2, [R14];
  MOVUPD XMM3, [R14];
  MOVUPD XMM4, [R14];
  MOVUPD XMM5, [R14];
  MOVUPD XMM6, [R14];
  MOVUPD XMM7, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 8.01
  • Reference cycles: 6.05
  • UOPS_EXECUTED.THREAD: 16.1
  • RETIRE_SLOTS: 16.1
  • UOPS_MITE: 0.16
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 3.99
  • UOPS_PORT_1: 4.01
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 8.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.08

With unroll_count=100 and no inner loop

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
     5:	f3 41 0f 2a c8       	cvtsi2ss xmm1,r8d
     a:	f3 41 0f 2a d0       	cvtsi2ss xmm2,r8d
     f:	f3 41 0f 2a d8       	cvtsi2ss xmm3,r8d
    14:	f3 41 0f 2a e0       	cvtsi2ss xmm4,r8d
    19:	f3 41 0f 2a e8       	cvtsi2ss xmm5,r8d
    1e:	f3 41 0f 2a f0       	cvtsi2ss xmm6,r8d
    23:	f3 41 0f 2a f8       	cvtsi2ss xmm7,r8d
    28:	f3 45 0f 2a c0       	cvtsi2ss xmm8,r8d
    2d:	f3 45 0f 2a c8       	cvtsi2ss xmm9,r8d
    32:	f3 45 0f 2a d0       	cvtsi2ss xmm10,r8d
    37:	f3 45 0f 2a d8       	cvtsi2ss xmm11,r8d
    3c:	f3 45 0f 2a e0       	cvtsi2ss xmm12,r8d
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14];
  MOVUPD XMM1, [R14];
  MOVUPD XMM2, [R14];
  MOVUPD XMM3, [R14];
  MOVUPD XMM4, [R14];
  MOVUPD XMM5, [R14];
  MOVUPD XMM6, [R14];
  MOVUPD XMM7, [R14];
  MOVUPD XMM8, [R14];
  MOVUPD XMM9, [R14];
  MOVUPD XMM10, [R14];
  MOVUPD XMM11, [R14];
  MOVUPD XMM12, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 13.0
  • Core cycles: 13.0
  • Reference cycles: 9.76
  • UOPS_EXECUTED.THREAD: 26.01
  • RETIRE_SLOTS: 26.0
  • UOPS_MITE: 25.68
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 6.41
  • UOPS_PORT_1: 6.59
  • UOPS_PORT_6: 0.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 13.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 13.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
     5:	f3 41 0f 2a c8       	cvtsi2ss xmm1,r8d
     a:	f3 41 0f 2a d0       	cvtsi2ss xmm2,r8d
     f:	f3 41 0f 2a d8       	cvtsi2ss xmm3,r8d
    14:	f3 41 0f 2a e0       	cvtsi2ss xmm4,r8d
    19:	f3 41 0f 2a e8       	cvtsi2ss xmm5,r8d
    1e:	f3 41 0f 2a f0       	cvtsi2ss xmm6,r8d
    23:	f3 41 0f 2a f8       	cvtsi2ss xmm7,r8d
    28:	f3 45 0f 2a c0       	cvtsi2ss xmm8,r8d
    2d:	f3 45 0f 2a c8       	cvtsi2ss xmm9,r8d
    32:	f3 45 0f 2a d0       	cvtsi2ss xmm10,r8d
    37:	f3 45 0f 2a d8       	cvtsi2ss xmm11,r8d
    3c:	f3 45 0f 2a e0       	cvtsi2ss xmm12,r8d
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14];
  MOVUPD XMM1, [R14];
  MOVUPD XMM2, [R14];
  MOVUPD XMM3, [R14];
  MOVUPD XMM4, [R14];
  MOVUPD XMM5, [R14];
  MOVUPD XMM6, [R14];
  MOVUPD XMM7, [R14];
  MOVUPD XMM8, [R14];
  MOVUPD XMM9, [R14];
  MOVUPD XMM10, [R14];
  MOVUPD XMM11, [R14];
  MOVUPD XMM12, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 15.0
  • Core cycles: 13.01
  • Reference cycles: 10.18
  • UOPS_EXECUTED.THREAD: 27.0
  • RETIRE_SLOTS: 27.0
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 6.47
  • UOPS_PORT_1: 6.53
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 13.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
     5:	f3 41 0f 2a c8       	cvtsi2ss xmm1,r8d
     a:	f3 41 0f 2a d0       	cvtsi2ss xmm2,r8d
     f:	f3 41 0f 2a d8       	cvtsi2ss xmm3,r8d
    14:	f3 41 0f 2a e0       	cvtsi2ss xmm4,r8d
    19:	f3 41 0f 2a e8       	cvtsi2ss xmm5,r8d
    1e:	f3 41 0f 2a f0       	cvtsi2ss xmm6,r8d
    23:	f3 41 0f 2a f8       	cvtsi2ss xmm7,r8d
    28:	f3 45 0f 2a c0       	cvtsi2ss xmm8,r8d
    2d:	f3 45 0f 2a c8       	cvtsi2ss xmm9,r8d
    32:	f3 45 0f 2a d0       	cvtsi2ss xmm10,r8d
    37:	f3 45 0f 2a d8       	cvtsi2ss xmm11,r8d
    3c:	f3 45 0f 2a e0       	cvtsi2ss xmm12,r8d
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14];
  MOVUPD XMM1, [R14];
  MOVUPD XMM2, [R14];
  MOVUPD XMM3, [R14];
  MOVUPD XMM4, [R14];
  MOVUPD XMM5, [R14];
  MOVUPD XMM6, [R14];
  MOVUPD XMM7, [R14];
  MOVUPD XMM8, [R14];
  MOVUPD XMM9, [R14];
  MOVUPD XMM10, [R14];
  MOVUPD XMM11, [R14];
  MOVUPD XMM12, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 13.2
  • Core cycles: 13.01
  • Reference cycles: 10.24
  • UOPS_EXECUTED.THREAD: 26.1
  • RETIRE_SLOTS: 26.1
  • UOPS_MITE: 0.25
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 6.5
  • UOPS_PORT_1: 6.5
  • UOPS_PORT_6: 0.1
  • UOPS_PORT_49: 0.0
  • UOPS_PORT_78: 0.0
  • UOPS_PORT_5B: 13.0
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.13