ADD (M32, I32) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 1.0
  • Reference cycles: 0.8
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.2
  • UOPS_PORT_1: 0.2
  • UOPS_PORT_6: 0.2
  • UOPS_PORT_49: 1.0
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 0.4
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     7:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.0
  • Reference cycles: 0.7
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.18
  • UOPS_PORT_1: 0.2
  • UOPS_PORT_6: 0.22
  • UOPS_PORT_49: 1.0
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 0.4
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     7:	90                   	nop
     8:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 1.0
  • Reference cycles: 0.77
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.18
  • UOPS_PORT_1: 0.2
  • UOPS_PORT_6: 0.2
  • UOPS_PORT_49: 1.0
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 0.43
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 1.02
  • Reference cycles: 0.77
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 4.94
  • UOPS_MS: 0.07
  • UOPS_PORT_0: 0.18
  • UOPS_PORT_1: 0.19
  • UOPS_PORT_6: 0.23
  • UOPS_PORT_49: 1.0
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 0.43
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 4 NOPs

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
     a:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 1.02
  • Reference cycles: 0.8
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 6.0
  • UOPS_MITE: 5.93
  • UOPS_MS: 0.07
  • UOPS_PORT_0: 0.14
  • UOPS_PORT_1: 0.14
  • UOPS_PORT_6: 0.21
  • UOPS_PORT_49: 1.0
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 0.5
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 5 NOPs

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
     a:	90                   	nop
     b:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 6.0
  • Core cycles: 2.0
  • Reference cycles: 1.47
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 7.0
  • UOPS_MITE: 7.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.2
  • UOPS_PORT_1: 0.2
  • UOPS_PORT_6: 0.2
  • UOPS_PORT_49: 1.0
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 0.4
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 1.0
  • Reference cycles: 0.75
  • UOPS_EXECUTED.THREAD: 4.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 2.1
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.2
  • UOPS_PORT_1: 0.2
  • UOPS_PORT_6: 0.29
  • UOPS_PORT_49: 1.0
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 0.41
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 1.0
  • Reference cycles: 0.75
  • UOPS_EXECUTED.THREAD: 4.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 2.1
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.2
  • UOPS_PORT_1: 0.2
  • UOPS_PORT_6: 0.29
  • UOPS_PORT_49: 1.0
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 0.41
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=100

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 1.0
  • Reference cycles: 0.75
  • UOPS_EXECUTED.THREAD: 4.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 2.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.2
  • UOPS_PORT_1: 0.19
  • UOPS_PORT_6: 0.21
  • UOPS_PORT_49: 1.0
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 0.4
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 1.0
  • Reference cycles: 0.75
  • UOPS_EXECUTED.THREAD: 4.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 2.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.2
  • UOPS_PORT_1: 0.19
  • UOPS_PORT_6: 0.21
  • UOPS_PORT_49: 1.0
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 0.4
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=200 and no inner loop

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
     e:	01 
     f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    16:	01 
    17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    1e:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 3.81
  • Reference cycles: 3.04
  • UOPS_EXECUTED.THREAD: 16.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 7.91
  • UOPS_MS: 0.19
  • UOPS_PORT_0: 0.7
  • UOPS_PORT_1: 0.74
  • UOPS_PORT_6: 0.87
  • UOPS_PORT_49: 4.01
  • UOPS_PORT_78: 4.0
  • UOPS_PORT_5B: 1.78
  • UOPS_PORT_5B>=2: 0.09
  • UOPS_PORT_23A: 4.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 3.96

With loop_count=1000 and unroll_count=2

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
     e:	01 
     f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    16:	01 
    17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    1e:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 3.99
  • Reference cycles: 3.0
  • UOPS_EXECUTED.THREAD: 16.51
  • RETIRE_SLOTS: 8.5
  • UOPS_MITE: 8.5
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 0.75
  • UOPS_PORT_1: 0.75
  • UOPS_PORT_6: 1.18
  • UOPS_PORT_49: 4.0
  • UOPS_PORT_78: 4.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.01
  • UOPS_PORT_23A: 4.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     8:	40                   	rex
     9:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
    10:	01 
    11:	40                   	rex
    12:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    19:	01 
    1a:	40                   	rex
    1b:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    22:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 3.99
  • Reference cycles: 2.99
  • UOPS_EXECUTED.THREAD: 16.51
  • RETIRE_SLOTS: 8.5
  • UOPS_MITE: 8.5
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 0.75
  • UOPS_PORT_1: 0.75
  • UOPS_PORT_6: 1.18
  • UOPS_PORT_49: 4.0
  • UOPS_PORT_78: 4.0
  • UOPS_PORT_5B: 2.0
  • UOPS_PORT_5B>=2: 0.01
  • UOPS_PORT_23A: 4.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=100 and unroll_count=20

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
     e:	01 
     f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    16:	01 
    17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    1e:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 3.98
  • Reference cycles: 3.03
  • UOPS_EXECUTED.THREAD: 16.05
  • RETIRE_SLOTS: 8.05
  • UOPS_MITE: 8.04
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 0.74
  • UOPS_PORT_1: 0.72
  • UOPS_PORT_6: 0.82
  • UOPS_PORT_49: 4.0
  • UOPS_PORT_78: 4.0
  • UOPS_PORT_5B: 1.77
  • UOPS_PORT_5B>=2: 0.01
  • UOPS_PORT_23A: 4.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     8:	40                   	rex
     9:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
    10:	01 
    11:	40                   	rex
    12:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    19:	01 
    1a:	40                   	rex
    1b:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    22:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 3.98
  • Reference cycles: 2.99
  • UOPS_EXECUTED.THREAD: 16.05
  • RETIRE_SLOTS: 8.05
  • UOPS_MITE: 8.04
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 0.69
  • UOPS_PORT_1: 0.75
  • UOPS_PORT_6: 0.88
  • UOPS_PORT_49: 4.0
  • UOPS_PORT_78: 4.0
  • UOPS_PORT_5B: 1.78
  • UOPS_PORT_5B>=2: 0.07
  • UOPS_PORT_23A: 4.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With unroll_count=100 and no inner loop

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
     e:	01 
     f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    16:	01 
    17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    1e:	01 
    1f:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
    26:	01 
    27:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
    2e:	01 
    2f:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
    36:	01 
    37:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
    3e:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 7.65
  • Reference cycles: 6.08
  • UOPS_EXECUTED.THREAD: 32.0
  • RETIRE_SLOTS: 15.99
  • UOPS_MITE: 15.82
  • UOPS_MS: 0.37
  • UOPS_PORT_0: 1.51
  • UOPS_PORT_1: 1.56
  • UOPS_PORT_6: 1.74
  • UOPS_PORT_49: 8.05
  • UOPS_PORT_78: 8.0
  • UOPS_PORT_5B: 3.54
  • UOPS_PORT_5B>=2: 0.28
  • UOPS_PORT_23A: 8.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 7.91

With loop_count=1000 and unroll_count=1

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
     e:	01 
     f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    16:	01 
    17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    1e:	01 
    1f:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
    26:	01 
    27:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
    2e:	01 
    2f:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
    36:	01 
    37:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
    3e:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 7.99
  • Reference cycles: 5.98
  • UOPS_EXECUTED.THREAD: 33.01
  • RETIRE_SLOTS: 17.0
  • UOPS_MITE: 17.01
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 1.46
  • UOPS_PORT_1: 1.64
  • UOPS_PORT_6: 2.14
  • UOPS_PORT_49: 8.0
  • UOPS_PORT_78: 8.0
  • UOPS_PORT_5B: 3.32
  • UOPS_PORT_5B>=2: 0.01
  • UOPS_PORT_23A: 8.01
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     8:	40                   	rex
     9:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
    10:	01 
    11:	40                   	rex
    12:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    19:	01 
    1a:	40                   	rex
    1b:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    22:	01 
    23:	40                   	rex
    24:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
    2b:	01 
    2c:	40                   	rex
    2d:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
    34:	01 
    35:	40                   	rex
    36:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
    3d:	01 
    3e:	40                   	rex
    3f:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
    46:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 7.99
  • Reference cycles: 6.02
  • UOPS_EXECUTED.THREAD: 33.01
  • RETIRE_SLOTS: 17.0
  • UOPS_MITE: 17.01
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 1.46
  • UOPS_PORT_1: 1.64
  • UOPS_PORT_6: 2.14
  • UOPS_PORT_49: 8.0
  • UOPS_PORT_78: 8.0
  • UOPS_PORT_5B: 3.77
  • UOPS_PORT_5B>=2: 0.01
  • UOPS_PORT_23A: 8.01
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=100 and unroll_count=10

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
     e:	01 
     f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    16:	01 
    17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    1e:	01 
    1f:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
    26:	01 
    27:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
    2e:	01 
    2f:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
    36:	01 
    37:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
    3e:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 7.96
  • Reference cycles: 5.95
  • UOPS_EXECUTED.THREAD: 32.1
  • RETIRE_SLOTS: 16.1
  • UOPS_MITE: 16.08
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 1.4
  • UOPS_PORT_1: 1.52
  • UOPS_PORT_6: 1.7
  • UOPS_PORT_49: 8.0
  • UOPS_PORT_78: 8.0
  • UOPS_PORT_5B: 3.52
  • UOPS_PORT_5B>=2: 0.16
  • UOPS_PORT_23A: 8.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 7.99

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     8:	40                   	rex
     9:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
    10:	01 
    11:	40                   	rex
    12:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    19:	01 
    1a:	40                   	rex
    1b:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    22:	01 
    23:	40                   	rex
    24:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
    2b:	01 
    2c:	40                   	rex
    2d:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
    34:	01 
    35:	40                   	rex
    36:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
    3d:	01 
    3e:	40                   	rex
    3f:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
    46:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 7.96
  • Reference cycles: 5.97
  • UOPS_EXECUTED.THREAD: 32.1
  • RETIRE_SLOTS: 16.1
  • UOPS_MITE: 16.08
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 1.45
  • UOPS_PORT_1: 1.5
  • UOPS_PORT_6: 1.72
  • UOPS_PORT_49: 8.01
  • UOPS_PORT_78: 8.0
  • UOPS_PORT_5B: 3.45
  • UOPS_PORT_5B>=2: 0.29
  • UOPS_PORT_23A: 8.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 7.99

With unroll_count=100 and no inner loop

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
     e:	01 
     f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    16:	01 
    17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    1e:	01 
    1f:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
    26:	01 
    27:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
    2e:	01 
    2f:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
    36:	01 
    37:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
    3e:	01 
    3f:	41 81 46 20 00 00 00 	add    DWORD PTR [r14+0x20],0x1000000
    46:	01 
    47:	41 81 46 24 00 00 00 	add    DWORD PTR [r14+0x24],0x1000000
    4e:	01 
    4f:	41 81 46 28 00 00 00 	add    DWORD PTR [r14+0x28],0x1000000
    56:	01 
    57:	41 81 46 2c 00 00 00 	add    DWORD PTR [r14+0x2c],0x1000000
    5e:	01 
    5f:	41 81 46 30 00 00 00 	add    DWORD PTR [r14+0x30],0x1000000
    66:	01 
    67:	41 81 46 34 00 00 00 	add    DWORD PTR [r14+0x34],0x1000000
    6e:	01 
    6f:	41 81 46 38 00 00 00 	add    DWORD PTR [r14+0x38],0x1000000
    76:	01 
    77:	41 81 46 3c 00 00 00 	add    DWORD PTR [r14+0x3c],0x1000000
    7e:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 15.65
  • Reference cycles: 11.52
  • UOPS_EXECUTED.THREAD: 64.02
  • RETIRE_SLOTS: 32.0
  • UOPS_MITE: 31.82
  • UOPS_MS: 0.36
  • UOPS_PORT_0: 2.82
  • UOPS_PORT_1: 2.99
  • UOPS_PORT_6: 3.42
  • UOPS_PORT_49: 16.0
  • UOPS_PORT_78: 16.0
  • UOPS_PORT_5B: 6.87
  • UOPS_PORT_5B>=2: 0.37
  • UOPS_PORT_23A: 16.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 15.91

With loop_count=1000 and unroll_count=1

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
     e:	01 
     f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    16:	01 
    17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    1e:	01 
    1f:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
    26:	01 
    27:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
    2e:	01 
    2f:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
    36:	01 
    37:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
    3e:	01 
    3f:	41 81 46 20 00 00 00 	add    DWORD PTR [r14+0x20],0x1000000
    46:	01 
    47:	41 81 46 24 00 00 00 	add    DWORD PTR [r14+0x24],0x1000000
    4e:	01 
    4f:	41 81 46 28 00 00 00 	add    DWORD PTR [r14+0x28],0x1000000
    56:	01 
    57:	41 81 46 2c 00 00 00 	add    DWORD PTR [r14+0x2c],0x1000000
    5e:	01 
    5f:	41 81 46 30 00 00 00 	add    DWORD PTR [r14+0x30],0x1000000
    66:	01 
    67:	41 81 46 34 00 00 00 	add    DWORD PTR [r14+0x34],0x1000000
    6e:	01 
    6f:	41 81 46 38 00 00 00 	add    DWORD PTR [r14+0x38],0x1000000
    76:	01 
    77:	41 81 46 3c 00 00 00 	add    DWORD PTR [r14+0x3c],0x1000000
    7e:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 15.98
  • Reference cycles: 12.0
  • UOPS_EXECUTED.THREAD: 65.01
  • RETIRE_SLOTS: 33.0
  • UOPS_MITE: 33.01
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 2.8
  • UOPS_PORT_1: 2.87
  • UOPS_PORT_6: 4.14
  • UOPS_PORT_49: 16.0
  • UOPS_PORT_78: 16.0
  • UOPS_PORT_5B: 7.2
  • UOPS_PORT_5B>=2: 0.4
  • UOPS_PORT_23A: 16.01
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     8:	40                   	rex
     9:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
    10:	01 
    11:	40                   	rex
    12:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    19:	01 
    1a:	40                   	rex
    1b:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    22:	01 
    23:	40                   	rex
    24:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
    2b:	01 
    2c:	40                   	rex
    2d:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
    34:	01 
    35:	40                   	rex
    36:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
    3d:	01 
    3e:	40                   	rex
    3f:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
    46:	01 
    47:	40                   	rex
    48:	41 81 46 20 00 00 00 	add    DWORD PTR [r14+0x20],0x1000000
    4f:	01 
    50:	40                   	rex
    51:	41 81 46 24 00 00 00 	add    DWORD PTR [r14+0x24],0x1000000
    58:	01 
    59:	40                   	rex
    5a:	41 81 46 28 00 00 00 	add    DWORD PTR [r14+0x28],0x1000000
    61:	01 
    62:	40                   	rex
    63:	41 81 46 2c 00 00 00 	add    DWORD PTR [r14+0x2c],0x1000000
    6a:	01 
    6b:	40                   	rex
    6c:	41 81 46 30 00 00 00 	add    DWORD PTR [r14+0x30],0x1000000
    73:	01 
    74:	40                   	rex
    75:	41 81 46 34 00 00 00 	add    DWORD PTR [r14+0x34],0x1000000
    7c:	01 
    7d:	40                   	rex
    7e:	41 81 46 38 00 00 00 	add    DWORD PTR [r14+0x38],0x1000000
    85:	01 
    86:	40                   	rex
    87:	41 81 46 3c 00 00 00 	add    DWORD PTR [r14+0x3c],0x1000000
    8e:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 15.98
  • Reference cycles: 12.0
  • UOPS_EXECUTED.THREAD: 65.01
  • RETIRE_SLOTS: 33.0
  • UOPS_MITE: 33.04
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 2.61
  • UOPS_PORT_1: 3.0
  • UOPS_PORT_6: 4.0
  • UOPS_PORT_49: 16.0
  • UOPS_PORT_78: 16.0
  • UOPS_PORT_5B: 7.34
  • UOPS_PORT_5B>=2: 0.35
  • UOPS_PORT_23A: 16.01
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=100 and unroll_count=10

• Code:

     0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     7:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
     e:	01 
     f:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    16:	01 
    17:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    1e:	01 
    1f:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
    26:	01 
    27:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
    2e:	01 
    2f:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
    36:	01 
    37:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
    3e:	01 
    3f:	41 81 46 20 00 00 00 	add    DWORD PTR [r14+0x20],0x1000000
    46:	01 
    47:	41 81 46 24 00 00 00 	add    DWORD PTR [r14+0x24],0x1000000
    4e:	01 
    4f:	41 81 46 28 00 00 00 	add    DWORD PTR [r14+0x28],0x1000000
    56:	01 
    57:	41 81 46 2c 00 00 00 	add    DWORD PTR [r14+0x2c],0x1000000
    5e:	01 
    5f:	41 81 46 30 00 00 00 	add    DWORD PTR [r14+0x30],0x1000000
    66:	01 
    67:	41 81 46 34 00 00 00 	add    DWORD PTR [r14+0x34],0x1000000
    6e:	01 
    6f:	41 81 46 38 00 00 00 	add    DWORD PTR [r14+0x38],0x1000000
    76:	01 
    77:	41 81 46 3c 00 00 00 	add    DWORD PTR [r14+0x3c],0x1000000
    7e:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 15.96
  • Reference cycles: 12.0
  • UOPS_EXECUTED.THREAD: 64.1
  • RETIRE_SLOTS: 32.1
  • UOPS_MITE: 32.1
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 2.86
  • UOPS_PORT_1: 3.05
  • UOPS_PORT_6: 3.44
  • UOPS_PORT_49: 16.0
  • UOPS_PORT_78: 16.0
  • UOPS_PORT_5B: 6.88
  • UOPS_PORT_5B>=2: 0.35
  • UOPS_PORT_23A: 16.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 15.99

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
     8:	40                   	rex
     9:	41 81 46 04 00 00 00 	add    DWORD PTR [r14+0x4],0x1000000
    10:	01 
    11:	40                   	rex
    12:	41 81 46 08 00 00 00 	add    DWORD PTR [r14+0x8],0x1000000
    19:	01 
    1a:	40                   	rex
    1b:	41 81 46 0c 00 00 00 	add    DWORD PTR [r14+0xc],0x1000000
    22:	01 
    23:	40                   	rex
    24:	41 81 46 10 00 00 00 	add    DWORD PTR [r14+0x10],0x1000000
    2b:	01 
    2c:	40                   	rex
    2d:	41 81 46 14 00 00 00 	add    DWORD PTR [r14+0x14],0x1000000
    34:	01 
    35:	40                   	rex
    36:	41 81 46 18 00 00 00 	add    DWORD PTR [r14+0x18],0x1000000
    3d:	01 
    3e:	40                   	rex
    3f:	41 81 46 1c 00 00 00 	add    DWORD PTR [r14+0x1c],0x1000000
    46:	01 
    47:	40                   	rex
    48:	41 81 46 20 00 00 00 	add    DWORD PTR [r14+0x20],0x1000000
    4f:	01 
    50:	40                   	rex
    51:	41 81 46 24 00 00 00 	add    DWORD PTR [r14+0x24],0x1000000
    58:	01 
    59:	40                   	rex
    5a:	41 81 46 28 00 00 00 	add    DWORD PTR [r14+0x28],0x1000000
    61:	01 
    62:	40                   	rex
    63:	41 81 46 2c 00 00 00 	add    DWORD PTR [r14+0x2c],0x1000000
    6a:	01 
    6b:	40                   	rex
    6c:	41 81 46 30 00 00 00 	add    DWORD PTR [r14+0x30],0x1000000
    73:	01 
    74:	40                   	rex
    75:	41 81 46 34 00 00 00 	add    DWORD PTR [r14+0x34],0x1000000
    7c:	01 
    7d:	40                   	rex
    7e:	41 81 46 38 00 00 00 	add    DWORD PTR [r14+0x38],0x1000000
    85:	01 
    86:	40                   	rex
    87:	41 81 46 3c 00 00 00 	add    DWORD PTR [r14+0x3c],0x1000000
    8e:	01 
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 15.96
  • Reference cycles: 12.02
  • UOPS_EXECUTED.THREAD: 64.1
  • RETIRE_SLOTS: 32.1
  • UOPS_MITE: 32.11
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 2.72
  • UOPS_PORT_1: 3.05
  • UOPS_PORT_6: 3.5
  • UOPS_PORT_49: 16.0
  • UOPS_PORT_78: 16.0
  • UOPS_PORT_5B: 6.9
  • UOPS_PORT_5B>=2: 0.47
  • UOPS_PORT_23A: 16.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With unroll_count=500 and no inner loop

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 7.39
  • Reference cycles: 5.57
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.88
  • UOPS_PORT_1: 2.66
  • UOPS_PORT_6: 2.94
  • UOPS_PORT_49: 5.59
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 5.92
  • UOPS_PORT_5B>=2: 1.2
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
     8:	90                   	nop
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.44
  • Reference cycles: 5.57
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 2.93
  • UOPS_MS: 0.07
  • UOPS_PORT_0: 2.55
  • UOPS_PORT_1: 2.83
  • UOPS_PORT_6: 2.81
  • UOPS_PORT_49: 4.1
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 5.63
  • UOPS_PORT_5B>=2: 0.96
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.98

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
     8:	90                   	nop
     9:	90                   	nop
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 7.44
  • Reference cycles: 5.57
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 3.92
  • UOPS_MS: 0.07
  • UOPS_PORT_0: 2.55
  • UOPS_PORT_1: 2.83
  • UOPS_PORT_6: 2.81
  • UOPS_PORT_49: 4.1
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 5.63
  • UOPS_PORT_5B>=2: 0.96
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.98

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
     8:	90                   	nop
     9:	90                   	nop
     a:	90                   	nop
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 7.36
  • Reference cycles: 5.57
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 6.0
  • UOPS_MITE: 4.9
  • UOPS_MS: 0.07
  • UOPS_PORT_0: 2.65
  • UOPS_PORT_1: 2.79
  • UOPS_PORT_6: 2.89
  • UOPS_PORT_49: 4.2
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 4.4
  • UOPS_PORT_5B>=2: 0.59
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 4 NOPs

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
     8:	90                   	nop
     9:	90                   	nop
     a:	90                   	nop
     b:	90                   	nop
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 7.39
  • Reference cycles: 5.57
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 7.0
  • UOPS_MITE: 5.9
  • UOPS_MS: 0.07
  • UOPS_PORT_0: 2.54
  • UOPS_PORT_1: 2.58
  • UOPS_PORT_6: 2.58
  • UOPS_PORT_49: 4.34
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 5.26
  • UOPS_PORT_5B>=2: 0.95
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 5 NOPs

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
     8:	90                   	nop
     9:	90                   	nop
     a:	90                   	nop
     b:	90                   	nop
     c:	90                   	nop
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 6.0
  • Core cycles: 7.33
  • Reference cycles: 5.54
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 7.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.86
  • UOPS_PORT_1: 2.85
  • UOPS_PORT_6: 2.84
  • UOPS_PORT_49: 4.94
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 5.57
  • UOPS_PORT_5B>=2: 1.11
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 7.39
  • Reference cycles: 5.56
  • UOPS_EXECUTED.THREAD: 4.1
  • RETIRE_SLOTS: 3.1
  • UOPS_MITE: 2.11
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.76
  • UOPS_PORT_1: 2.69
  • UOPS_PORT_6: 3.03
  • UOPS_PORT_49: 5.48
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 5.92
  • UOPS_PORT_5B>=2: 1.24
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     8:	01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 7.39
  • Reference cycles: 5.56
  • UOPS_EXECUTED.THREAD: 4.1
  • RETIRE_SLOTS: 3.1
  • UOPS_MITE: 2.11
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.76
  • UOPS_PORT_1: 2.69
  • UOPS_PORT_6: 3.03
  • UOPS_PORT_49: 5.48
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 5.92
  • UOPS_PORT_5B>=2: 1.24
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=100

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 7.39
  • Reference cycles: 5.56
  • UOPS_EXECUTED.THREAD: 4.01
  • RETIRE_SLOTS: 3.01
  • UOPS_MITE: 2.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.82
  • UOPS_PORT_1: 2.64
  • UOPS_PORT_6: 2.98
  • UOPS_PORT_49: 5.52
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 5.92
  • UOPS_PORT_5B>=2: 1.28
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     8:	01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 7.39
  • Reference cycles: 5.57
  • UOPS_EXECUTED.THREAD: 4.01
  • RETIRE_SLOTS: 3.01
  • UOPS_MITE: 2.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.81
  • UOPS_PORT_1: 2.63
  • UOPS_PORT_6: 2.97
  • UOPS_PORT_49: 5.52
  • UOPS_PORT_78: 1.0
  • UOPS_PORT_5B: 5.92
  • UOPS_PORT_5B>=2: 1.28
  • UOPS_PORT_23A: 1.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=200 and no inner loop

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
     8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
     f:	00 01 
    11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    18:	00 01 
    1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    21:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 8.35
  • Reference cycles: 6.24
  • UOPS_EXECUTED.THREAD: 16.01
  • RETIRE_SLOTS: 12.0
  • UOPS_MITE: 7.91
  • UOPS_MS: 0.19
  • UOPS_PORT_0: 3.86
  • UOPS_PORT_1: 3.81
  • UOPS_PORT_6: 4.02
  • UOPS_PORT_49: 4.87
  • UOPS_PORT_78: 4.0
  • UOPS_PORT_5B: 8.03
  • UOPS_PORT_5B>=2: 1.7
  • UOPS_PORT_23A: 4.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 3.96

With loop_count=1000 and unroll_count=2

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
     8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
     f:	00 01 
    11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    18:	00 01 
    1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    21:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 8.0
  • Reference cycles: 6.01
  • UOPS_EXECUTED.THREAD: 16.5
  • RETIRE_SLOTS: 12.5
  • UOPS_MITE: 8.54
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 2.32
  • UOPS_PORT_1: 2.37
  • UOPS_PORT_6: 2.93
  • UOPS_PORT_49: 5.56
  • UOPS_PORT_78: 4.0
  • UOPS_PORT_5B: 5.19
  • UOPS_PORT_5B>=2: 0.91
  • UOPS_PORT_23A: 4.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.02

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     8:	01 
     9:	40                   	rex
     a:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
    11:	00 01 
    13:	40                   	rex
    14:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    1b:	00 01 
    1d:	40                   	rex
    1e:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    25:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 8.0
  • Reference cycles: 6.0
  • UOPS_EXECUTED.THREAD: 16.5
  • RETIRE_SLOTS: 12.5
  • UOPS_MITE: 8.54
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 2.29
  • UOPS_PORT_1: 2.37
  • UOPS_PORT_6: 2.93
  • UOPS_PORT_49: 5.56
  • UOPS_PORT_78: 4.0
  • UOPS_PORT_5B: 5.02
  • UOPS_PORT_5B>=2: 0.89
  • UOPS_PORT_23A: 4.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.02

With loop_count=100 and unroll_count=20

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
     8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
     f:	00 01 
    11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    18:	00 01 
    1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    21:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 8.33
  • Reference cycles: 6.26
  • UOPS_EXECUTED.THREAD: 16.05
  • RETIRE_SLOTS: 12.05
  • UOPS_MITE: 8.04
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 3.71
  • UOPS_PORT_1: 3.79
  • UOPS_PORT_6: 3.95
  • UOPS_PORT_49: 5.01
  • UOPS_PORT_78: 4.0
  • UOPS_PORT_5B: 7.74
  • UOPS_PORT_5B>=2: 1.79
  • UOPS_PORT_23A: 4.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     8:	01 
     9:	40                   	rex
     a:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
    11:	00 01 
    13:	40                   	rex
    14:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    1b:	00 01 
    1d:	40                   	rex
    1e:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    25:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 8.33
  • Reference cycles: 6.27
  • UOPS_EXECUTED.THREAD: 16.05
  • RETIRE_SLOTS: 12.05
  • UOPS_MITE: 8.04
  • UOPS_MS: 0.02
  • UOPS_PORT_0: 3.67
  • UOPS_PORT_1: 3.76
  • UOPS_PORT_6: 3.9
  • UOPS_PORT_49: 4.81
  • UOPS_PORT_78: 4.0
  • UOPS_PORT_5B: 7.96
  • UOPS_PORT_5B>=2: 1.86
  • UOPS_PORT_23A: 4.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With unroll_count=100 and no inner loop

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
     8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
     f:	00 01 
    11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    18:	00 01 
    1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    21:	00 01 
    23:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
    2a:	00 01 
    2c:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
    33:	00 01 
    35:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
    3c:	00 01 
    3e:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
    45:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 7.68
  • Reference cycles: 5.76
  • UOPS_EXECUTED.THREAD: 31.96
  • RETIRE_SLOTS: 24.0
  • UOPS_MITE: 15.68
  • UOPS_MS: 0.37
  • UOPS_PORT_0: 1.6
  • UOPS_PORT_1: 1.59
  • UOPS_PORT_6: 1.6
  • UOPS_PORT_49: 8.0
  • UOPS_PORT_78: 8.0
  • UOPS_PORT_5B: 3.22
  • UOPS_PORT_5B>=2: 0.07
  • UOPS_PORT_23A: 8.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 7.91

With loop_count=1000 and unroll_count=1

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
     8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
     f:	00 01 
    11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    18:	00 01 
    1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    21:	00 01 
    23:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
    2a:	00 01 
    2c:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
    33:	00 01 
    35:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
    3c:	00 01 
    3e:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
    45:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 7.99
  • Reference cycles: 5.97
  • UOPS_EXECUTED.THREAD: 33.01
  • RETIRE_SLOTS: 25.0
  • UOPS_MITE: 17.0
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 1.6
  • UOPS_PORT_1: 1.6
  • UOPS_PORT_6: 2.14
  • UOPS_PORT_49: 8.0
  • UOPS_PORT_78: 8.0
  • UOPS_PORT_5B: 3.66
  • UOPS_PORT_5B>=2: 0.01
  • UOPS_PORT_23A: 8.01
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     8:	01 
     9:	40                   	rex
     a:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
    11:	00 01 
    13:	40                   	rex
    14:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    1b:	00 01 
    1d:	40                   	rex
    1e:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    25:	00 01 
    27:	40                   	rex
    28:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
    2f:	00 01 
    31:	40                   	rex
    32:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
    39:	00 01 
    3b:	40                   	rex
    3c:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
    43:	00 01 
    45:	40                   	rex
    46:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
    4d:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 7.99
  • Reference cycles: 6.0
  • UOPS_EXECUTED.THREAD: 33.01
  • RETIRE_SLOTS: 25.0
  • UOPS_MITE: 17.0
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 1.6
  • UOPS_PORT_1: 1.6
  • UOPS_PORT_6: 2.14
  • UOPS_PORT_49: 8.01
  • UOPS_PORT_78: 8.0
  • UOPS_PORT_5B: 3.66
  • UOPS_PORT_5B>=2: 0.01
  • UOPS_PORT_23A: 8.01
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=100 and unroll_count=10

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
     8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
     f:	00 01 
    11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    18:	00 01 
    1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    21:	00 01 
    23:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
    2a:	00 01 
    2c:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
    33:	00 01 
    35:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
    3c:	00 01 
    3e:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
    45:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 7.97
  • Reference cycles: 5.95
  • UOPS_EXECUTED.THREAD: 32.1
  • RETIRE_SLOTS: 24.1
  • UOPS_MITE: 16.08
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 1.43
  • UOPS_PORT_1: 1.6
  • UOPS_PORT_6: 1.67
  • UOPS_PORT_49: 8.0
  • UOPS_PORT_78: 8.0
  • UOPS_PORT_5B: 3.41
  • UOPS_PORT_5B>=2: 0.01
  • UOPS_PORT_23A: 8.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 7.99

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     8:	01 
     9:	40                   	rex
     a:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
    11:	00 01 
    13:	40                   	rex
    14:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    1b:	00 01 
    1d:	40                   	rex
    1e:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    25:	00 01 
    27:	40                   	rex
    28:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
    2f:	00 01 
    31:	40                   	rex
    32:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
    39:	00 01 
    3b:	40                   	rex
    3c:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
    43:	00 01 
    45:	40                   	rex
    46:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
    4d:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 8.21
  • Reference cycles: 6.16
  • UOPS_EXECUTED.THREAD: 32.1
  • RETIRE_SLOTS: 24.1
  • UOPS_MITE: 16.08
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 1.43
  • UOPS_PORT_1: 1.6
  • UOPS_PORT_6: 1.67
  • UOPS_PORT_49: 8.0
  • UOPS_PORT_78: 8.0
  • UOPS_PORT_5B: 3.41
  • UOPS_PORT_5B>=2: 0.01
  • UOPS_PORT_23A: 8.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 7.99

With unroll_count=100 and no inner loop

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
     8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
     f:	00 01 
    11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    18:	00 01 
    1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    21:	00 01 
    23:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
    2a:	00 01 
    2c:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
    33:	00 01 
    35:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
    3c:	00 01 
    3e:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
    45:	00 01 
    47:	43 81 44 2e 20 00 00 	add    DWORD PTR [r14+r13*1+0x20],0x1000000
    4e:	00 01 
    50:	43 81 44 2e 24 00 00 	add    DWORD PTR [r14+r13*1+0x24],0x1000000
    57:	00 01 
    59:	43 81 44 2e 28 00 00 	add    DWORD PTR [r14+r13*1+0x28],0x1000000
    60:	00 01 
    62:	43 81 44 2e 2c 00 00 	add    DWORD PTR [r14+r13*1+0x2c],0x1000000
    69:	00 01 
    6b:	43 81 44 2e 30 00 00 	add    DWORD PTR [r14+r13*1+0x30],0x1000000
    72:	00 01 
    74:	43 81 44 2e 34 00 00 	add    DWORD PTR [r14+r13*1+0x34],0x1000000
    7b:	00 01 
    7d:	43 81 44 2e 38 00 00 	add    DWORD PTR [r14+r13*1+0x38],0x1000000
    84:	00 01 
    86:	43 81 44 2e 3c 00 00 	add    DWORD PTR [r14+r13*1+0x3c],0x1000000
    8d:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 16.0
  • Reference cycles: 12.16
  • UOPS_EXECUTED.THREAD: 64.0
  • RETIRE_SLOTS: 48.0
  • UOPS_MITE: 32.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 3.21
  • UOPS_PORT_1: 3.2
  • UOPS_PORT_6: 3.21
  • UOPS_PORT_49: 16.0
  • UOPS_PORT_78: 16.0
  • UOPS_PORT_5B: 6.38
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 16.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.08

With loop_count=1000 and unroll_count=1

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
     8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
     f:	00 01 
    11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    18:	00 01 
    1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    21:	00 01 
    23:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
    2a:	00 01 
    2c:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
    33:	00 01 
    35:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
    3c:	00 01 
    3e:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
    45:	00 01 
    47:	43 81 44 2e 20 00 00 	add    DWORD PTR [r14+r13*1+0x20],0x1000000
    4e:	00 01 
    50:	43 81 44 2e 24 00 00 	add    DWORD PTR [r14+r13*1+0x24],0x1000000
    57:	00 01 
    59:	43 81 44 2e 28 00 00 	add    DWORD PTR [r14+r13*1+0x28],0x1000000
    60:	00 01 
    62:	43 81 44 2e 2c 00 00 	add    DWORD PTR [r14+r13*1+0x2c],0x1000000
    69:	00 01 
    6b:	43 81 44 2e 30 00 00 	add    DWORD PTR [r14+r13*1+0x30],0x1000000
    72:	00 01 
    74:	43 81 44 2e 34 00 00 	add    DWORD PTR [r14+r13*1+0x34],0x1000000
    7b:	00 01 
    7d:	43 81 44 2e 38 00 00 	add    DWORD PTR [r14+r13*1+0x38],0x1000000
    84:	00 01 
    86:	43 81 44 2e 3c 00 00 	add    DWORD PTR [r14+r13*1+0x3c],0x1000000
    8d:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 15.99
  • Reference cycles: 12.0
  • UOPS_EXECUTED.THREAD: 65.01
  • RETIRE_SLOTS: 49.0
  • UOPS_MITE: 33.04
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 3.2
  • UOPS_PORT_1: 3.2
  • UOPS_PORT_6: 4.2
  • UOPS_PORT_49: 16.0
  • UOPS_PORT_78: 16.01
  • UOPS_PORT_5B: 6.41
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 16.01
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     8:	01 
     9:	40                   	rex
     a:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
    11:	00 01 
    13:	40                   	rex
    14:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    1b:	00 01 
    1d:	40                   	rex
    1e:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    25:	00 01 
    27:	40                   	rex
    28:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
    2f:	00 01 
    31:	40                   	rex
    32:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
    39:	00 01 
    3b:	40                   	rex
    3c:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
    43:	00 01 
    45:	40                   	rex
    46:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
    4d:	00 01 
    4f:	40                   	rex
    50:	43 81 44 2e 20 00 00 	add    DWORD PTR [r14+r13*1+0x20],0x1000000
    57:	00 01 
    59:	40                   	rex
    5a:	43 81 44 2e 24 00 00 	add    DWORD PTR [r14+r13*1+0x24],0x1000000
    61:	00 01 
    63:	40                   	rex
    64:	43 81 44 2e 28 00 00 	add    DWORD PTR [r14+r13*1+0x28],0x1000000
    6b:	00 01 
    6d:	40                   	rex
    6e:	43 81 44 2e 2c 00 00 	add    DWORD PTR [r14+r13*1+0x2c],0x1000000
    75:	00 01 
    77:	40                   	rex
    78:	43 81 44 2e 30 00 00 	add    DWORD PTR [r14+r13*1+0x30],0x1000000
    7f:	00 01 
    81:	40                   	rex
    82:	43 81 44 2e 34 00 00 	add    DWORD PTR [r14+r13*1+0x34],0x1000000
    89:	00 01 
    8b:	40                   	rex
    8c:	43 81 44 2e 38 00 00 	add    DWORD PTR [r14+r13*1+0x38],0x1000000
    93:	00 01 
    95:	40                   	rex
    96:	43 81 44 2e 3c 00 00 	add    DWORD PTR [r14+r13*1+0x3c],0x1000000
    9d:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 15.99
  • Reference cycles: 12.0
  • UOPS_EXECUTED.THREAD: 65.01
  • RETIRE_SLOTS: 49.01
  • UOPS_MITE: 33.04
  • UOPS_MS: 0.01
  • UOPS_PORT_0: 3.2
  • UOPS_PORT_1: 3.2
  • UOPS_PORT_6: 4.2
  • UOPS_PORT_49: 16.0
  • UOPS_PORT_78: 16.01
  • UOPS_PORT_5B: 6.41
  • UOPS_PORT_5B>=2: 0.0
  • UOPS_PORT_23A: 16.01
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.01

With loop_count=100 and unroll_count=10

• Code:

     0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     7:	01 
     8:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
     f:	00 01 
    11:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    18:	00 01 
    1a:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    21:	00 01 
    23:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
    2a:	00 01 
    2c:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
    33:	00 01 
    35:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
    3c:	00 01 
    3e:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
    45:	00 01 
    47:	43 81 44 2e 20 00 00 	add    DWORD PTR [r14+r13*1+0x20],0x1000000
    4e:	00 01 
    50:	43 81 44 2e 24 00 00 	add    DWORD PTR [r14+r13*1+0x24],0x1000000
    57:	00 01 
    59:	43 81 44 2e 28 00 00 	add    DWORD PTR [r14+r13*1+0x28],0x1000000
    60:	00 01 
    62:	43 81 44 2e 2c 00 00 	add    DWORD PTR [r14+r13*1+0x2c],0x1000000
    69:	00 01 
    6b:	43 81 44 2e 30 00 00 	add    DWORD PTR [r14+r13*1+0x30],0x1000000
    72:	00 01 
    74:	43 81 44 2e 34 00 00 	add    DWORD PTR [r14+r13*1+0x34],0x1000000
    7b:	00 01 
    7d:	43 81 44 2e 38 00 00 	add    DWORD PTR [r14+r13*1+0x38],0x1000000
    84:	00 01 
    86:	43 81 44 2e 3c 00 00 	add    DWORD PTR [r14+r13*1+0x3c],0x1000000
    8d:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 15.97
  • Reference cycles: 12.02
  • UOPS_EXECUTED.THREAD: 64.1
  • RETIRE_SLOTS: 48.1
  • UOPS_MITE: 32.11
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 3.2
  • UOPS_PORT_1: 3.2
  • UOPS_PORT_6: 3.3
  • UOPS_PORT_49: 16.0
  • UOPS_PORT_78: 16.0
  • UOPS_PORT_5B: 6.4
  • UOPS_PORT_5B>=2: 0.01
  • UOPS_PORT_23A: 16.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

• Code:

     0:	40                   	rex
     1:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
     8:	01 
     9:	40                   	rex
     a:	43 81 44 2e 04 00 00 	add    DWORD PTR [r14+r13*1+0x4],0x1000000
    11:	00 01 
    13:	40                   	rex
    14:	43 81 44 2e 08 00 00 	add    DWORD PTR [r14+r13*1+0x8],0x1000000
    1b:	00 01 
    1d:	40                   	rex
    1e:	43 81 44 2e 0c 00 00 	add    DWORD PTR [r14+r13*1+0xc],0x1000000
    25:	00 01 
    27:	40                   	rex
    28:	43 81 44 2e 10 00 00 	add    DWORD PTR [r14+r13*1+0x10],0x1000000
    2f:	00 01 
    31:	40                   	rex
    32:	43 81 44 2e 14 00 00 	add    DWORD PTR [r14+r13*1+0x14],0x1000000
    39:	00 01 
    3b:	40                   	rex
    3c:	43 81 44 2e 18 00 00 	add    DWORD PTR [r14+r13*1+0x18],0x1000000
    43:	00 01 
    45:	40                   	rex
    46:	43 81 44 2e 1c 00 00 	add    DWORD PTR [r14+r13*1+0x1c],0x1000000
    4d:	00 01 
    4f:	40                   	rex
    50:	43 81 44 2e 20 00 00 	add    DWORD PTR [r14+r13*1+0x20],0x1000000
    57:	00 01 
    59:	40                   	rex
    5a:	43 81 44 2e 24 00 00 	add    DWORD PTR [r14+r13*1+0x24],0x1000000
    61:	00 01 
    63:	40                   	rex
    64:	43 81 44 2e 28 00 00 	add    DWORD PTR [r14+r13*1+0x28],0x1000000
    6b:	00 01 
    6d:	40                   	rex
    6e:	43 81 44 2e 2c 00 00 	add    DWORD PTR [r14+r13*1+0x2c],0x1000000
    75:	00 01 
    77:	40                   	rex
    78:	43 81 44 2e 30 00 00 	add    DWORD PTR [r14+r13*1+0x30],0x1000000
    7f:	00 01 
    81:	40                   	rex
    82:	43 81 44 2e 34 00 00 	add    DWORD PTR [r14+r13*1+0x34],0x1000000
    89:	00 01 
    8b:	40                   	rex
    8c:	43 81 44 2e 38 00 00 	add    DWORD PTR [r14+r13*1+0x38],0x1000000
    93:	00 01 
    95:	40                   	rex
    96:	43 81 44 2e 3c 00 00 	add    DWORD PTR [r14+r13*1+0x3c],0x1000000
    9d:	00 01 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 15.97
  • Reference cycles: 12.0
  • UOPS_EXECUTED.THREAD: 64.1
  • RETIRE_SLOTS: 48.1
  • UOPS_MITE: 32.11
  • UOPS_MS: 0.04
  • UOPS_PORT_0: 3.2
  • UOPS_PORT_1: 3.2
  • UOPS_PORT_6: 3.3
  • UOPS_PORT_49: 16.0
  • UOPS_PORT_78: 16.0
  • UOPS_PORT_5B: 6.4
  • UOPS_PORT_5B>=2: 0.01
  • UOPS_PORT_23A: 16.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0