ADC (RAX, I32)

With unroll_count=500 and no inner loop

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.93
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.19

With loop_count=1000 and unroll_count=10

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.6
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	48 15 00 00 00 01    	adc    rax,0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.6
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.51
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	48 15 00 00 00 01    	adc    rax,0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.51
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	48 15 00 00 00 01    	adc    rax,0x1000000

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.5
- Reference cycles: 0.32
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.35

With loop_count=1000 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	48 15 00 00 00 01    	adc    rax,0x1000000

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 0.55
- Reference cycles: 0.42
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.55
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.55
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	48 15 00 00 00 01    	adc    rax,0x1000000

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 0.55
- Reference cycles: 0.41
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.55
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.55
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	48 15 00 00 00 01    	adc    rax,0x1000000

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 0.51
- Reference cycles: 0.38
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.51
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	48 15 00 00 00 01    	adc    rax,0x1000000

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 0.51
- Reference cycles: 0.38
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.51
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.51
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With JB (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 82 00 00 00 00    	jb     0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.12
- Reference cycles: 0.64
- UOPS_EXECUTED.THREAD: 1.98
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.58
- UOPS_MS: 0.37
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JB (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	72 00                	jb     0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.11
- Reference cycles: 0.64
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.7
- UOPS_MS: 0.36
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JBE (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 86 00 00 00 00    	jbe    0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.11
- Reference cycles: 0.64
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.58
- UOPS_MS: 0.36
- UOPS_PORT_0: 0.94
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.06
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JBE (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	76 00                	jbe    0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.14
- Reference cycles: 1.92
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.67
- UOPS_MS: 0.37
- UOPS_PORT_0: 0.94
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.06
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JL (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 8c 00 00 00 00    	jl     0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.15
- Reference cycles: 1.6
- UOPS_EXECUTED.THREAD: 2.02
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.58
- UOPS_MS: 0.36
- UOPS_PORT_0: 0.96
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JL (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	7c 00                	jl     0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.14
- Reference cycles: 0.64
- UOPS_EXECUTED.THREAD: 2.02
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.74
- UOPS_MS: 0.36
- UOPS_PORT_0: 0.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.02
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JLE (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 8e 00 00 00 00    	jle    0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.11
- Reference cycles: 0.64
- UOPS_EXECUTED.THREAD: 1.98
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.58
- UOPS_MS: 0.37
- UOPS_PORT_0: 0.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.02
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JLE (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	7e 00                	jle    0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.13
- Reference cycles: 0.8
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.67
- UOPS_MS: 0.36
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JNB (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 83 00 00 00 00    	jae    0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.22
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.04
- UOPS_MITE: 0.65
- UOPS_MS: 0.32
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.27

With JNB (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	73 00                	jae    0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.25
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.78
- UOPS_MS: 0.37
- UOPS_PORT_0: 0.96
- UOPS_PORT_1: 0.01
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.32

With JNBE (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 87 00 00 00 00    	ja     0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.22
- Reference cycles: 0.64
- UOPS_EXECUTED.THREAD: 2.02
- RETIRE_SLOTS: 2.04
- UOPS_MITE: 0.51
- UOPS_MS: 0.32
- UOPS_PORT_0: 0.95
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.28

With JNBE (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	77 00                	ja     0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.24
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 1.98
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.82
- UOPS_MS: 0.36
- UOPS_PORT_0: 0.94
- UOPS_PORT_1: 0.01
- UOPS_PORT_6: 1.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.29

With JNL (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 8d 00 00 00 00    	jge    0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.2
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.04
- UOPS_MITE: 0.84
- UOPS_MS: 0.33
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.03
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.23

With JNL (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	7d 00                	jge    0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.27
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.87
- UOPS_MS: 0.37
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.03
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.29

With JNLE (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 8f 00 00 00 00    	jg     0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.22
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.03
- UOPS_MITE: 0.52
- UOPS_MS: 0.34
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.23

With JNLE (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	7f 00                	jg     0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.23
- Reference cycles: 0.64
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.74
- UOPS_MS: 0.36
- UOPS_PORT_0: 0.96
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.29

With JNO (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 81 00 00 00 00    	jno    0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.2
- Reference cycles: 0.8
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.03
- UOPS_MITE: 0.75
- UOPS_MS: 0.34
- UOPS_PORT_0: 0.96
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.29

With JNO (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	71 00                	jno    0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.22
- Reference cycles: 1.12
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.87
- UOPS_MS: 0.37
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.03
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.29

With JNP (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 8b 00 00 00 00    	jnp    0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.13
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.74
- UOPS_MS: 0.37
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JNP (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	7b 00                	jnp    0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.11
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 1.98
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.58
- UOPS_MS: 0.37
- UOPS_PORT_0: 0.98
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.02
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JNS (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 89 00 00 00 00    	jns    0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.21
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 1.98
- RETIRE_SLOTS: 2.04
- UOPS_MITE: 0.56
- UOPS_MS: 0.33
- UOPS_PORT_0: 0.96
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.22

With JNS (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	79 00                	jns    0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.21
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 2.02
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.95
- UOPS_MS: 0.36
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.29

With JNZ (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 85 00 00 00 00    	jne    0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.24
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.03
- UOPS_MITE: 0.6
- UOPS_MS: 0.33
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With JNZ (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	75 00                	jne    0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.28
- Reference cycles: 0.16
- UOPS_EXECUTED.THREAD: 2.02
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.58
- UOPS_MS: 0.36
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.01
- UOPS_PORT_6: 1.03
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.3

With JO (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 80 00 00 00 00    	jo     0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.13
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 2.02
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.74
- UOPS_MS: 0.36
- UOPS_PORT_0: 0.96
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JO (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	70 00                	jo     0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.12
- Reference cycles: 1.92
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.58
- UOPS_MS: 0.36
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JP (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 8a 00 00 00 00    	jp     0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.18
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.03
- UOPS_MITE: 1.1
- UOPS_MS: 0.33
- UOPS_PORT_0: 0.96
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.39

With JP (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	7a 00                	jp     0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.38
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 2.02
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 0.83
- UOPS_MS: 0.36
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.03
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.32

With JS (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 88 00 00 00 00    	js     0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.1
- Reference cycles: 0.8
- UOPS_EXECUTED.THREAD: 2.02
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.74
- UOPS_MS: 0.36
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JS (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	78 00                	js     0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.13
- Reference cycles: 1.12
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.74
- UOPS_MS: 0.37
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JZ (Rel32)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	0f 84 00 00 00 00    	je     0xc

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.12
- Reference cycles: 0.64
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.74
- UOPS_MS: 0.37
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

With JZ (Rel8)

Code:

   0:	48 15 00 00 00 01    	adc    rax,0x1000000
   6:	74 00                	je     0x8

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.12
- Reference cycles: 0.96
- UOPS_EXECUTED.THREAD: 2.02
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.74
- UOPS_MS: 0.36
- UOPS_PORT_0: 0.97
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.04
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.44

ADC (RAX, I32) - Throughput and Uops

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Tests for macro-fusion

With JB (Rel32)

With JB (Rel8)

With JBE (Rel32)

With JBE (Rel8)

With JL (Rel32)

With JL (Rel8)

With JLE (Rel32)

With JLE (Rel8)

With JNB (Rel32)

With JNB (Rel8)

With JNBE (Rel32)

With JNBE (Rel8)

With JNL (Rel32)

With JNL (Rel8)

With JNLE (Rel32)

With JNLE (Rel8)

With JNO (Rel32)

With JNO (Rel8)

With JNP (Rel32)

With JNP (Rel8)

With JNS (Rel32)

With JNS (Rel8)

With JNZ (Rel32)

With JNZ (Rel8)

With JO (Rel32)

With JO (Rel8)

With JP (Rel32)

With JP (Rel8)

With JS (Rel32)

With JS (Rel8)

With JZ (Rel32)

With JZ (Rel8)