ADD (M32, I32) - Port Usage

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	0f 7e c2             	movd   edx,mm0
  1d:	41 0f 7e c0          	movd   r8d,mm0
  21:	41 0f 7e c1          	movd   r9d,mm0
  25:	41 0f 7e c2          	movd   r10d,mm0
  29:	41 0f 7e c3          	movd   r11d,mm0
  2d:	41 0f 7e c4          	movd   r12d,mm0
  31:	0f 7e c3             	movd   ebx,mm0
  34:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:
```
PXOR MM0, MM0
```
Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 14.13
- Reference cycles: 8.23
- UOPS_PORT_0: 14.0

With blocking instructions for port '1':

Code:

   0:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
   7:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
   e:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  15:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  1c:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  23:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  2a:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  31:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  38:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  3f:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  46:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  4d:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  54:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  5b:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  62:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 14.08
- Reference cycles: 8.23
- UOPS_PORT_1: 14.01

With blocking instructions for port '23':

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  81:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  88:	00 00 
  8a:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  91:	00 00 
  93:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  9a:	00 00 
  9c:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  a3:	00 00 
  a5:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  ac:	00 00 
  ae:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  b5:	00 00 
  b7:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  be:	00 00 
  c0:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  c7:	00 00 
  c9:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  d0:	00 00 
  d2:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  d8:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  de:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 14.84
- Reference cycles: 8.34
- UOPS_PORT_23: 29.0

⇨ One μop that can only use port '23'

With blocking instructions for port '49':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  35:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  3c:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  43:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  4a:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  51:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  58:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  5c:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  60:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  64:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  68:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  6c:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  70:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  74:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  78:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  7f:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  86:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  8d:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  94:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 14.99
- Reference cycles: 8.34
- UOPS_PORT_49: 29.0

⇨ One μop that can only use port '49'

With blocking instructions for port '5':

Code:

   0:	66 0f 3a 21 c1 02    	insertps xmm0,xmm1,0x2
   6:	66 0f 3a 21 d1 02    	insertps xmm2,xmm1,0x2
   c:	66 0f 3a 21 d9 02    	insertps xmm3,xmm1,0x2
  12:	66 0f 3a 21 e1 02    	insertps xmm4,xmm1,0x2
  18:	66 0f 3a 21 e9 02    	insertps xmm5,xmm1,0x2
  1e:	66 0f 3a 21 f1 02    	insertps xmm6,xmm1,0x2
  24:	66 0f 3a 21 f9 02    	insertps xmm7,xmm1,0x2
  2a:	66 44 0f 3a 21 c1 02 	insertps xmm8,xmm1,0x2
  31:	66 44 0f 3a 21 c9 02 	insertps xmm9,xmm1,0x2
  38:	66 44 0f 3a 21 d1 02 	insertps xmm10,xmm1,0x2
  3f:	66 44 0f 3a 21 d9 02 	insertps xmm11,xmm1,0x2
  46:	66 44 0f 3a 21 e1 02 	insertps xmm12,xmm1,0x2
  4d:	66 0f 3a 21 c1 02    	insertps xmm0,xmm1,0x2
  53:	66 0f 3a 21 d1 02    	insertps xmm2,xmm1,0x2
  59:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 14.04
- Reference cycles: 8.23
- UOPS_PORT_5: 13.99

With blocking instructions for port '78':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  35:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  3c:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  43:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  4a:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  51:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  58:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  5c:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  60:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  64:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  68:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  6c:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  70:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  74:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  78:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  7f:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  86:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  8d:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  94:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 15.04
- Reference cycles: 10.43
- UOPS_PORT_78: 29.0

⇨ One μop that can only use port '78'

With blocking instructions for ports {'0', '1'}:

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  30:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  35:	66 0f 58 c1          	addpd  xmm0,xmm1
  39:	66 0f 58 d1          	addpd  xmm2,xmm1
  3d:	66 0f 58 d9          	addpd  xmm3,xmm1
  41:	66 0f 58 e1          	addpd  xmm4,xmm1
  45:	66 0f 58 e9          	addpd  xmm5,xmm1
  49:	66 0f 58 f1          	addpd  xmm6,xmm1
  4d:	66 0f 58 f9          	addpd  xmm7,xmm1
  51:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  56:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  5b:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  60:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  65:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  6a:	66 0f 58 c1          	addpd  xmm0,xmm1
  6e:	66 0f 58 d1          	addpd  xmm2,xmm1
  72:	66 0f 58 d9          	addpd  xmm3,xmm1
  76:	66 0f 58 e1          	addpd  xmm4,xmm1
  7a:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 14.43
- Reference cycles: 10.43
- UOPS_PORT_1: 14.06
- UOPS_PORT_0: 13.94

With blocking instructions for ports {'0', '5'}:

Code:

   0:	0f 6f c1             	movq   mm0,mm1
   3:	0f 6f d1             	movq   mm2,mm1
   6:	0f 6f d9             	movq   mm3,mm1
   9:	0f 6f e1             	movq   mm4,mm1
   c:	0f 6f e9             	movq   mm5,mm1
   f:	0f 6f f1             	movq   mm6,mm1
  12:	0f 6f f9             	movq   mm7,mm1
  15:	0f 6f c1             	movq   mm0,mm1
  18:	0f 6f d1             	movq   mm2,mm1
  1b:	0f 6f d9             	movq   mm3,mm1
  1e:	0f 6f e1             	movq   mm4,mm1
  21:	0f 6f e9             	movq   mm5,mm1
  24:	0f 6f f1             	movq   mm6,mm1
  27:	0f 6f f9             	movq   mm7,mm1
  2a:	0f 6f c1             	movq   mm0,mm1
  2d:	0f 6f d1             	movq   mm2,mm1
  30:	0f 6f d9             	movq   mm3,mm1
  33:	0f 6f e1             	movq   mm4,mm1
  36:	0f 6f e9             	movq   mm5,mm1
  39:	0f 6f f1             	movq   mm6,mm1
  3c:	0f 6f f9             	movq   mm7,mm1
  3f:	0f 6f c1             	movq   mm0,mm1
  42:	0f 6f d1             	movq   mm2,mm1
  45:	0f 6f d9             	movq   mm3,mm1
  48:	0f 6f e1             	movq   mm4,mm1
  4b:	0f 6f e9             	movq   mm5,mm1
  4e:	0f 6f f1             	movq   mm6,mm1
  51:	0f 6f f9             	movq   mm7,mm1
  54:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:
```
PXOR MM1, MM1
```
Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 14.29
- Reference cycles: 10.43
- UOPS_PORT_0: 13.97
- UOPS_PORT_5: 14.03

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 c1 c2 00          	rol    dx,0x0
  25:	66 41 c1 c0 00       	rol    r8w,0x0
  2a:	66 41 c1 c1 00       	rol    r9w,0x0
  2f:	66 41 c1 c2 00       	rol    r10w,0x0
  34:	66 41 c1 c3 00       	rol    r11w,0x0
  39:	66 41 c1 c4 00       	rol    r12w,0x0
  3e:	66 c1 c3 00          	rol    bx,0x0
  42:	66 c1 c1 00          	rol    cx,0x0
  46:	66 c1 c2 00          	rol    dx,0x0
  4a:	66 41 c1 c0 00       	rol    r8w,0x0
  4f:	66 41 c1 c1 00       	rol    r9w,0x0
  54:	66 41 c1 c2 00       	rol    r10w,0x0
  59:	66 41 c1 c3 00       	rol    r11w,0x0
  5e:	66 41 c1 c4 00       	rol    r12w,0x0
  63:	66 c1 c3 00          	rol    bx,0x0
  67:	66 c1 c1 00          	rol    cx,0x0
  6b:	66 c1 c2 00          	rol    dx,0x0
  6f:	66 41 c1 c0 00       	rol    r8w,0x0
  74:	66 41 c1 c1 00       	rol    r9w,0x0
  79:	66 41 c1 c2 00       	rol    r10w,0x0
  7e:	66 41 c1 c3 00       	rol    r11w,0x0
  83:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 14.09
- Reference cycles: 10.43
- UOPS_PORT_6: 14.06
- UOPS_PORT_0: 13.94

With blocking instructions for ports {'1', '5'}:

Code:

   0:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
   4:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
   8:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
   c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  10:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  14:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  18:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  1c:	43 8d 14 6e          	lea    edx,[r14+r13*2]
  20:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  24:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  28:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  2c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  30:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  34:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  38:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  3c:	43 8d 14 6e          	lea    edx,[r14+r13*2]
  40:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  44:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  48:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  4c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  50:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  54:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  58:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  5c:	43 8d 14 6e          	lea    edx,[r14+r13*2]
  60:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  64:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  68:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  6c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  70:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 14.09
- Reference cycles: 10.08
- UOPS_PORT_1: 14.0
- UOPS_PORT_5: 14.03

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	66 0f 55 c1          	andnpd xmm0,xmm1
  39:	66 0f 55 d1          	andnpd xmm2,xmm1
  3d:	66 0f 55 d9          	andnpd xmm3,xmm1
  41:	66 0f 55 e1          	andnpd xmm4,xmm1
  45:	66 0f 55 e9          	andnpd xmm5,xmm1
  49:	66 0f 55 f1          	andnpd xmm6,xmm1
  4d:	66 0f 55 f9          	andnpd xmm7,xmm1
  51:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  56:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  5b:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  60:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  65:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  6a:	66 0f 55 c1          	andnpd xmm0,xmm1
  6e:	66 0f 55 d1          	andnpd xmm2,xmm1
  72:	66 0f 55 d9          	andnpd xmm3,xmm1
  76:	66 0f 55 e1          	andnpd xmm4,xmm1
  7a:	66 0f 55 e9          	andnpd xmm5,xmm1
  7e:	66 0f 55 f1          	andnpd xmm6,xmm1
  82:	66 0f 55 f9          	andnpd xmm7,xmm1
  86:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  8b:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  90:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  95:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  9a:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  9f:	66 0f 55 c1          	andnpd xmm0,xmm1
  a3:	66 0f 55 d1          	andnpd xmm2,xmm1
  a7:	66 0f 55 d9          	andnpd xmm3,xmm1
  ab:	66 0f 55 e1          	andnpd xmm4,xmm1
  af:	66 0f 55 e9          	andnpd xmm5,xmm1
  b3:	66 0f 55 f1          	andnpd xmm6,xmm1
  b7:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 43.0
- Core cycles: 14.43
- Reference cycles: 9.52
- UOPS_PORT_1: 13.91
- UOPS_PORT_0: 14.0
- UOPS_PORT_5: 13.96

With blocking instructions for ports {'0', '1', '5', '6'}:

Code:

   0:	45 8d 46 08          	lea    r8d,[r14+0x8]
   4:	45 8d 4e 08          	lea    r9d,[r14+0x8]
   8:	45 8d 56 08          	lea    r10d,[r14+0x8]
   c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  10:	45 8d 66 08          	lea    r12d,[r14+0x8]
  14:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  18:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  1c:	41 8d 56 08          	lea    edx,[r14+0x8]
  20:	45 8d 46 08          	lea    r8d,[r14+0x8]
  24:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  28:	45 8d 56 08          	lea    r10d,[r14+0x8]
  2c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  30:	45 8d 66 08          	lea    r12d,[r14+0x8]
  34:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  38:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  3c:	41 8d 56 08          	lea    edx,[r14+0x8]
  40:	45 8d 46 08          	lea    r8d,[r14+0x8]
  44:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  48:	45 8d 56 08          	lea    r10d,[r14+0x8]
  4c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  50:	45 8d 66 08          	lea    r12d,[r14+0x8]
  54:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  58:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  5c:	41 8d 56 08          	lea    edx,[r14+0x8]
  60:	45 8d 46 08          	lea    r8d,[r14+0x8]
  64:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  68:	45 8d 56 08          	lea    r10d,[r14+0x8]
  6c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  70:	45 8d 66 08          	lea    r12d,[r14+0x8]
  74:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  78:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  7c:	41 8d 56 08          	lea    edx,[r14+0x8]
  80:	45 8d 46 08          	lea    r8d,[r14+0x8]
  84:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  88:	45 8d 56 08          	lea    r10d,[r14+0x8]
  8c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  90:	45 8d 66 08          	lea    r12d,[r14+0x8]
  94:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  98:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  9c:	41 8d 56 08          	lea    edx,[r14+0x8]
  a0:	45 8d 46 08          	lea    r8d,[r14+0x8]
  a4:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  a8:	45 8d 56 08          	lea    r10d,[r14+0x8]
  ac:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  b0:	45 8d 66 08          	lea    r12d,[r14+0x8]
  b4:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  b8:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  bc:	41 8d 56 08          	lea    edx,[r14+0x8]
  c0:	45 8d 46 08          	lea    r8d,[r14+0x8]
  c4:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  c8:	45 8d 56 08          	lea    r10d,[r14+0x8]
  cc:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  d0:	45 8d 66 08          	lea    r12d,[r14+0x8]
  d4:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  d8:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  dc:	41 8d 56 08          	lea    edx,[r14+0x8]
  e0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 57.0
- Core cycles: 15.24
- Reference cycles: 8.59
- UOPS_PORT_1: 14.18
- UOPS_PORT_0: 14.06
- UOPS_PORT_6: 14.41
- UOPS_PORT_5: 14.35

⇨ One μop that can only use ports {'0', '1', '5', '6'}

With an indexed addressing mode

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	0f 7e c2             	movd   edx,mm0
  1d:	41 0f 7e c0          	movd   r8d,mm0
  21:	41 0f 7e c1          	movd   r9d,mm0
  25:	41 0f 7e c2          	movd   r10d,mm0
  29:	41 0f 7e c3          	movd   r11d,mm0
  2d:	41 0f 7e c4          	movd   r12d,mm0
  31:	0f 7e c3             	movd   ebx,mm0
  34:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  3b:	01

Init:
```
PXOR MM0, MM0;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 14.08
- Reference cycles: 8.23
- UOPS_PORT_0: 14.01

With blocking instructions for port '1':

Code:

   0:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
   7:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
   e:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  15:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  1c:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  23:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  2a:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  31:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  38:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  3f:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  46:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  4d:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  54:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  5b:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  62:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  69:	01

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 14.08
- Reference cycles: 8.4
- UOPS_PORT_1: 14.0

With blocking instructions for port '23':

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  81:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  88:	00 00 
  8a:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  91:	00 00 
  93:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  9a:	00 00 
  9c:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  a3:	00 00 
  a5:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  ac:	00 00 
  ae:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  b5:	00 00 
  b7:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  be:	00 00 
  c0:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  c7:	00 00 
  c9:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  d0:	00 00 
  d2:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  d8:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  de:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  e5:	01

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 14.8
- Reference cycles: 8.34
- UOPS_PORT_23: 29.0

⇨ One μop that can only use port '23'

With blocking instructions for port '49':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  35:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  3c:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  43:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  4a:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  51:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  58:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  5c:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  60:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  64:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  68:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  6c:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  70:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  74:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  78:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  7f:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  86:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  8d:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  94:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  9b:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 14.98
- Reference cycles: 8.34
- UOPS_PORT_49: 29.0

⇨ One μop that can only use port '49'

With blocking instructions for port '5':

Code:

   0:	66 0f 3a 21 c1 02    	insertps xmm0,xmm1,0x2
   6:	66 0f 3a 21 d1 02    	insertps xmm2,xmm1,0x2
   c:	66 0f 3a 21 d9 02    	insertps xmm3,xmm1,0x2
  12:	66 0f 3a 21 e1 02    	insertps xmm4,xmm1,0x2
  18:	66 0f 3a 21 e9 02    	insertps xmm5,xmm1,0x2
  1e:	66 0f 3a 21 f1 02    	insertps xmm6,xmm1,0x2
  24:	66 0f 3a 21 f9 02    	insertps xmm7,xmm1,0x2
  2a:	66 44 0f 3a 21 c1 02 	insertps xmm8,xmm1,0x2
  31:	66 44 0f 3a 21 c9 02 	insertps xmm9,xmm1,0x2
  38:	66 44 0f 3a 21 d1 02 	insertps xmm10,xmm1,0x2
  3f:	66 44 0f 3a 21 d9 02 	insertps xmm11,xmm1,0x2
  46:	66 44 0f 3a 21 e1 02 	insertps xmm12,xmm1,0x2
  4d:	66 0f 3a 21 c1 02    	insertps xmm0,xmm1,0x2
  53:	66 0f 3a 21 d1 02    	insertps xmm2,xmm1,0x2
  59:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  60:	01

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 14.08
- Reference cycles: 8.23
- UOPS_PORT_5: 14.0

With blocking instructions for port '78':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  35:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  3c:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  43:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  4a:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  51:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  58:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  5c:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  60:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  64:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  68:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  6c:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  70:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  74:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  78:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  7f:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  86:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  8d:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  94:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  9b:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 14.98
- Reference cycles: 8.34
- UOPS_PORT_78: 29.0

⇨ One μop that can only use port '78'

With blocking instructions for ports {'0', '1'}:

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  30:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  35:	66 0f 58 c1          	addpd  xmm0,xmm1
  39:	66 0f 58 d1          	addpd  xmm2,xmm1
  3d:	66 0f 58 d9          	addpd  xmm3,xmm1
  41:	66 0f 58 e1          	addpd  xmm4,xmm1
  45:	66 0f 58 e9          	addpd  xmm5,xmm1
  49:	66 0f 58 f1          	addpd  xmm6,xmm1
  4d:	66 0f 58 f9          	addpd  xmm7,xmm1
  51:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  56:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  5b:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  60:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  65:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  6a:	66 0f 58 c1          	addpd  xmm0,xmm1
  6e:	66 0f 58 d1          	addpd  xmm2,xmm1
  72:	66 0f 58 d9          	addpd  xmm3,xmm1
  76:	66 0f 58 e1          	addpd  xmm4,xmm1
  7a:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  81:	01

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 14.4
- Reference cycles: 8.34
- UOPS_PORT_1: 14.03
- UOPS_PORT_0: 13.94

With blocking instructions for ports {'0', '5'}:

Code:

   0:	0f 6f c1             	movq   mm0,mm1
   3:	0f 6f d1             	movq   mm2,mm1
   6:	0f 6f d9             	movq   mm3,mm1
   9:	0f 6f e1             	movq   mm4,mm1
   c:	0f 6f e9             	movq   mm5,mm1
   f:	0f 6f f1             	movq   mm6,mm1
  12:	0f 6f f9             	movq   mm7,mm1
  15:	0f 6f c1             	movq   mm0,mm1
  18:	0f 6f d1             	movq   mm2,mm1
  1b:	0f 6f d9             	movq   mm3,mm1
  1e:	0f 6f e1             	movq   mm4,mm1
  21:	0f 6f e9             	movq   mm5,mm1
  24:	0f 6f f1             	movq   mm6,mm1
  27:	0f 6f f9             	movq   mm7,mm1
  2a:	0f 6f c1             	movq   mm0,mm1
  2d:	0f 6f d1             	movq   mm2,mm1
  30:	0f 6f d9             	movq   mm3,mm1
  33:	0f 6f e1             	movq   mm4,mm1
  36:	0f 6f e9             	movq   mm5,mm1
  39:	0f 6f f1             	movq   mm6,mm1
  3c:	0f 6f f9             	movq   mm7,mm1
  3f:	0f 6f c1             	movq   mm0,mm1
  42:	0f 6f d1             	movq   mm2,mm1
  45:	0f 6f d9             	movq   mm3,mm1
  48:	0f 6f e1             	movq   mm4,mm1
  4b:	0f 6f e9             	movq   mm5,mm1
  4e:	0f 6f f1             	movq   mm6,mm1
  51:	0f 6f f9             	movq   mm7,mm1
  54:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  5b:	01

Init:
```
PXOR MM1, MM1;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 14.29
- Reference cycles: 8.34
- UOPS_PORT_0: 13.97
- UOPS_PORT_5: 14.03

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 c1 c2 00          	rol    dx,0x0
  25:	66 41 c1 c0 00       	rol    r8w,0x0
  2a:	66 41 c1 c1 00       	rol    r9w,0x0
  2f:	66 41 c1 c2 00       	rol    r10w,0x0
  34:	66 41 c1 c3 00       	rol    r11w,0x0
  39:	66 41 c1 c4 00       	rol    r12w,0x0
  3e:	66 c1 c3 00          	rol    bx,0x0
  42:	66 c1 c1 00          	rol    cx,0x0
  46:	66 c1 c2 00          	rol    dx,0x0
  4a:	66 41 c1 c0 00       	rol    r8w,0x0
  4f:	66 41 c1 c1 00       	rol    r9w,0x0
  54:	66 41 c1 c2 00       	rol    r10w,0x0
  59:	66 41 c1 c3 00       	rol    r11w,0x0
  5e:	66 41 c1 c4 00       	rol    r12w,0x0
  63:	66 c1 c3 00          	rol    bx,0x0
  67:	66 c1 c1 00          	rol    cx,0x0
  6b:	66 c1 c2 00          	rol    dx,0x0
  6f:	66 41 c1 c0 00       	rol    r8w,0x0
  74:	66 41 c1 c1 00       	rol    r9w,0x0
  79:	66 41 c1 c2 00       	rol    r10w,0x0
  7e:	66 41 c1 c3 00       	rol    r11w,0x0
  83:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  8a:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 14.14
- Reference cycles: 8.34
- UOPS_PORT_6: 14.11
- UOPS_PORT_0: 13.94

With blocking instructions for ports {'1', '5'}:

Code:

   0:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
   4:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
   8:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
   c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  10:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  14:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  18:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  1c:	43 8d 14 6e          	lea    edx,[r14+r13*2]
  20:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  24:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  28:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  2c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  30:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  34:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  38:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  3c:	43 8d 14 6e          	lea    edx,[r14+r13*2]
  40:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  44:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  48:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  4c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  50:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  54:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  58:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  5c:	43 8d 14 6e          	lea    edx,[r14+r13*2]
  60:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  64:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  68:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  6c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  70:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  77:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 14.14
- Reference cycles: 8.34
- UOPS_PORT_1: 13.97
- UOPS_PORT_5: 14.06

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	66 0f 55 c1          	andnpd xmm0,xmm1
  39:	66 0f 55 d1          	andnpd xmm2,xmm1
  3d:	66 0f 55 d9          	andnpd xmm3,xmm1
  41:	66 0f 55 e1          	andnpd xmm4,xmm1
  45:	66 0f 55 e9          	andnpd xmm5,xmm1
  49:	66 0f 55 f1          	andnpd xmm6,xmm1
  4d:	66 0f 55 f9          	andnpd xmm7,xmm1
  51:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  56:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  5b:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  60:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  65:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  6a:	66 0f 55 c1          	andnpd xmm0,xmm1
  6e:	66 0f 55 d1          	andnpd xmm2,xmm1
  72:	66 0f 55 d9          	andnpd xmm3,xmm1
  76:	66 0f 55 e1          	andnpd xmm4,xmm1
  7a:	66 0f 55 e9          	andnpd xmm5,xmm1
  7e:	66 0f 55 f1          	andnpd xmm6,xmm1
  82:	66 0f 55 f9          	andnpd xmm7,xmm1
  86:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  8b:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  90:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  95:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  9a:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  9f:	66 0f 55 c1          	andnpd xmm0,xmm1
  a3:	66 0f 55 d1          	andnpd xmm2,xmm1
  a7:	66 0f 55 d9          	andnpd xmm3,xmm1
  ab:	66 0f 55 e1          	andnpd xmm4,xmm1
  af:	66 0f 55 e9          	andnpd xmm5,xmm1
  b3:	66 0f 55 f1          	andnpd xmm6,xmm1
  b7:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  be:	01

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 43.0
- Core cycles: 14.52
- Reference cycles: 8.46
- UOPS_PORT_1: 14.04
- UOPS_PORT_0: 13.96
- UOPS_PORT_5: 14.0

With blocking instructions for ports {'0', '1', '5', '6'}:

Code:

   0:	45 8d 46 08          	lea    r8d,[r14+0x8]
   4:	45 8d 4e 08          	lea    r9d,[r14+0x8]
   8:	45 8d 56 08          	lea    r10d,[r14+0x8]
   c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  10:	45 8d 66 08          	lea    r12d,[r14+0x8]
  14:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  18:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  1c:	41 8d 56 08          	lea    edx,[r14+0x8]
  20:	45 8d 46 08          	lea    r8d,[r14+0x8]
  24:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  28:	45 8d 56 08          	lea    r10d,[r14+0x8]
  2c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  30:	45 8d 66 08          	lea    r12d,[r14+0x8]
  34:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  38:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  3c:	41 8d 56 08          	lea    edx,[r14+0x8]
  40:	45 8d 46 08          	lea    r8d,[r14+0x8]
  44:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  48:	45 8d 56 08          	lea    r10d,[r14+0x8]
  4c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  50:	45 8d 66 08          	lea    r12d,[r14+0x8]
  54:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  58:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  5c:	41 8d 56 08          	lea    edx,[r14+0x8]
  60:	45 8d 46 08          	lea    r8d,[r14+0x8]
  64:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  68:	45 8d 56 08          	lea    r10d,[r14+0x8]
  6c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  70:	45 8d 66 08          	lea    r12d,[r14+0x8]
  74:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  78:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  7c:	41 8d 56 08          	lea    edx,[r14+0x8]
  80:	45 8d 46 08          	lea    r8d,[r14+0x8]
  84:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  88:	45 8d 56 08          	lea    r10d,[r14+0x8]
  8c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  90:	45 8d 66 08          	lea    r12d,[r14+0x8]
  94:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  98:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  9c:	41 8d 56 08          	lea    edx,[r14+0x8]
  a0:	45 8d 46 08          	lea    r8d,[r14+0x8]
  a4:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  a8:	45 8d 56 08          	lea    r10d,[r14+0x8]
  ac:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  b0:	45 8d 66 08          	lea    r12d,[r14+0x8]
  b4:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  b8:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  bc:	41 8d 56 08          	lea    edx,[r14+0x8]
  c0:	45 8d 46 08          	lea    r8d,[r14+0x8]
  c4:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  c8:	45 8d 56 08          	lea    r10d,[r14+0x8]
  cc:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  d0:	45 8d 66 08          	lea    r12d,[r14+0x8]
  d4:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  d8:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  dc:	41 8d 56 08          	lea    edx,[r14+0x8]
  e0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  e7:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 57.0
- Core cycles: 15.24
- Reference cycles: 8.59
- UOPS_PORT_1: 14.47
- UOPS_PORT_0: 14.06
- UOPS_PORT_6: 14.35
- UOPS_PORT_5: 14.12

⇨ One μop that can only use ports {'0', '1', '5', '6'}