ROL (R32, I8) - Port Usage

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c1          	movd   r9d,mm0
   4:	41 0f 7e c2          	movd   r10d,mm0
   8:	41 0f 7e c3          	movd   r11d,mm0
   c:	41 0f 7e c4          	movd   r12d,mm0
  10:	0f 7e c3             	movd   ebx,mm0
  13:	0f 7e c1             	movd   ecx,mm0
  16:	0f 7e c2             	movd   edx,mm0
  19:	41 0f 7e c1          	movd   r9d,mm0
  1d:	41 0f 7e c2          	movd   r10d,mm0
  21:	41 0f 7e c3          	movd   r11d,mm0
  25:	41 c1 c0 02          	rol    r8d,0x2

Init:
```
PXOR MM0, MM0
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.05
- Reference cycles: 10.14
- UOPS_PORT_0: 10.01

With blocking instructions for port '5':

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	41 c1 c0 02          	rol    r8d,0x2

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.05
- Reference cycles: 9.97
- UOPS_PORT_5: 10.0

With blocking instructions for ports {'0', '1'}:

Code:

   0:	45 8d 0e             	lea    r9d,[r14]
   3:	45 8d 16             	lea    r10d,[r14]
   6:	45 8d 1e             	lea    r11d,[r14]
   9:	45 8d 26             	lea    r12d,[r14]
   c:	41 8d 1e             	lea    ebx,[r14]
   f:	41 8d 0e             	lea    ecx,[r14]
  12:	41 8d 16             	lea    edx,[r14]
  15:	45 8d 0e             	lea    r9d,[r14]
  18:	45 8d 16             	lea    r10d,[r14]
  1b:	45 8d 1e             	lea    r11d,[r14]
  1e:	41 c1 c0 02          	rol    r8d,0x2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.06
- Reference cycles: 4.99
- UOPS_PORT_1: 4.98
- UOPS_PORT_0: 5.02

With blocking instructions for ports {'0', '5'}:

Code:

   0:	66 41 c1 f9 00       	sar    r9w,0x0
   5:	66 41 c1 fa 00       	sar    r10w,0x0
   a:	66 41 c1 fb 00       	sar    r11w,0x0
   f:	66 41 c1 fc 00       	sar    r12w,0x0
  14:	66 c1 fb 00          	sar    bx,0x0
  18:	66 c1 f9 00          	sar    cx,0x0
  1c:	66 c1 fa 00          	sar    dx,0x0
  20:	66 41 c1 f9 00       	sar    r9w,0x0
  25:	66 41 c1 fa 00       	sar    r10w,0x0
  2a:	66 41 c1 fb 00       	sar    r11w,0x0
  2f:	41 c1 c0 02          	rol    r8d,0x2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 6.06
- Reference cycles: 6.12
- UOPS_PORT_5: 5.99
- UOPS_PORT_0: 6.02

⇨ 2 μops that can only use ports {'0', '5'}