PCMPESTRM (XMM, XMM, I8) - Port Usage

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	41 0f 7e c0          	movd   r8d,mm0
  1e:	41 0f 7e c1          	movd   r9d,mm0
  22:	41 0f 7e c2          	movd   r10d,mm0
  26:	66 0f 3a 60 ca 02    	pcmpestrm xmm1,xmm2,0x2

Init:

PXOR MM0, MM0;
VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 13.13
- Reference cycles: 13.26
- UOPS_PORT_0: 13.0

⇨ 3 μops that can only use port '0'

With blocking instructions for port '1':

Code:

   0:	66 0f 58 dc          	addpd  xmm3,xmm4
   4:	66 0f 58 ec          	addpd  xmm5,xmm4
   8:	66 0f 58 f4          	addpd  xmm6,xmm4
   c:	66 0f 58 fc          	addpd  xmm7,xmm4
  10:	66 44 0f 58 c4       	addpd  xmm8,xmm4
  15:	66 44 0f 58 cc       	addpd  xmm9,xmm4
  1a:	66 44 0f 58 d4       	addpd  xmm10,xmm4
  1f:	66 44 0f 58 dc       	addpd  xmm11,xmm4
  24:	66 44 0f 58 e4       	addpd  xmm12,xmm4
  29:	66 0f 58 dc          	addpd  xmm3,xmm4
  2d:	66 0f 3a 60 ca 02    	pcmpestrm xmm1,xmm2,0x2

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14];
PXOR XMM1, XMM1;
PXOR XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.25
- Reference cycles: 11.33
- UOPS_PORT_1: 10.99

⇨ One μop that can only use port '1'

With blocking instructions for port '5':

Code:

   0:	66 0f 55 dc          	andnpd xmm3,xmm4
   4:	66 0f 55 ec          	andnpd xmm5,xmm4
   8:	66 0f 55 f4          	andnpd xmm6,xmm4
   c:	66 0f 55 fc          	andnpd xmm7,xmm4
  10:	66 44 0f 55 c4       	andnpd xmm8,xmm4
  15:	66 44 0f 55 cc       	andnpd xmm9,xmm4
  1a:	66 44 0f 55 d4       	andnpd xmm10,xmm4
  1f:	66 44 0f 55 dc       	andnpd xmm11,xmm4
  24:	66 44 0f 55 e4       	andnpd xmm12,xmm4
  29:	66 0f 55 dc          	andnpd xmm3,xmm4
  2d:	66 0f 3a 60 ca 02    	pcmpestrm xmm1,xmm2,0x2

Init:

VZEROALL;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 13.21
- Reference cycles: 13.15
- UOPS_PORT_5: 12.99

⇨ 3 μops that can only use port '5'

With blocking instructions for ports {'0', '5'}:

Code:

   0:	66 41 c1 f8 00       	sar    r8w,0x0
   5:	66 41 c1 f9 00       	sar    r9w,0x0
   a:	66 41 c1 fa 00       	sar    r10w,0x0
   f:	66 41 c1 fb 00       	sar    r11w,0x0
  14:	66 41 c1 fc 00       	sar    r12w,0x0
  19:	66 c1 fb 00          	sar    bx,0x0
  1d:	66 c1 f9 00          	sar    cx,0x0
  21:	66 41 c1 f8 00       	sar    r8w,0x0
  26:	66 41 c1 f9 00       	sar    r9w,0x0
  2b:	66 41 c1 fa 00       	sar    r10w,0x0
  30:	66 41 c1 fb 00       	sar    r11w,0x0
  35:	66 41 c1 fc 00       	sar    r12w,0x0
  3a:	66 c1 fb 00          	sar    bx,0x0
  3e:	66 c1 f9 00          	sar    cx,0x0
  42:	66 41 c1 f8 00       	sar    r8w,0x0
  47:	66 41 c1 f9 00       	sar    r9w,0x0
  4c:	66 0f 3a 60 ca 02    	pcmpestrm xmm1,xmm2,0x2

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 12.1
- Reference cycles: 11.88
- UOPS_PORT_5: 11.77
- UOPS_PORT_0: 11.24

⇨ One μop that can only use ports {'0', '5'}