MOVSB_REPE - Port Usage

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c2             	movd   edx,mm0
  1a:	41 0f 7e c0          	movd   r8d,mm0
  1e:	41 0f 7e c1          	movd   r9d,mm0
  22:	41 0f 7e c2          	movd   r10d,mm0
  26:	41 0f 7e c3          	movd   r11d,mm0
  2a:	41 0f 7e c4          	movd   r12d,mm0
  2e:	0f 7e c3             	movd   ebx,mm0
  31:	0f 7e c2             	movd   edx,mm0
  34:	41 0f 7e c0          	movd   r8d,mm0
  38:	41 0f 7e c1          	movd   r9d,mm0
  3c:	41 0f 7e c2          	movd   r10d,mm0
  40:	41 0f 7e c3          	movd   r11d,mm0
  44:	41 0f 7e c4          	movd   r12d,mm0
  48:	0f 7e c3             	movd   ebx,mm0
  4b:	0f 7e c2             	movd   edx,mm0
  4e:	41 0f 7e c0          	movd   r8d,mm0
  52:	41 0f 7e c1          	movd   r9d,mm0
  56:	48 c7 c1 02 00 00 00 	mov    rcx,0x2
  5d:	f3 a4                	rep movs BYTE PTR es:[rdi],BYTE PTR ds:[rsi]

Init:
```
PXOR MM0, MM0
```
Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 23.26
- Reference cycles: 23.46
- UOPS_PORT_0: 23.02

With blocking instructions for port '1':

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  30:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  35:	66 0f 58 c1          	addpd  xmm0,xmm1
  39:	66 0f 58 d1          	addpd  xmm2,xmm1
  3d:	66 0f 58 d9          	addpd  xmm3,xmm1
  41:	66 0f 58 e1          	addpd  xmm4,xmm1
  45:	66 0f 58 e9          	addpd  xmm5,xmm1
  49:	66 0f 58 f1          	addpd  xmm6,xmm1
  4d:	66 0f 58 f9          	addpd  xmm7,xmm1
  51:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  56:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  5b:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  60:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  65:	48 c7 c1 02 00 00 00 	mov    rcx,0x2
  6c:	f3 a4                	rep movs BYTE PTR es:[rdi],BYTE PTR ds:[rsi]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 23.58
- Reference cycles: 23.59
- UOPS_PORT_1: 22.98

With blocking instructions for port '4':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  35:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  3c:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  43:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  4a:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  51:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  58:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  5c:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  60:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  64:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  68:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  6c:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  70:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  74:	48 c7 c1 02 00 00 00 	mov    rcx,0x2
  7b:	f3 a4                	rep movs BYTE PTR es:[rdi],BYTE PTR ds:[rsi]

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 28.26
- Reference cycles: 28.33
- UOPS_PORT_4: 26.0

⇨ 3 μops that can only use port '4'

With blocking instructions for port '5':

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	66 0f 55 c1          	andnpd xmm0,xmm1
  39:	66 0f 55 d1          	andnpd xmm2,xmm1
  3d:	66 0f 55 d9          	andnpd xmm3,xmm1
  41:	66 0f 55 e1          	andnpd xmm4,xmm1
  45:	66 0f 55 e9          	andnpd xmm5,xmm1
  49:	66 0f 55 f1          	andnpd xmm6,xmm1
  4d:	66 0f 55 f9          	andnpd xmm7,xmm1
  51:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  56:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  5b:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  60:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  65:	48 c7 c1 02 00 00 00 	mov    rcx,0x2
  6c:	f3 a4                	rep movs BYTE PTR es:[rdi],BYTE PTR ds:[rsi]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 25.21
- Reference cycles: 25.04
- UOPS_PORT_5: 25.0

⇨ 2 μops that can only use port '5'

With blocking instructions for ports {'0', '1'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 16             	lea    edx,[r14]
  15:	45 8d 06             	lea    r8d,[r14]
  18:	45 8d 0e             	lea    r9d,[r14]
  1b:	45 8d 16             	lea    r10d,[r14]
  1e:	45 8d 1e             	lea    r11d,[r14]
  21:	45 8d 26             	lea    r12d,[r14]
  24:	41 8d 1e             	lea    ebx,[r14]
  27:	41 8d 16             	lea    edx,[r14]
  2a:	45 8d 06             	lea    r8d,[r14]
  2d:	45 8d 0e             	lea    r9d,[r14]
  30:	45 8d 16             	lea    r10d,[r14]
  33:	45 8d 1e             	lea    r11d,[r14]
  36:	45 8d 26             	lea    r12d,[r14]
  39:	41 8d 1e             	lea    ebx,[r14]
  3c:	41 8d 16             	lea    edx,[r14]
  3f:	45 8d 06             	lea    r8d,[r14]
  42:	45 8d 0e             	lea    r9d,[r14]
  45:	45 8d 16             	lea    r10d,[r14]
  48:	45 8d 1e             	lea    r11d,[r14]
  4b:	45 8d 26             	lea    r12d,[r14]
  4e:	41 8d 1e             	lea    ebx,[r14]
  51:	41 8d 16             	lea    edx,[r14]
  54:	45 8d 06             	lea    r8d,[r14]
  57:	45 8d 0e             	lea    r9d,[r14]
  5a:	45 8d 16             	lea    r10d,[r14]
  5d:	45 8d 1e             	lea    r11d,[r14]
  60:	45 8d 26             	lea    r12d,[r14]
  63:	41 8d 1e             	lea    ebx,[r14]
  66:	41 8d 16             	lea    edx,[r14]
  69:	45 8d 06             	lea    r8d,[r14]
  6c:	45 8d 0e             	lea    r9d,[r14]
  6f:	45 8d 16             	lea    r10d,[r14]
  72:	45 8d 1e             	lea    r11d,[r14]
  75:	45 8d 26             	lea    r12d,[r14]
  78:	41 8d 1e             	lea    ebx,[r14]
  7b:	41 8d 16             	lea    edx,[r14]
  7e:	45 8d 06             	lea    r8d,[r14]
  81:	45 8d 0e             	lea    r9d,[r14]
  84:	45 8d 16             	lea    r10d,[r14]
  87:	45 8d 1e             	lea    r11d,[r14]
  8a:	48 c7 c1 02 00 00 00 	mov    rcx,0x2
  91:	f3 a4                	rep movs BYTE PTR es:[rdi],BYTE PTR ds:[rsi]

Show nanoBench command
Results:
- Instructions retired: 48.0
- Core cycles: 24.02
- Reference cycles: 24.02
- UOPS_PORT_1: 23.33
- UOPS_PORT_0: 23.48

⇨ One μop that can only use ports {'0', '1'}

With blocking instructions for ports {'0', '5'}:

Code:

   0:	66 41 c1 f8 00       	sar    r8w,0x0
   5:	66 41 c1 f9 00       	sar    r9w,0x0
   a:	66 41 c1 fa 00       	sar    r10w,0x0
   f:	66 41 c1 fb 00       	sar    r11w,0x0
  14:	66 41 c1 fc 00       	sar    r12w,0x0
  19:	66 c1 fb 00          	sar    bx,0x0
  1d:	66 c1 fa 00          	sar    dx,0x0
  21:	66 41 c1 f8 00       	sar    r8w,0x0
  26:	66 41 c1 f9 00       	sar    r9w,0x0
  2b:	66 41 c1 fa 00       	sar    r10w,0x0
  30:	66 41 c1 fb 00       	sar    r11w,0x0
  35:	66 41 c1 fc 00       	sar    r12w,0x0
  3a:	66 c1 fb 00          	sar    bx,0x0
  3e:	66 c1 fa 00          	sar    dx,0x0
  42:	66 41 c1 f8 00       	sar    r8w,0x0
  47:	66 41 c1 f9 00       	sar    r9w,0x0
  4c:	66 41 c1 fa 00       	sar    r10w,0x0
  51:	66 41 c1 fb 00       	sar    r11w,0x0
  56:	66 41 c1 fc 00       	sar    r12w,0x0
  5b:	66 c1 fb 00          	sar    bx,0x0
  5f:	66 c1 fa 00          	sar    dx,0x0
  63:	66 41 c1 f8 00       	sar    r8w,0x0
  68:	66 41 c1 f9 00       	sar    r9w,0x0
  6d:	66 41 c1 fa 00       	sar    r10w,0x0
  72:	66 41 c1 fb 00       	sar    r11w,0x0
  77:	66 41 c1 fc 00       	sar    r12w,0x0
  7c:	66 c1 fb 00          	sar    bx,0x0
  80:	66 c1 fa 00          	sar    dx,0x0
  84:	66 41 c1 f8 00       	sar    r8w,0x0
  89:	66 41 c1 f9 00       	sar    r9w,0x0
  8e:	66 41 c1 fa 00       	sar    r10w,0x0
  93:	66 41 c1 fb 00       	sar    r11w,0x0
  98:	66 41 c1 fc 00       	sar    r12w,0x0
  9d:	66 c1 fb 00          	sar    bx,0x0
  a1:	66 c1 fa 00          	sar    dx,0x0
  a5:	66 41 c1 f8 00       	sar    r8w,0x0
  aa:	66 41 c1 f9 00       	sar    r9w,0x0
  af:	66 41 c1 fa 00       	sar    r10w,0x0
  b4:	66 41 c1 fb 00       	sar    r11w,0x0
  b9:	66 41 c1 fc 00       	sar    r12w,0x0
  be:	66 c1 fb 00          	sar    bx,0x0
  c2:	66 c1 fa 00          	sar    dx,0x0
  c6:	66 41 c1 f8 00       	sar    r8w,0x0
  cb:	66 41 c1 f9 00       	sar    r9w,0x0
  d0:	66 41 c1 fa 00       	sar    r10w,0x0
  d5:	66 41 c1 fb 00       	sar    r11w,0x0
  da:	48 c7 c1 02 00 00 00 	mov    rcx,0x2
  e1:	f3 a4                	rep movs BYTE PTR es:[rdi],BYTE PTR ds:[rsi]

Show nanoBench command
Results:
- Instructions retired: 48.0
- Core cycles: 25.0
- Reference cycles: 25.64
- UOPS_PORT_5: 24.52
- UOPS_PORT_0: 24.52

⇨ One μop that can only use ports {'0', '5'}

With blocking instructions for ports {'1', '5'}:

Code:

   0:	0f 38 1c c1          	pabsb  mm0,mm1
   4:	0f 38 1c d1          	pabsb  mm2,mm1
   8:	0f 38 1c d9          	pabsb  mm3,mm1
   c:	0f 38 1c e1          	pabsb  mm4,mm1
  10:	0f 38 1c e9          	pabsb  mm5,mm1
  14:	0f 38 1c f1          	pabsb  mm6,mm1
  18:	0f 38 1c f9          	pabsb  mm7,mm1
  1c:	0f 38 1c c1          	pabsb  mm0,mm1
  20:	0f 38 1c d1          	pabsb  mm2,mm1
  24:	0f 38 1c d9          	pabsb  mm3,mm1
  28:	0f 38 1c e1          	pabsb  mm4,mm1
  2c:	0f 38 1c e9          	pabsb  mm5,mm1
  30:	0f 38 1c f1          	pabsb  mm6,mm1
  34:	0f 38 1c f9          	pabsb  mm7,mm1
  38:	0f 38 1c c1          	pabsb  mm0,mm1
  3c:	0f 38 1c d1          	pabsb  mm2,mm1
  40:	0f 38 1c d9          	pabsb  mm3,mm1
  44:	0f 38 1c e1          	pabsb  mm4,mm1
  48:	0f 38 1c e9          	pabsb  mm5,mm1
  4c:	0f 38 1c f1          	pabsb  mm6,mm1
  50:	0f 38 1c f9          	pabsb  mm7,mm1
  54:	0f 38 1c c1          	pabsb  mm0,mm1
  58:	0f 38 1c d1          	pabsb  mm2,mm1
  5c:	0f 38 1c d9          	pabsb  mm3,mm1
  60:	0f 38 1c e1          	pabsb  mm4,mm1
  64:	0f 38 1c e9          	pabsb  mm5,mm1
  68:	0f 38 1c f1          	pabsb  mm6,mm1
  6c:	0f 38 1c f9          	pabsb  mm7,mm1
  70:	0f 38 1c c1          	pabsb  mm0,mm1
  74:	0f 38 1c d1          	pabsb  mm2,mm1
  78:	0f 38 1c d9          	pabsb  mm3,mm1
  7c:	0f 38 1c e1          	pabsb  mm4,mm1
  80:	0f 38 1c e9          	pabsb  mm5,mm1
  84:	0f 38 1c f1          	pabsb  mm6,mm1
  88:	0f 38 1c f9          	pabsb  mm7,mm1
  8c:	0f 38 1c c1          	pabsb  mm0,mm1
  90:	0f 38 1c d1          	pabsb  mm2,mm1
  94:	0f 38 1c d9          	pabsb  mm3,mm1
  98:	0f 38 1c e1          	pabsb  mm4,mm1
  9c:	0f 38 1c e9          	pabsb  mm5,mm1
  a0:	0f 38 1c f1          	pabsb  mm6,mm1
  a4:	0f 38 1c f9          	pabsb  mm7,mm1
  a8:	0f 38 1c c1          	pabsb  mm0,mm1
  ac:	0f 38 1c d1          	pabsb  mm2,mm1
  b0:	0f 38 1c d9          	pabsb  mm3,mm1
  b4:	0f 38 1c e1          	pabsb  mm4,mm1
  b8:	48 c7 c1 02 00 00 00 	mov    rcx,0x2
  bf:	f3 a4                	rep movs BYTE PTR es:[rdi],BYTE PTR ds:[rsi]

Init:
```
VZEROALL;
PXOR MM1, MM1
```
Show nanoBench command
Results:
- Instructions retired: 48.0
- Core cycles: 24.52
- Reference cycles: 24.83
- UOPS_PORT_5: 24.02
- UOPS_PORT_1: 23.93

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  81:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  88:	00 00 
  8a:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  91:	00 00 
  93:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  9a:	00 00 
  9c:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  a3:	00 00 
  a5:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  ac:	00 00 
  ae:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  b5:	00 00 
  b7:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  be:	00 00 
  c0:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  c7:	00 00 
  c9:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  d0:	00 00 
  d2:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  d8:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  de:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  e4:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  ea:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  f1:	00 00 
  f3:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  fa:	00 00 
  fc:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 103:	00 00 
 105:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 10c:	00 00 
 10e:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 115:	00 00 
 117:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 11e:	00 00 
 120:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 127:	00 00 
 129:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 130:	00 00 
 132:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 139:	00 00 
 13b:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 141:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 147:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 14d:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 153:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 15a:	00 00 
 15c:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 163:	00 00 
 165:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 16c:	00 00 
 16e:	48 c7 c1 02 00 00 00 	mov    rcx,0x2
 175:	f3 a4                	rep movs BYTE PTR es:[rdi],BYTE PTR ds:[rsi]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 48.0
- Core cycles: 29.16
- Reference cycles: 28.87
- UOPS_PORT_2: 25.57
- UOPS_PORT_3: 26.38

⇨ 6 μops that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	41 b0 00             	mov    r8b,0x0
   3:	41 b1 00             	mov    r9b,0x0
   6:	41 b2 00             	mov    r10b,0x0
   9:	41 b3 00             	mov    r11b,0x0
   c:	41 b4 00             	mov    r12b,0x0
   f:	b3 00                	mov    bl,0x0
  11:	b2 00                	mov    dl,0x0
  13:	41 b0 00             	mov    r8b,0x0
  16:	41 b1 00             	mov    r9b,0x0
  19:	41 b2 00             	mov    r10b,0x0
  1c:	41 b3 00             	mov    r11b,0x0
  1f:	41 b4 00             	mov    r12b,0x0
  22:	b3 00                	mov    bl,0x0
  24:	b2 00                	mov    dl,0x0
  26:	41 b0 00             	mov    r8b,0x0
  29:	41 b1 00             	mov    r9b,0x0
  2c:	41 b2 00             	mov    r10b,0x0
  2f:	41 b3 00             	mov    r11b,0x0
  32:	41 b4 00             	mov    r12b,0x0
  35:	b3 00                	mov    bl,0x0
  37:	b2 00                	mov    dl,0x0
  39:	41 b0 00             	mov    r8b,0x0
  3c:	41 b1 00             	mov    r9b,0x0
  3f:	41 b2 00             	mov    r10b,0x0
  42:	41 b3 00             	mov    r11b,0x0
  45:	41 b4 00             	mov    r12b,0x0
  48:	b3 00                	mov    bl,0x0
  4a:	b2 00                	mov    dl,0x0
  4c:	41 b0 00             	mov    r8b,0x0
  4f:	41 b1 00             	mov    r9b,0x0
  52:	41 b2 00             	mov    r10b,0x0
  55:	41 b3 00             	mov    r11b,0x0
  58:	41 b4 00             	mov    r12b,0x0
  5b:	b3 00                	mov    bl,0x0
  5d:	b2 00                	mov    dl,0x0
  5f:	41 b0 00             	mov    r8b,0x0
  62:	41 b1 00             	mov    r9b,0x0
  65:	41 b2 00             	mov    r10b,0x0
  68:	41 b3 00             	mov    r11b,0x0
  6b:	41 b4 00             	mov    r12b,0x0
  6e:	b3 00                	mov    bl,0x0
  70:	b2 00                	mov    dl,0x0
  72:	41 b0 00             	mov    r8b,0x0
  75:	41 b1 00             	mov    r9b,0x0
  78:	41 b2 00             	mov    r10b,0x0
  7b:	41 b3 00             	mov    r11b,0x0
  7e:	41 b4 00             	mov    r12b,0x0
  81:	b3 00                	mov    bl,0x0
  83:	b2 00                	mov    dl,0x0
  85:	41 b0 00             	mov    r8b,0x0
  88:	41 b1 00             	mov    r9b,0x0
  8b:	41 b2 00             	mov    r10b,0x0
  8e:	41 b3 00             	mov    r11b,0x0
  91:	41 b4 00             	mov    r12b,0x0
  94:	b3 00                	mov    bl,0x0
  96:	b2 00                	mov    dl,0x0
  98:	41 b0 00             	mov    r8b,0x0
  9b:	41 b1 00             	mov    r9b,0x0
  9e:	41 b2 00             	mov    r10b,0x0
  a1:	41 b3 00             	mov    r11b,0x0
  a4:	41 b4 00             	mov    r12b,0x0
  a7:	b3 00                	mov    bl,0x0
  a9:	b2 00                	mov    dl,0x0
  ab:	41 b0 00             	mov    r8b,0x0
  ae:	41 b1 00             	mov    r9b,0x0
  b1:	41 b2 00             	mov    r10b,0x0
  b4:	41 b3 00             	mov    r11b,0x0
  b7:	41 b4 00             	mov    r12b,0x0
  ba:	b3 00                	mov    bl,0x0
  bc:	48 c7 c1 02 00 00 00 	mov    rcx,0x2
  c3:	f3 a4                	rep movs BYTE PTR es:[rdi],BYTE PTR ds:[rsi]

Show nanoBench command
Results:
- Instructions retired: 71.0
- Core cycles: 32.36
- Reference cycles: 31.17
- UOPS_PORT_5: 27.0
- UOPS_PORT_1: 27.86
- UOPS_PORT_0: 28.14

⇨ 9 μops that can only use ports {'0', '1', '5'}