VSQRTSD (XMM, K, XMM, M64) - Port Usage

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	0f 7e c2             	movd   edx,mm0
  1d:	41 0f 7e c0          	movd   r8d,mm0
  21:	41 0f 7e c1          	movd   r9d,mm0
  25:	41 0f 7e c2          	movd   r10d,mm0
  29:	41 0f 7e c3          	movd   r11d,mm0
  2d:	41 0f 7e c4          	movd   r12d,mm0
  31:	0f 7e c3             	movd   ebx,mm0
  34:	0f 7e c1             	movd   ecx,mm0
  37:	0f 7e c2             	movd   edx,mm0
  3a:	41 0f 7e c0          	movd   r8d,mm0
  3e:	41 0f 7e c1          	movd   r9d,mm0
  42:	41 0f 7e c2          	movd   r10d,mm0
  46:	41 0f 7e c3          	movd   r11d,mm0
  4a:	41 0f 7e c4          	movd   r12d,mm0
  4e:	0f 7e c3             	movd   ebx,mm0
  51:	0f 7e c1             	movd   ecx,mm0
  54:	0f 7e c2             	movd   edx,mm0
  57:	41 0f 7e c0          	movd   r8d,mm0
  5b:	41 0f 7e c1          	movd   r9d,mm0
  5f:	62 d1 ff 09 51 16    	vsqrtsd xmm2{k1},xmm0,QWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
PXOR MM0, MM0;
VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX

Show nanoBench command
Results:
- Instructions retired: 27.0
- Core cycles: 27.47
- Reference cycles: 24.33
- UOPS_PORT_0: 26.97

⇨ One μop that can only use port '0'

With blocking instructions for ports {'2', '3'}:

Code:

   0:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
   4:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
   8:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
   c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  10:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  14:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  18:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  1c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  20:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  24:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
  28:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
  2c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  30:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  34:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  38:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  3c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  40:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  44:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
  48:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
  4c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  50:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  54:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  58:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  5c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  60:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  64:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
  68:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
  6c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  70:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  74:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  78:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  7c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  80:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  84:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
  88:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
  8c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  90:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  94:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  98:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  9c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  a0:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  a4:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
  a8:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
  ac:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  b0:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  b4:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  b8:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  bc:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  c0:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  c4:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
  c8:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
  cc:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  d0:	62 d1 ff 09 51 16    	vsqrtsd xmm2{k1},xmm0,QWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX

Show nanoBench command
Results:
- Instructions retired: 53.0
- Core cycles: 27.63
- Reference cycles: 23.05
- UOPS_PORT_3: 26.5
- UOPS_PORT_2: 26.5

⇨ One μop that can only use ports {'2', '3'}

With an indexed addressing mode

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	0f 7e c2             	movd   edx,mm0
  1d:	41 0f 7e c0          	movd   r8d,mm0
  21:	41 0f 7e c1          	movd   r9d,mm0
  25:	41 0f 7e c2          	movd   r10d,mm0
  29:	41 0f 7e c3          	movd   r11d,mm0
  2d:	41 0f 7e c4          	movd   r12d,mm0
  31:	0f 7e c3             	movd   ebx,mm0
  34:	0f 7e c1             	movd   ecx,mm0
  37:	0f 7e c2             	movd   edx,mm0
  3a:	41 0f 7e c0          	movd   r8d,mm0
  3e:	41 0f 7e c1          	movd   r9d,mm0
  42:	41 0f 7e c2          	movd   r10d,mm0
  46:	41 0f 7e c3          	movd   r11d,mm0
  4a:	41 0f 7e c4          	movd   r12d,mm0
  4e:	0f 7e c3             	movd   ebx,mm0
  51:	0f 7e c1             	movd   ecx,mm0
  54:	0f 7e c2             	movd   edx,mm0
  57:	41 0f 7e c0          	movd   r8d,mm0
  5b:	41 0f 7e c1          	movd   r9d,mm0
  5f:	62 d1 ff 09 51 16    	vsqrtsd xmm2{k1},xmm0,QWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
PXOR MM0, MM0;
VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX

Show nanoBench command
Results:
- Instructions retired: 27.0
- Core cycles: 27.5
- Reference cycles: 24.97
- UOPS_PORT_0: 26.97

⇨ One μop that can only use port '0'

With blocking instructions for ports {'2', '3'}:

Code:

   0:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
   4:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
   8:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
   c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  10:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  14:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  18:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  1c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  20:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  24:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
  28:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
  2c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  30:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  34:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  38:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  3c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  40:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  44:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
  48:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
  4c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  50:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  54:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  58:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  5c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  60:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  64:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
  68:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
  6c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  70:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  74:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  78:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  7c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  80:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  84:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
  88:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
  8c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  90:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  94:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  98:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  9c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  a0:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  a4:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
  a8:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
  ac:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  b0:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  b4:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  b8:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  bc:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  c0:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  c4:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
  c8:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
  cc:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  d0:	62 d1 ff 09 51 16    	vsqrtsd xmm2{k1},xmm0,QWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX

Show nanoBench command
Results:
- Instructions retired: 53.0
- Core cycles: 27.63
- Reference cycles: 29.46
- UOPS_PORT_3: 26.5
- UOPS_PORT_2: 26.5

⇨ One μop that can only use ports {'2', '3'}