DIVPS (XMM, M128) - Port Usage

With blocking instructions for port '0':

Code:

   0:	66 0f 38 de c1       	aesdec xmm0,xmm1
   5:	66 0f 38 de d9       	aesdec xmm3,xmm1
   a:	66 0f 38 de e1       	aesdec xmm4,xmm1
   f:	66 0f 38 de e9       	aesdec xmm5,xmm1
  14:	66 0f 38 de f1       	aesdec xmm6,xmm1
  19:	66 0f 38 de f9       	aesdec xmm7,xmm1
  1e:	66 44 0f 38 de c1    	aesdec xmm8,xmm1
  24:	66 44 0f 38 de c9    	aesdec xmm9,xmm1
  2a:	66 44 0f 38 de d1    	aesdec xmm10,xmm1
  30:	66 44 0f 38 de d9    	aesdec xmm11,xmm1
  36:	0f 10 d1             	movups xmm2,xmm1
  39:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 11.17
- Reference cycles: 8.76
- UOPS_PORT_0: 11.0

⇨ One μop that can only use port '0'

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  12:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  18:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
  31:	00 00 
  33:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 9e e0 00 	lddqu  xmm11,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 a6 f0 00 	lddqu  xmm12,[r14+0xf0]
  5e:	00 00 
  60:	0f 10 d1             	movups xmm2,xmm1
  63:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 6.76
- Reference cycles: 5.28
- UOPS_PORT_3: 6.5
- UOPS_PORT_2: 6.5

⇨ One μop that can only use ports {'2', '3'}

With an indexed addressing mode

With blocking instructions for port '0':

Code:

   0:	66 0f 38 de c1       	aesdec xmm0,xmm1
   5:	66 0f 38 de d9       	aesdec xmm3,xmm1
   a:	66 0f 38 de e1       	aesdec xmm4,xmm1
   f:	66 0f 38 de e9       	aesdec xmm5,xmm1
  14:	66 0f 38 de f1       	aesdec xmm6,xmm1
  19:	66 0f 38 de f9       	aesdec xmm7,xmm1
  1e:	66 44 0f 38 de c1    	aesdec xmm8,xmm1
  24:	66 44 0f 38 de c9    	aesdec xmm9,xmm1
  2a:	66 44 0f 38 de d1    	aesdec xmm10,xmm1
  30:	66 44 0f 38 de d9    	aesdec xmm11,xmm1
  36:	0f 10 d1             	movups xmm2,xmm1
  39:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 11.17
- Reference cycles: 8.76
- UOPS_PORT_0: 11.0

⇨ One μop that can only use port '0'

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  12:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  18:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
  31:	00 00 
  33:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 9e e0 00 	lddqu  xmm11,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 a6 f0 00 	lddqu  xmm12,[r14+0xf0]
  5e:	00 00 
  60:	0f 10 d1             	movups xmm2,xmm1
  63:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 6.76
- Reference cycles: 5.28
- UOPS_PORT_3: 6.5
- UOPS_PORT_2: 6.5

⇨ One μop that can only use ports {'2', '3'}