CPUID - Port Usage (IACA 3.0)
With blocking instructions for port '0':
Throughput Analysis Report
--------------------------
Block Throughput: 33.90 Cycles Throughput Bottleneck: Backend
Loop Count: 24
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 34.0 0.0 | 2.7 | 0.0 0.0 | 0.0 0.0 | 0.0 | 2.7 | 2.7 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | movd r8d, mmx0
| 1 | 1.0 | | | | | | | | movd r9d, mmx0
| 1 | 1.0 | | | | | | | | movd r10d, mmx0
| 1 | 1.0 | | | | | | | | movd r11d, mmx0
| 1 | 1.0 | | | | | | | | movd r12d, mmx0
| 1 | 1.0 | | | | | | | | movd r8d, mmx0
| 1 | 1.0 | | | | | | | | movd r9d, mmx0
| 1 | 1.0 | | | | | | | | movd r10d, mmx0
| 1 | 1.0 | | | | | | | | movd r11d, mmx0
| 1 | 1.0 | | | | | | | | movd r12d, mmx0
| 1 | 1.0 | | | | | | | | movd r8d, mmx0
| 1 | 1.0 | | | | | | | | movd r9d, mmx0
| 1 | 1.0 | | | | | | | | movd r10d, mmx0
| 1 | 1.0 | | | | | | | | movd r11d, mmx0
| 1 | 1.0 | | | | | | | | movd r12d, mmx0
| 1 | 1.0 | | | | | | | | movd r8d, mmx0
| 1 | 1.0 | | | | | | | | movd r9d, mmx0
| 1 | 1.0 | | | | | | | | movd r10d, mmx0
| 1 | 1.0 | | | | | | | | movd r11d, mmx0
| 1 | 1.0 | | | | | | | | movd r12d, mmx0
| 1 | 1.0 | | | | | | | | movd r8d, mmx0
| 1 | 1.0 | | | | | | | | movd r9d, mmx0
| 1 | 1.0 | | | | | | | | movd r10d, mmx0
| 1 | 1.0 | | | | | | | | movd r11d, mmx0
| 1 | 1.0 | | | | | | | | movd r12d, mmx0
| 1 | 1.0 | | | | | | | | movd r8d, mmx0
| 1 | 1.0 | | | | | | | | movd r9d, mmx0
| 1 | 1.0 | | | | | | | | movd r10d, mmx0
| 1 | 1.0 | | | | | | | | movd r11d, mmx0
| 1 | 1.0 | | | | | | | | movd r12d, mmx0
| 1 | 1.0 | | | | | | | | movd r8d, mmx0
| 1 | 1.0 | | | | | | | | movd r9d, mmx0
| 1 | 1.0 | | | | | | | | movd r10d, mmx0
| 1 | 1.0 | | | | | | | | movd r11d, mmx0
| 8 | | 2.7 | | | | 2.7 | 2.7 | | cpuid
Total Num Of Uops: 42
With blocking instructions for port '1':
Throughput Analysis Report
--------------------------
Block Throughput: 33.89 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 2.7 0.0 | 34.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 2.6 | 2.7 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | | 1.0 | | | | | | | imul r8w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r10w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r11w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r12w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r8w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r10w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r11w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r12w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r8w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r10w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r11w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r12w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r8w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r10w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r11w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r12w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r8w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r10w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r11w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r12w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r8w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r10w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r11w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r12w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r8w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r10w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r11w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r12w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r8w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r10w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r11w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r12w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r8w, r9w, 0x0
| 1 | | 1.0 | | | | | | | imul r10w, r9w, 0x0
| 8 | 2.7 | | | | | 2.6 | 2.7 | | cpuid
Total Num Of Uops: 42
With blocking instructions for port '5':
Throughput Analysis Report
--------------------------
Block Throughput: 34.89 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 2.3 0.0 | 2.4 | 0.0 0.0 | 0.0 0.0 | 0.0 | 35.0 | 2.3 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | | | | | | 1.0 | | | insertps xmm0, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm2, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm3, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm4, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm5, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm6, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm7, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm8, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm9, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm10, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm11, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm12, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm0, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm2, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm3, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm4, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm5, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm6, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm7, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm8, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm9, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm10, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm11, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm12, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm0, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm2, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm3, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm4, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm5, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm6, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm7, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm8, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm9, xmm1, 0x2
| 1 | | | | | | 1.0 | | | insertps xmm10, xmm1, 0x2
| 8 | 2.3 | 2.4 | | | | 1.0 | 2.3 | | cpuid
Total Num Of Uops: 42
⇨ One μop that can only use port '5'
With blocking instructions for ports {'0', '1'}:
Throughput Analysis Report
--------------------------
Block Throughput: 33.89 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 34.0 0.0 | 34.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 4.0 | 4.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | pabsb xmm0, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm2, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm3, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm4, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm5, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm6, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm7, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm8, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm9, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm10, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm11, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm12, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm0, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm2, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm3, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm4, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm5, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm6, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm7, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm8, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm9, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm10, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm11, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm12, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm0, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm2, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm3, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm4, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm5, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm6, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm7, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm8, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm9, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm10, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm11, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm12, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm0, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm2, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm3, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm4, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm5, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm6, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm7, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm8, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm9, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm10, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm11, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm12, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm0, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm2, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm3, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm4, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm5, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm6, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm7, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm8, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm9, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm10, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm11, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm12, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm0, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm2, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm3, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm4, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm5, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm6, xmm1
| 1 | 1.0 | | | | | | | | pabsb xmm7, xmm1
| 1 | | 1.0 | | | | | | | pabsb xmm8, xmm1
| 8 | | | | | | 4.0 | 4.0 | | cpuid
Total Num Of Uops: 76
With blocking instructions for ports {'0', '5'}:
Throughput Analysis Report
--------------------------
Block Throughput: 34.42 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 34.5 0.0 | 3.5 | 0.0 0.0 | 0.0 0.0 | 0.0 | 34.5 | 3.5 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | movq mmx5, mmx1
| 8 | | 3.5 | | | | 1.0 | 3.5 | | cpuid
Total Num Of Uops: 76
With blocking instructions for ports {'0', '6'}:
Throughput Analysis Report
--------------------------
Block Throughput: 67.89 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 35.0 0.0 | 3.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 3.0 | 35.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 1 | 1.0 | | | | | | | | sar r12b, 0x0
| 1 | | | | | | | 1.0 | | sar r12b, 0x0
| 8 | 1.0 | 3.0 | | | | 3.0 | 1.0 | | cpuid
Total Num Of Uops: 76
⇨ 2 μops that can only use ports {'0', '6'}
With blocking instructions for ports {'1', '5'}:
Throughput Analysis Report
--------------------------
Block Throughput: 34.47 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 3.5 0.0 | 34.5 | 0.0 0.0 | 0.0 0.0 | 0.0 | 34.5 | 3.5 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | | 1.0 | | | | | | | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | lea r10w, ptr [r14]
| 8 | 3.5 | | | | | 1.0 | 3.5 | | cpuid
Total Num Of Uops: 76
With blocking instructions for ports {'0', '1', '5'}:
Throughput Analysis Report
--------------------------
Block Throughput: 33.79 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 33.6 0.0 | 33.7 | 0.0 0.0 | 0.0 0.0 | 0.0 | 33.7 | 7.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | 0.6 | 0.4 | | | | | | | addpd xmm0, xmm1
| 1 | 0.4 | 0.6 | | | | | | | addpd xmm2, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm4, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm5, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm7, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm8, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm10, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm11, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm0, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm2, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm4, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm5, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm7, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm8, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm10, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm11, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm0, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm2, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm4, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm5, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm7, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm8, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm10, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm11, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm0, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm2, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm4, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm5, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm7, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm8, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm10, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm11, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm0, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm2, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm4, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm5, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm7, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm8, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm10, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm11, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm0, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm2, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm4, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm5, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm7, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm8, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm10, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm11, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm0, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm2, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm4, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm5, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm7, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm8, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm10, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm11, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm0, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm2, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm4, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm5, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm7, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm8, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm10, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm11, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm0, xmm1
| 1 | 0.4 | 0.3 | | | | 0.3 | | | addpd xmm2, xmm1
| 1 | 0.3 | 0.4 | | | | 0.3 | | | addpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.4 | | | addpd xmm4, xmm1
| 8 | | | | | | 1.0 | 7.0 | | cpuid
Total Num Of Uops: 108
With blocking instructions for ports {'0', '1', '5', '6'}:
Throughput Analysis Report
--------------------------
Block Throughput: 26.89 Cycles Throughput Bottleneck: Dependency chains
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 27.0 0.0 | 27.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 27.0 | 27.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 1 | 1.0 | | | | | | | | mov bh, 0x0
| 1 | | 1.0 | | | | | | | mov bh, 0x0
| 1 | | | | | | 1.0 | | | mov bh, 0x0
| 1 | | | | | | | 1.0 | | mov bh, 0x0
| 8 | 2.0 | 2.0 | | | | 2.0 | 2.0 | | cpuid
Total Num Of Uops: 108
⇨ 5 μops that can only use ports {'0', '1', '5', '6'}