MOVSQ - Port Usage

With blocking instructions for port '4':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	48 a5                	movs   QWORD PTR es:[rdi],QWORD PTR ds:[rsi]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.18
- Reference cycles: 10.2
- UOPS_PORT_4: 11.09

⇨ One μop that can only use port '4'

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 c1 c2 00          	rol    dx,0x0
  25:	66 41 c1 c0 00       	rol    r8w,0x0
  2a:	66 41 c1 c1 00       	rol    r9w,0x0
  2f:	66 41 c1 c2 00       	rol    r10w,0x0
  34:	66 41 c1 c3 00       	rol    r11w,0x0
  39:	66 41 c1 c4 00       	rol    r12w,0x0
  3e:	66 c1 c3 00          	rol    bx,0x0
  42:	66 c1 c1 00          	rol    cx,0x0
  46:	66 c1 c2 00          	rol    dx,0x0
  4a:	48 a5                	movs   QWORD PTR es:[rdi],QWORD PTR ds:[rsi]

Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.11
- Reference cycles: 6.79
- UOPS_PORT_6: 7.98
- UOPS_PORT_0: 8.02

With blocking instructions for ports {'1', '5'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	41 8d 16             	lea    edx,[r14]
  18:	45 8d 06             	lea    r8d,[r14]
  1b:	45 8d 0e             	lea    r9d,[r14]
  1e:	45 8d 16             	lea    r10d,[r14]
  21:	45 8d 1e             	lea    r11d,[r14]
  24:	45 8d 26             	lea    r12d,[r14]
  27:	41 8d 1e             	lea    ebx,[r14]
  2a:	41 8d 0e             	lea    ecx,[r14]
  2d:	41 8d 16             	lea    edx,[r14]
  30:	48 a5                	movs   QWORD PTR es:[rdi],QWORD PTR ds:[rsi]

Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.11
- Reference cycles: 6.79
- UOPS_PORT_5: 8.0
- UOPS_PORT_1: 8.0

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	48 a5                	movs   QWORD PTR es:[rdi],QWORD PTR ds:[rsi]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 9.33
- Reference cycles: 8.58
- UOPS_PORT_2: 8.99
- UOPS_PORT_3: 9.01

⇨ 2 μops that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	66 0f 55 c1          	andnpd xmm0,xmm1
  39:	66 0f 55 d1          	andnpd xmm2,xmm1
  3d:	66 0f 55 d9          	andnpd xmm3,xmm1
  41:	66 0f 55 e1          	andnpd xmm4,xmm1
  45:	66 0f 55 e9          	andnpd xmm5,xmm1
  49:	66 0f 55 f1          	andnpd xmm6,xmm1
  4d:	66 0f 55 f9          	andnpd xmm7,xmm1
  51:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  56:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  5b:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  60:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  65:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  6a:	48 a5                	movs   QWORD PTR es:[rdi],QWORD PTR ds:[rsi]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 10.17
- Reference cycles: 9.73
- UOPS_PORT_5: 8.02
- UOPS_PORT_1: 8.0
- UOPS_PORT_0: 8.0

With blocking instructions for ports {'0', '1', '5', '6'}:

Code:

   0:	45 0f bf c1          	movsx  r8d,r9w
   4:	45 0f bf d1          	movsx  r10d,r9w
   8:	45 0f bf d9          	movsx  r11d,r9w
   c:	45 0f bf e1          	movsx  r12d,r9w
  10:	41 0f bf d9          	movsx  ebx,r9w
  14:	41 0f bf c9          	movsx  ecx,r9w
  18:	41 0f bf d1          	movsx  edx,r9w
  1c:	45 0f bf c1          	movsx  r8d,r9w
  20:	45 0f bf d1          	movsx  r10d,r9w
  24:	45 0f bf d9          	movsx  r11d,r9w
  28:	45 0f bf e1          	movsx  r12d,r9w
  2c:	41 0f bf d9          	movsx  ebx,r9w
  30:	41 0f bf c9          	movsx  ecx,r9w
  34:	41 0f bf d1          	movsx  edx,r9w
  38:	45 0f bf c1          	movsx  r8d,r9w
  3c:	45 0f bf d1          	movsx  r10d,r9w
  40:	45 0f bf d9          	movsx  r11d,r9w
  44:	45 0f bf e1          	movsx  r12d,r9w
  48:	41 0f bf d9          	movsx  ebx,r9w
  4c:	41 0f bf c9          	movsx  ecx,r9w
  50:	41 0f bf d1          	movsx  edx,r9w
  54:	45 0f bf c1          	movsx  r8d,r9w
  58:	45 0f bf d1          	movsx  r10d,r9w
  5c:	45 0f bf d9          	movsx  r11d,r9w
  60:	45 0f bf e1          	movsx  r12d,r9w
  64:	41 0f bf d9          	movsx  ebx,r9w
  68:	41 0f bf c9          	movsx  ecx,r9w
  6c:	41 0f bf d1          	movsx  edx,r9w
  70:	45 0f bf c1          	movsx  r8d,r9w
  74:	45 0f bf d1          	movsx  r10d,r9w
  78:	45 0f bf d9          	movsx  r11d,r9w
  7c:	45 0f bf e1          	movsx  r12d,r9w
  80:	48 a5                	movs   QWORD PTR es:[rdi],QWORD PTR ds:[rsi]

Show nanoBench command
Results:
- Instructions retired: 33.0
- Core cycles: 12.19
- Reference cycles: 10.73
- UOPS_PORT_5: 8.71
- UOPS_PORT_6: 8.65
- UOPS_PORT_1: 8.58
- UOPS_PORT_0: 8.06

⇨ 2 μops that can only use ports {'0', '1', '5', '6'}