CPUID - Port Usage (IACA 2.3)
With blocking instructions for port '0':
Throughput Analysis Report
--------------------------
Block Throughput: 34.00 Cycles Throughput Bottleneck: Backend. Port0
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 34.0 0.0 | 2.7 | 0.0 0.0 | 0.0 0.0 | 0.0 | 2.7 | 2.7 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | CP | aesdec xmm0, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm2, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm3, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm4, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm5, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm6, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm7, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm8, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm9, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm10, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm11, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm12, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm0, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm2, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm3, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm4, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm5, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm6, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm7, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm8, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm9, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm10, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm11, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm12, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm0, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm2, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm3, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm4, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm5, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm6, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm7, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm8, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm9, xmm1
| 1 | 1.0 | | | | | | | | CP | aesdec xmm10, xmm1
| 8 | | 2.7 | | | | 2.7 | 2.7 | | | cpuid
Total Num Of Uops: 42
With blocking instructions for port '1':
Throughput Analysis Report
--------------------------
Block Throughput: 34.00 Cycles Throughput Bottleneck: Backend. Port1
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 2.7 0.0 | 34.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 2.7 | 2.7 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | | 1.0 | | | | | | | CP | imul r8w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r10w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r11w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r12w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r8w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r10w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r11w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r12w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r8w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r10w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r11w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r12w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r8w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r10w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r11w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r12w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r8w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r10w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r11w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r12w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r8w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r10w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r11w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r12w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r8w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r10w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r11w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r12w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r8w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r10w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r11w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r12w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r8w, r9w
| 1 | | 1.0 | | | | | | | CP | imul r10w, r9w
| 8 | 2.7 | | | | | 2.7 | 2.7 | | | cpuid
Total Num Of Uops: 42
With blocking instructions for port '5':
Throughput Analysis Report
--------------------------
Block Throughput: 35.00 Cycles Throughput Bottleneck: Backend. Port5
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 2.0 0.0 | 2.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 35.0 | 3.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | | | | | | 1.0 | | | CP | insertps xmm0, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm2, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm3, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm4, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm5, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm6, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm7, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm8, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm9, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm10, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm11, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm12, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm0, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm2, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm3, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm4, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm5, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm6, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm7, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm8, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm9, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm10, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm11, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm12, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm0, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm2, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm3, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm4, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm5, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm6, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm7, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm8, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm9, xmm1, 0x2
| 1 | | | | | | 1.0 | | | CP | insertps xmm10, xmm1, 0x2
| 8 | 2.0 | 2.0 | | | | 1.0 | 3.0 | | CP | cpuid
Total Num Of Uops: 42
⇨ One μop that can only use port '5'
With blocking instructions for ports {'0', '1'}:
Throughput Analysis Report
--------------------------
Block Throughput: 34.00 Cycles Throughput Bottleneck: Backend. Port0, Port1
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 34.0 0.0 | 34.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 4.0 | 4.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | CP | addpd xmm0, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm2, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm3, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm4, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm5, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm6, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm7, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm8, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm9, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm10, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm11, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm12, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm0, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm2, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm3, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm4, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm5, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm6, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm7, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm8, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm9, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm10, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm11, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm12, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm0, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm2, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm3, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm4, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm5, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm6, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm7, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm8, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm9, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm10, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm11, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm12, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm0, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm2, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm3, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm4, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm5, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm6, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm7, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm8, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm9, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm10, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm11, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm12, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm0, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm2, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm3, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm4, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm5, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm6, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm7, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm8, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm9, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm10, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm11, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm12, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm0, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm2, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm3, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm4, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm5, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm6, xmm1
| 1 | 1.0 | | | | | | | | CP | addpd xmm7, xmm1
| 1 | | 1.0 | | | | | | | CP | addpd xmm8, xmm1
| 8 | | | | | | 4.0 | 4.0 | | | cpuid
Total Num Of Uops: 76
With blocking instructions for ports {'0', '5'}:
Throughput Analysis Report
--------------------------
Block Throughput: 34.50 Cycles Throughput Bottleneck: Backend. Port0, Port5
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 34.5 0.0 | 3.5 | 0.0 0.0 | 0.0 0.0 | 0.0 | 34.5 | 3.5 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | CP | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx5, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx6, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx7, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx0, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx2, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx3, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx4, mmx1
| 1 | 0.5 | | | | | 0.5 | | | CP | movq mmx5, mmx1
| 8 | | 3.5 | | | | 1.0 | 3.5 | | CP | cpuid
Total Num Of Uops: 76
With blocking instructions for ports {'0', '6'}:
Throughput Analysis Report
--------------------------
Block Throughput: 35.00 Cycles Throughput Bottleneck: Backend. Port0, Port6
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 35.0 0.0 | 3.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 3.0 | 35.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | CP | sar r8w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r9w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r10w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r11w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r12w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r8w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r9w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r10w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r11w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r12w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r8w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r9w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r10w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r11w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r12w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r8w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r9w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r10w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r11w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r12w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r8w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r9w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r10w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r11w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r12w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r8w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r9w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r10w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r11w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r12w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r8w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r9w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r10w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r11w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r12w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r8w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r9w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r10w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r11w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r12w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r8w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r9w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r10w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r11w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r12w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r8w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r9w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r10w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r11w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r12w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r8w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r9w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r10w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r11w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r12w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r8w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r9w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r10w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r11w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r12w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r8w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r9w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r10w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r11w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r12w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r8w, 0x0
| 1 | 1.0 | | | | | | | | CP | sar r9w, 0x0
| 1 | | | | | | | 1.0 | | CP | sar r10w, 0x0
| 8 | 1.0 | 3.0 | | | | 3.0 | 1.0 | | CP | cpuid
Total Num Of Uops: 76
⇨ 2 μops that can only use ports {'0', '6'}
With blocking instructions for ports {'1', '5'}:
Throughput Analysis Report
--------------------------
Block Throughput: 34.50 Cycles Throughput Bottleneck: Backend. Port1, Port5
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 3.5 0.0 | 34.5 | 0.0 0.0 | 0.0 0.0 | 0.0 | 34.5 | 3.5 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | | 1.0 | | | | | | | CP | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r10w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r11w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r12w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r8w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r9w, ptr [r14]
| 1 | | 0.5 | | | | 0.5 | | | CP | lea r10w, ptr [r14]
| 8 | 3.5 | | | | | 1.0 | 3.5 | | CP | cpuid
Total Num Of Uops: 76
With blocking instructions for ports {'0', '1', '5'}:
Throughput Analysis Report
--------------------------
Block Throughput: 33.70 Cycles Throughput Bottleneck: Backend. Port0, Port1, Port5
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 33.7 0.0 | 33.7 | 0.0 0.0 | 0.0 0.0 | 0.0 | 33.7 | 7.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 0.6 | 0.3 | | | | | | | CP | andnpd xmm0, xmm1
| 1 | 0.3 | 0.6 | | | | | | | CP | andnpd xmm2, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm4, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm5, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm7, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm8, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm10, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm11, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm0, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm2, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm4, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm5, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm7, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm8, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm10, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm11, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm0, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm2, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm4, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm5, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm7, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm8, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm10, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm11, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm0, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm2, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm4, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm5, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm7, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm8, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm10, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm11, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm0, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm2, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm4, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm5, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm7, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm8, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm10, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm11, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm0, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm2, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm4, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm5, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm7, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm8, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm10, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm11, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm0, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm2, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm4, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm5, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm7, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm8, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm10, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm11, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm0, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm2, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm4, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm5, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm6, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm7, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm8, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm9, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm10, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm11, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm12, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm0, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm2, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm3, xmm1
| 1 | 0.3 | 0.3 | | | | 0.3 | | | CP | andnpd xmm4, xmm1
| 8 | | | | | | 1.0 | 7.0 | | CP | cpuid
Total Num Of Uops: 108
With blocking instructions for ports {'0', '1', '5', '6'}:
Throughput Analysis Report
--------------------------
Block Throughput: 27.00 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 27.0 0.0 | 27.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 27.0 | 27.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 1 | 1.0 | | | | | | | | CP | mov r8w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r9w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r10w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r11w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r12w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r8w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r9w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r10w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r11w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r12w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r8w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r9w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r10w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r11w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r12w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r8w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r9w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r10w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r11w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r12w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r8w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r9w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r10w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r11w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r12w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r8w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r9w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r10w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r11w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r12w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r8w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r9w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r10w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r11w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r12w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r8w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r9w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r10w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r11w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r12w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r8w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r9w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r10w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r11w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r12w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r8w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r9w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r10w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r11w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r12w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r8w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r9w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r10w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r11w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r12w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r8w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r9w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r10w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r11w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r12w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r8w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r9w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r10w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r11w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r12w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r8w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r9w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r10w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r11w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r12w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r8w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r9w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r10w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r11w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r12w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r8w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r9w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r10w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r11w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r12w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r8w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r9w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r10w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r11w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r12w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r8w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r9w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r10w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r11w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r12w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r8w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r9w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r10w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r11w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r12w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r8w, 0x100
| 1 | 1.0 | | | | | | | | CP | mov r9w, 0x100
| 1 | | | | | | | 1.0 | | CP | mov r10w, 0x100
| 1 | | 1.0 | | | | | | | CP | mov r11w, 0x100
| 1 | | | | | | 1.0 | | | CP | mov r12w, 0x100
| 8 | 2.0 | 2.0 | | | | 2.0 | 2.0 | | CP | cpuid
Total Num Of Uops: 108
⇨ 5 μops that can only use ports {'0', '1', '5', '6'}