BSR (R64, M64) - Port Usage (IACA 3.0)
With blocking instructions for port '1':
Throughput Analysis Report
--------------------------
Block Throughput: 10.95 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 11.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | | 1.0 | | | | | | | imul r9w, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul r11w, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul r12w, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul bx, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul cx, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul dx, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul r9w, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul r11w, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul r12w, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul bx, r10w, 0x0
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | | | bsr r8, qword ptr [r14]
Total Num Of Uops: 12
⇨ One μop that can only use port '1'
With blocking instructions for ports {'2', '3'}:
Throughput Analysis Report
--------------------------
Block Throughput: 5.53 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 1.0 | 5.5 5.5 | 5.5 5.5 | 0.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov bh, byte ptr [rdi+0x40]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov ch, byte ptr [rdi+0x41]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov dh, byte ptr [rdi+0x42]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov ah, byte ptr [rdi+0x43]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov bh, byte ptr [rdi+0x40]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov ch, byte ptr [rdi+0x41]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov dh, byte ptr [rdi+0x42]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov ah, byte ptr [rdi+0x43]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov bh, byte ptr [rdi+0x40]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov ch, byte ptr [rdi+0x41]
| 2^ | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | | | bsr r8, qword ptr [r14]
Total Num Of Uops: 12
⇨ One μop that can only use ports {'2', '3'}
With an indexed addressing mode
With blocking instructions for port '1':
Throughput Analysis Report
--------------------------
Block Throughput: 10.95 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 11.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | | 1.0 | | | | | | | imul r9w, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul r11w, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul r12w, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul bx, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul cx, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul dx, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul r9w, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul r11w, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul r12w, r10w, 0x0
| 1 | | 1.0 | | | | | | | imul bx, r10w, 0x0
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | | | bsr r8, qword ptr [r14+r13*1]
Total Num Of Uops: 12
⇨ One μop that can only use port '1'
With blocking instructions for ports {'2', '3'}:
Throughput Analysis Report
--------------------------
Block Throughput: 5.53 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 0.0 0.0 | 1.0 | 5.5 5.5 | 5.5 5.5 | 0.0 | 0.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov bh, byte ptr [rdi+0x40]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov ch, byte ptr [rdi+0x41]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov dh, byte ptr [rdi+0x42]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov ah, byte ptr [rdi+0x43]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov bh, byte ptr [rdi+0x40]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov ch, byte ptr [rdi+0x41]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov dh, byte ptr [rdi+0x42]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov ah, byte ptr [rdi+0x43]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov bh, byte ptr [rdi+0x40]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | | | mov ch, byte ptr [rdi+0x41]
| 2 | | 1.0 | 0.5 0.5 | 0.5 0.5 | | | | | bsr r8, qword ptr [r14+r13*1]
Total Num Of Uops: 12
⇨ One μop that can only use ports {'2', '3'}