BSR (R64, M64) - Port Usage

With blocking instructions for port '1':

Code:

   0:	66 f2 45 0f 38 f1 ca 	crc32  r9d,r10w
   7:	66 f2 45 0f 38 f1 da 	crc32  r11d,r10w
   e:	66 f2 45 0f 38 f1 e2 	crc32  r12d,r10w
  15:	66 f2 41 0f 38 f1 da 	crc32  ebx,r10w
  1c:	66 f2 41 0f 38 f1 ca 	crc32  ecx,r10w
  23:	66 f2 41 0f 38 f1 d2 	crc32  edx,r10w
  2a:	66 f2 45 0f 38 f1 ca 	crc32  r9d,r10w
  31:	66 f2 45 0f 38 f1 da 	crc32  r11d,r10w
  38:	66 f2 45 0f 38 f1 e2 	crc32  r12d,r10w
  3f:	66 f2 41 0f 38 f1 da 	crc32  ebx,r10w
  46:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.06
- Reference cycles: 10.0
- UOPS_PORT_1: 11.0

⇨ One μop that can only use port '1'

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 6.63
- Reference cycles: 6.02
- UOPS_PORT_3: 6.5
- UOPS_PORT_2: 6.5

⇨ One μop that can only use ports {'2', '3'}

With an indexed addressing mode

With blocking instructions for port '1':

Code:

   0:	66 f2 45 0f 38 f1 ca 	crc32  r9d,r10w
   7:	66 f2 45 0f 38 f1 da 	crc32  r11d,r10w
   e:	66 f2 45 0f 38 f1 e2 	crc32  r12d,r10w
  15:	66 f2 41 0f 38 f1 da 	crc32  ebx,r10w
  1c:	66 f2 41 0f 38 f1 ca 	crc32  ecx,r10w
  23:	66 f2 41 0f 38 f1 d2 	crc32  edx,r10w
  2a:	66 f2 45 0f 38 f1 ca 	crc32  r9d,r10w
  31:	66 f2 45 0f 38 f1 da 	crc32  r11d,r10w
  38:	66 f2 45 0f 38 f1 e2 	crc32  r12d,r10w
  3f:	66 f2 41 0f 38 f1 da 	crc32  ebx,r10w
  46:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.07
- Reference cycles: 10.0
- UOPS_PORT_1: 11.0

⇨ One μop that can only use port '1'

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 6.62
- Reference cycles: 5.42
- UOPS_PORT_3: 6.5
- UOPS_PORT_2: 6.5

⇨ One μop that can only use ports {'2', '3'}