PCLMULQDQ (XMM, XMM, I8) - Port Usage

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	0f 7e c2             	movd   edx,mm0
  1d:	41 0f 7e c0          	movd   r8d,mm0
  21:	41 0f 7e c1          	movd   r9d,mm0
  25:	41 0f 7e c2          	movd   r10d,mm0
  29:	41 0f 7e c3          	movd   r11d,mm0
  2d:	41 0f 7e c4          	movd   r12d,mm0
  31:	0f 7e c3             	movd   ebx,mm0
  34:	0f 7e c1             	movd   ecx,mm0
  37:	0f 7e c2             	movd   edx,mm0
  3a:	41 0f 7e c0          	movd   r8d,mm0
  3e:	41 0f 7e c1          	movd   r9d,mm0
  42:	41 0f 7e c2          	movd   r10d,mm0
  46:	41 0f 7e c3          	movd   r11d,mm0
  4a:	41 0f 7e c4          	movd   r12d,mm0
  4e:	0f 7e c3             	movd   ebx,mm0
  51:	0f 7e c1             	movd   ecx,mm0
  54:	0f 7e c2             	movd   edx,mm0
  57:	41 0f 7e c0          	movd   r8d,mm0
  5b:	41 0f 7e c1          	movd   r9d,mm0
  5f:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1

Init:

PXOR MM0, MM0;
VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 27.0
- Core cycles: 28.39
- Reference cycles: 31.16
- UOPS_PORT_0: 28.0

⇨ 2 μops that can only use port '0'

With blocking instructions for port '1':

Code:

   0:	66 0f 58 d3          	addpd  xmm2,xmm3
   4:	66 0f 58 e3          	addpd  xmm4,xmm3
   8:	66 0f 58 eb          	addpd  xmm5,xmm3
   c:	66 0f 58 f3          	addpd  xmm6,xmm3
  10:	66 0f 58 fb          	addpd  xmm7,xmm3
  14:	66 44 0f 58 c3       	addpd  xmm8,xmm3
  19:	66 44 0f 58 cb       	addpd  xmm9,xmm3
  1e:	66 44 0f 58 d3       	addpd  xmm10,xmm3
  23:	66 44 0f 58 db       	addpd  xmm11,xmm3
  28:	66 44 0f 58 e3       	addpd  xmm12,xmm3
  2d:	66 0f 58 d3          	addpd  xmm2,xmm3
  31:	66 0f 58 e3          	addpd  xmm4,xmm3
  35:	66 0f 58 eb          	addpd  xmm5,xmm3
  39:	66 0f 58 f3          	addpd  xmm6,xmm3
  3d:	66 0f 58 fb          	addpd  xmm7,xmm3
  41:	66 44 0f 58 c3       	addpd  xmm8,xmm3
  46:	66 44 0f 58 cb       	addpd  xmm9,xmm3
  4b:	66 44 0f 58 d3       	addpd  xmm10,xmm3
  50:	66 44 0f 58 db       	addpd  xmm11,xmm3
  55:	66 44 0f 58 e3       	addpd  xmm12,xmm3
  5a:	66 0f 58 d3          	addpd  xmm2,xmm3
  5e:	66 0f 58 e3          	addpd  xmm4,xmm3
  62:	66 0f 58 eb          	addpd  xmm5,xmm3
  66:	66 0f 58 f3          	addpd  xmm6,xmm3
  6a:	66 0f 58 fb          	addpd  xmm7,xmm3
  6e:	66 44 0f 58 c3       	addpd  xmm8,xmm3
  73:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14];
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 27.0
- Core cycles: 30.28
- Reference cycles: 33.4
- UOPS_PORT_1: 30.0

⇨ 4 μops that can only use port '1'

With blocking instructions for port '5':

Code:

   0:	66 0f 55 d3          	andnpd xmm2,xmm3
   4:	66 0f 55 e3          	andnpd xmm4,xmm3
   8:	66 0f 55 eb          	andnpd xmm5,xmm3
   c:	66 0f 55 f3          	andnpd xmm6,xmm3
  10:	66 0f 55 fb          	andnpd xmm7,xmm3
  14:	66 44 0f 55 c3       	andnpd xmm8,xmm3
  19:	66 44 0f 55 cb       	andnpd xmm9,xmm3
  1e:	66 44 0f 55 d3       	andnpd xmm10,xmm3
  23:	66 44 0f 55 db       	andnpd xmm11,xmm3
  28:	66 44 0f 55 e3       	andnpd xmm12,xmm3
  2d:	66 0f 55 d3          	andnpd xmm2,xmm3
  31:	66 0f 55 e3          	andnpd xmm4,xmm3
  35:	66 0f 55 eb          	andnpd xmm5,xmm3
  39:	66 0f 55 f3          	andnpd xmm6,xmm3
  3d:	66 0f 55 fb          	andnpd xmm7,xmm3
  41:	66 44 0f 55 c3       	andnpd xmm8,xmm3
  46:	66 44 0f 55 cb       	andnpd xmm9,xmm3
  4b:	66 44 0f 55 d3       	andnpd xmm10,xmm3
  50:	66 44 0f 55 db       	andnpd xmm11,xmm3
  55:	66 44 0f 55 e3       	andnpd xmm12,xmm3
  5a:	66 0f 55 d3          	andnpd xmm2,xmm3
  5e:	66 0f 55 e3          	andnpd xmm4,xmm3
  62:	66 0f 55 eb          	andnpd xmm5,xmm3
  66:	66 0f 55 f3          	andnpd xmm6,xmm3
  6a:	66 0f 55 fb          	andnpd xmm7,xmm3
  6e:	66 44 0f 55 c3       	andnpd xmm8,xmm3
  73:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1

Init:

VZEROALL;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 27.0
- Core cycles: 29.15
- Reference cycles: 32.0
- UOPS_PORT_5: 29.0

⇨ 3 μops that can only use port '5'

With blocking instructions for ports {'0', '1'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	41 8d 16             	lea    edx,[r14]
  18:	45 8d 06             	lea    r8d,[r14]
  1b:	45 8d 0e             	lea    r9d,[r14]
  1e:	45 8d 16             	lea    r10d,[r14]
  21:	45 8d 1e             	lea    r11d,[r14]
  24:	45 8d 26             	lea    r12d,[r14]
  27:	41 8d 1e             	lea    ebx,[r14]
  2a:	41 8d 0e             	lea    ecx,[r14]
  2d:	41 8d 16             	lea    edx,[r14]
  30:	45 8d 06             	lea    r8d,[r14]
  33:	45 8d 0e             	lea    r9d,[r14]
  36:	45 8d 16             	lea    r10d,[r14]
  39:	45 8d 1e             	lea    r11d,[r14]
  3c:	45 8d 26             	lea    r12d,[r14]
  3f:	41 8d 1e             	lea    ebx,[r14]
  42:	41 8d 0e             	lea    ecx,[r14]
  45:	41 8d 16             	lea    edx,[r14]
  48:	45 8d 06             	lea    r8d,[r14]
  4b:	45 8d 0e             	lea    r9d,[r14]
  4e:	45 8d 16             	lea    r10d,[r14]
  51:	45 8d 1e             	lea    r11d,[r14]
  54:	45 8d 26             	lea    r12d,[r14]
  57:	41 8d 1e             	lea    ebx,[r14]
  5a:	41 8d 0e             	lea    ecx,[r14]
  5d:	41 8d 16             	lea    edx,[r14]
  60:	45 8d 06             	lea    r8d,[r14]
  63:	45 8d 0e             	lea    r9d,[r14]
  66:	45 8d 16             	lea    r10d,[r14]
  69:	45 8d 1e             	lea    r11d,[r14]
  6c:	45 8d 26             	lea    r12d,[r14]
  6f:	41 8d 1e             	lea    ebx,[r14]
  72:	41 8d 0e             	lea    ecx,[r14]
  75:	41 8d 16             	lea    edx,[r14]
  78:	45 8d 06             	lea    r8d,[r14]
  7b:	45 8d 0e             	lea    r9d,[r14]
  7e:	45 8d 16             	lea    r10d,[r14]
  81:	45 8d 1e             	lea    r11d,[r14]
  84:	45 8d 26             	lea    r12d,[r14]
  87:	41 8d 1e             	lea    ebx,[r14]
  8a:	41 8d 0e             	lea    ecx,[r14]
  8d:	41 8d 16             	lea    edx,[r14]
  90:	45 8d 06             	lea    r8d,[r14]
  93:	45 8d 0e             	lea    r9d,[r14]
  96:	45 8d 16             	lea    r10d,[r14]
  99:	45 8d 1e             	lea    r11d,[r14]
  9c:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 53.0
- Core cycles: 30.74
- Reference cycles: 33.68
- UOPS_PORT_0: 29.79
- UOPS_PORT_1: 28.11

With blocking instructions for ports {'0', '5'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 c1 c2 00          	rol    dx,0x0
  25:	66 41 c1 c0 00       	rol    r8w,0x0
  2a:	66 41 c1 c1 00       	rol    r9w,0x0
  2f:	66 41 c1 c2 00       	rol    r10w,0x0
  34:	66 41 c1 c3 00       	rol    r11w,0x0
  39:	66 41 c1 c4 00       	rol    r12w,0x0
  3e:	66 c1 c3 00          	rol    bx,0x0
  42:	66 c1 c1 00          	rol    cx,0x0
  46:	66 c1 c2 00          	rol    dx,0x0
  4a:	66 41 c1 c0 00       	rol    r8w,0x0
  4f:	66 41 c1 c1 00       	rol    r9w,0x0
  54:	66 41 c1 c2 00       	rol    r10w,0x0
  59:	66 41 c1 c3 00       	rol    r11w,0x0
  5e:	66 41 c1 c4 00       	rol    r12w,0x0
  63:	66 c1 c3 00          	rol    bx,0x0
  67:	66 c1 c1 00          	rol    cx,0x0
  6b:	66 c1 c2 00          	rol    dx,0x0
  6f:	66 41 c1 c0 00       	rol    r8w,0x0
  74:	66 41 c1 c1 00       	rol    r9w,0x0
  79:	66 41 c1 c2 00       	rol    r10w,0x0
  7e:	66 41 c1 c3 00       	rol    r11w,0x0
  83:	66 41 c1 c4 00       	rol    r12w,0x0
  88:	66 c1 c3 00          	rol    bx,0x0
  8c:	66 c1 c1 00          	rol    cx,0x0
  90:	66 c1 c2 00          	rol    dx,0x0
  94:	66 41 c1 c0 00       	rol    r8w,0x0
  99:	66 41 c1 c1 00       	rol    r9w,0x0
  9e:	66 41 c1 c2 00       	rol    r10w,0x0
  a3:	66 41 c1 c3 00       	rol    r11w,0x0
  a8:	66 41 c1 c4 00       	rol    r12w,0x0
  ad:	66 c1 c3 00          	rol    bx,0x0
  b1:	66 c1 c1 00          	rol    cx,0x0
  b5:	66 c1 c2 00          	rol    dx,0x0
  b9:	66 41 c1 c0 00       	rol    r8w,0x0
  be:	66 41 c1 c1 00       	rol    r9w,0x0
  c3:	66 41 c1 c2 00       	rol    r10w,0x0
  c8:	66 41 c1 c3 00       	rol    r11w,0x0
  cd:	66 41 c1 c4 00       	rol    r12w,0x0
  d2:	66 c1 c3 00          	rol    bx,0x0
  d6:	66 c1 c1 00          	rol    cx,0x0
  da:	66 c1 c2 00          	rol    dx,0x0
  de:	66 41 c1 c0 00       	rol    r8w,0x0
  e3:	66 41 c1 c1 00       	rol    r9w,0x0
  e8:	66 41 c1 c2 00       	rol    r10w,0x0
  ed:	66 41 c1 c3 00       	rol    r11w,0x0
  f2:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 53.0
- Core cycles: 30.79
- Reference cycles: 33.68
- UOPS_PORT_5: 30.05
- UOPS_PORT_0: 29.89

⇨ 3 μops that can only use ports {'0', '5'}

With blocking instructions for ports {'1', '5'}:

Code:

   0:	0f 38 1c c1          	pabsb  mm0,mm1
   4:	0f 38 1c d1          	pabsb  mm2,mm1
   8:	0f 38 1c d9          	pabsb  mm3,mm1
   c:	0f 38 1c e1          	pabsb  mm4,mm1
  10:	0f 38 1c e9          	pabsb  mm5,mm1
  14:	0f 38 1c f1          	pabsb  mm6,mm1
  18:	0f 38 1c f9          	pabsb  mm7,mm1
  1c:	0f 38 1c c1          	pabsb  mm0,mm1
  20:	0f 38 1c d1          	pabsb  mm2,mm1
  24:	0f 38 1c d9          	pabsb  mm3,mm1
  28:	0f 38 1c e1          	pabsb  mm4,mm1
  2c:	0f 38 1c e9          	pabsb  mm5,mm1
  30:	0f 38 1c f1          	pabsb  mm6,mm1
  34:	0f 38 1c f9          	pabsb  mm7,mm1
  38:	0f 38 1c c1          	pabsb  mm0,mm1
  3c:	0f 38 1c d1          	pabsb  mm2,mm1
  40:	0f 38 1c d9          	pabsb  mm3,mm1
  44:	0f 38 1c e1          	pabsb  mm4,mm1
  48:	0f 38 1c e9          	pabsb  mm5,mm1
  4c:	0f 38 1c f1          	pabsb  mm6,mm1
  50:	0f 38 1c f9          	pabsb  mm7,mm1
  54:	0f 38 1c c1          	pabsb  mm0,mm1
  58:	0f 38 1c d1          	pabsb  mm2,mm1
  5c:	0f 38 1c d9          	pabsb  mm3,mm1
  60:	0f 38 1c e1          	pabsb  mm4,mm1
  64:	0f 38 1c e9          	pabsb  mm5,mm1
  68:	0f 38 1c f1          	pabsb  mm6,mm1
  6c:	0f 38 1c f9          	pabsb  mm7,mm1
  70:	0f 38 1c c1          	pabsb  mm0,mm1
  74:	0f 38 1c d1          	pabsb  mm2,mm1
  78:	0f 38 1c d9          	pabsb  mm3,mm1
  7c:	0f 38 1c e1          	pabsb  mm4,mm1
  80:	0f 38 1c e9          	pabsb  mm5,mm1
  84:	0f 38 1c f1          	pabsb  mm6,mm1
  88:	0f 38 1c f9          	pabsb  mm7,mm1
  8c:	0f 38 1c c1          	pabsb  mm0,mm1
  90:	0f 38 1c d1          	pabsb  mm2,mm1
  94:	0f 38 1c d9          	pabsb  mm3,mm1
  98:	0f 38 1c e1          	pabsb  mm4,mm1
  9c:	0f 38 1c e9          	pabsb  mm5,mm1
  a0:	0f 38 1c f1          	pabsb  mm6,mm1
  a4:	0f 38 1c f9          	pabsb  mm7,mm1
  a8:	0f 38 1c c1          	pabsb  mm0,mm1
  ac:	0f 38 1c d1          	pabsb  mm2,mm1
  b0:	0f 38 1c d9          	pabsb  mm3,mm1
  b4:	0f 38 1c e1          	pabsb  mm4,mm1
  b8:	0f 38 1c e9          	pabsb  mm5,mm1
  bc:	0f 38 1c f1          	pabsb  mm6,mm1
  c0:	0f 38 1c f9          	pabsb  mm7,mm1
  c4:	0f 38 1c c1          	pabsb  mm0,mm1
  c8:	0f 38 1c d1          	pabsb  mm2,mm1
  cc:	0f 38 1c d9          	pabsb  mm3,mm1
  d0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1

Init:

VZEROALL;
PXOR MM1, MM1;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 53.0
- Core cycles: 31.26
- Reference cycles: 34.25
- UOPS_PORT_5: 30.47
- UOPS_PORT_1: 30.47

⇨ 2 μops that can only use ports {'1', '5'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	41 b0 00             	mov    r8b,0x0
   3:	41 b1 00             	mov    r9b,0x0
   6:	41 b2 00             	mov    r10b,0x0
   9:	41 b3 00             	mov    r11b,0x0
   c:	41 b4 00             	mov    r12b,0x0
   f:	b3 00                	mov    bl,0x0
  11:	b1 00                	mov    cl,0x0
  13:	b2 00                	mov    dl,0x0
  15:	41 b0 00             	mov    r8b,0x0
  18:	41 b1 00             	mov    r9b,0x0
  1b:	41 b2 00             	mov    r10b,0x0
  1e:	41 b3 00             	mov    r11b,0x0
  21:	41 b4 00             	mov    r12b,0x0
  24:	b3 00                	mov    bl,0x0
  26:	b1 00                	mov    cl,0x0
  28:	b2 00                	mov    dl,0x0
  2a:	41 b0 00             	mov    r8b,0x0
  2d:	41 b1 00             	mov    r9b,0x0
  30:	41 b2 00             	mov    r10b,0x0
  33:	41 b3 00             	mov    r11b,0x0
  36:	41 b4 00             	mov    r12b,0x0
  39:	b3 00                	mov    bl,0x0
  3b:	b1 00                	mov    cl,0x0
  3d:	b2 00                	mov    dl,0x0
  3f:	41 b0 00             	mov    r8b,0x0
  42:	41 b1 00             	mov    r9b,0x0
  45:	41 b2 00             	mov    r10b,0x0
  48:	41 b3 00             	mov    r11b,0x0
  4b:	41 b4 00             	mov    r12b,0x0
  4e:	b3 00                	mov    bl,0x0
  50:	b1 00                	mov    cl,0x0
  52:	b2 00                	mov    dl,0x0
  54:	41 b0 00             	mov    r8b,0x0
  57:	41 b1 00             	mov    r9b,0x0
  5a:	41 b2 00             	mov    r10b,0x0
  5d:	41 b3 00             	mov    r11b,0x0
  60:	41 b4 00             	mov    r12b,0x0
  63:	b3 00                	mov    bl,0x0
  65:	b1 00                	mov    cl,0x0
  67:	b2 00                	mov    dl,0x0
  69:	41 b0 00             	mov    r8b,0x0
  6c:	41 b1 00             	mov    r9b,0x0
  6f:	41 b2 00             	mov    r10b,0x0
  72:	41 b3 00             	mov    r11b,0x0
  75:	41 b4 00             	mov    r12b,0x0
  78:	b3 00                	mov    bl,0x0
  7a:	b1 00                	mov    cl,0x0
  7c:	b2 00                	mov    dl,0x0
  7e:	41 b0 00             	mov    r8b,0x0
  81:	41 b1 00             	mov    r9b,0x0
  84:	41 b2 00             	mov    r10b,0x0
  87:	41 b3 00             	mov    r11b,0x0
  8a:	41 b4 00             	mov    r12b,0x0
  8d:	b3 00                	mov    bl,0x0
  8f:	b1 00                	mov    cl,0x0
  91:	b2 00                	mov    dl,0x0
  93:	41 b0 00             	mov    r8b,0x0
  96:	41 b1 00             	mov    r9b,0x0
  99:	41 b2 00             	mov    r10b,0x0
  9c:	41 b3 00             	mov    r11b,0x0
  9f:	41 b4 00             	mov    r12b,0x0
  a2:	b3 00                	mov    bl,0x0
  a4:	b1 00                	mov    cl,0x0
  a6:	b2 00                	mov    dl,0x0
  a8:	41 b0 00             	mov    r8b,0x0
  ab:	41 b1 00             	mov    r9b,0x0
  ae:	41 b2 00             	mov    r10b,0x0
  b1:	41 b3 00             	mov    r11b,0x0
  b4:	41 b4 00             	mov    r12b,0x0
  b7:	b3 00                	mov    bl,0x0
  b9:	b1 00                	mov    cl,0x0
  bb:	b2 00                	mov    dl,0x0
  bd:	41 b0 00             	mov    r8b,0x0
  c0:	41 b1 00             	mov    r9b,0x0
  c3:	41 b2 00             	mov    r10b,0x0
  c6:	41 b3 00             	mov    r11b,0x0
  c9:	41 b4 00             	mov    r12b,0x0
  cc:	b3 00                	mov    bl,0x0
  ce:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 79.0
- Core cycles: 34.03
- Reference cycles: 37.33
- UOPS_PORT_5: 32.04
- UOPS_PORT_0: 32.9
- UOPS_PORT_1: 31.06

⇨ 4 μops that can only use ports {'0', '1', '5'}