MUL (R32) - Port Usage

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c1          	movd   r9d,mm0
   4:	41 0f 7e c2          	movd   r10d,mm0
   8:	41 0f 7e c3          	movd   r11d,mm0
   c:	41 0f 7e c4          	movd   r12d,mm0
  10:	0f 7e c3             	movd   ebx,mm0
  13:	0f 7e c1             	movd   ecx,mm0
  16:	41 0f 7e c1          	movd   r9d,mm0
  1a:	41 0f 7e c2          	movd   r10d,mm0
  1e:	41 0f 7e c3          	movd   r11d,mm0
  22:	41 0f 7e c4          	movd   r12d,mm0
  26:	41 f7 e0             	mul    r8d

Init:
```
PXOR MM0, MM0
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.05
- Reference cycles: 11.15
- UOPS_PORT_0: 10.0

With blocking instructions for port '1':

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	41 f7 e0             	mul    r8d

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.07
- Reference cycles: 12.32
- UOPS_PORT_1: 11.0

⇨ One μop that can only use port '1'

With blocking instructions for port '5':

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	41 f7 e0             	mul    r8d

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.05
- Reference cycles: 11.09
- UOPS_PORT_5: 10.0

With blocking instructions for ports {'0', '1'}:

Code:

   0:	45 8d 0e             	lea    r9d,[r14]
   3:	45 8d 16             	lea    r10d,[r14]
   6:	45 8d 1e             	lea    r11d,[r14]
   9:	45 8d 26             	lea    r12d,[r14]
   c:	41 8d 1e             	lea    ebx,[r14]
   f:	41 8d 0e             	lea    ecx,[r14]
  12:	45 8d 0e             	lea    r9d,[r14]
  15:	45 8d 16             	lea    r10d,[r14]
  18:	45 8d 1e             	lea    r11d,[r14]
  1b:	45 8d 26             	lea    r12d,[r14]
  1e:	41 8d 1e             	lea    ebx,[r14]
  21:	41 8d 0e             	lea    ecx,[r14]
  24:	45 8d 0e             	lea    r9d,[r14]
  27:	45 8d 16             	lea    r10d,[r14]
  2a:	45 8d 1e             	lea    r11d,[r14]
  2d:	45 8d 26             	lea    r12d,[r14]
  30:	41 f7 e0             	mul    r8d

Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 9.18
- Reference cycles: 10.06
- UOPS_PORT_0: 8.94
- UOPS_PORT_1: 8.03

With blocking instructions for ports {'0', '5'}:

Code:

   0:	66 41 c1 c1 00       	rol    r9w,0x0
   5:	66 41 c1 c2 00       	rol    r10w,0x0
   a:	66 41 c1 c3 00       	rol    r11w,0x0
   f:	66 41 c1 c4 00       	rol    r12w,0x0
  14:	66 c1 c3 00          	rol    bx,0x0
  18:	66 c1 c1 00          	rol    cx,0x0
  1c:	66 41 c1 c1 00       	rol    r9w,0x0
  21:	66 41 c1 c2 00       	rol    r10w,0x0
  26:	66 41 c1 c3 00       	rol    r11w,0x0
  2b:	66 41 c1 c4 00       	rol    r12w,0x0
  30:	66 c1 c3 00          	rol    bx,0x0
  34:	66 c1 c1 00          	rol    cx,0x0
  38:	66 41 c1 c1 00       	rol    r9w,0x0
  3d:	66 41 c1 c2 00       	rol    r10w,0x0
  42:	66 41 c1 c3 00       	rol    r11w,0x0
  47:	66 41 c1 c4 00       	rol    r12w,0x0
  4c:	41 f7 e0             	mul    r8d

Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.6
- Reference cycles: 9.29
- UOPS_PORT_5: 8.5
- UOPS_PORT_0: 8.48

⇨ One μop that can only use ports {'0', '5'}

With blocking instructions for ports {'1', '5'}:

Code:

   0:	0f 38 1c c1          	pabsb  mm0,mm1
   4:	0f 38 1c d1          	pabsb  mm2,mm1
   8:	0f 38 1c d9          	pabsb  mm3,mm1
   c:	0f 38 1c e1          	pabsb  mm4,mm1
  10:	0f 38 1c e9          	pabsb  mm5,mm1
  14:	0f 38 1c f1          	pabsb  mm6,mm1
  18:	0f 38 1c f9          	pabsb  mm7,mm1
  1c:	0f 38 1c c1          	pabsb  mm0,mm1
  20:	0f 38 1c d1          	pabsb  mm2,mm1
  24:	0f 38 1c d9          	pabsb  mm3,mm1
  28:	0f 38 1c e1          	pabsb  mm4,mm1
  2c:	0f 38 1c e9          	pabsb  mm5,mm1
  30:	0f 38 1c f1          	pabsb  mm6,mm1
  34:	0f 38 1c f9          	pabsb  mm7,mm1
  38:	0f 38 1c c1          	pabsb  mm0,mm1
  3c:	0f 38 1c d1          	pabsb  mm2,mm1
  40:	41 f7 e0             	mul    r8d

Init:
```
VZEROALL;
PXOR MM1, MM1
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.66
- Reference cycles: 9.55
- UOPS_PORT_5: 8.48
- UOPS_PORT_1: 8.5

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	41 b1 00             	mov    r9b,0x0
   3:	41 b2 00             	mov    r10b,0x0
   6:	41 b3 00             	mov    r11b,0x0
   9:	41 b4 00             	mov    r12b,0x0
   c:	b3 00                	mov    bl,0x0
   e:	b1 00                	mov    cl,0x0
  10:	41 b1 00             	mov    r9b,0x0
  13:	41 b2 00             	mov    r10b,0x0
  16:	41 b3 00             	mov    r11b,0x0
  19:	41 b4 00             	mov    r12b,0x0
  1c:	b3 00                	mov    bl,0x0
  1e:	b1 00                	mov    cl,0x0
  20:	41 b1 00             	mov    r9b,0x0
  23:	41 b2 00             	mov    r10b,0x0
  26:	41 b3 00             	mov    r11b,0x0
  29:	41 b4 00             	mov    r12b,0x0
  2c:	b3 00                	mov    bl,0x0
  2e:	b1 00                	mov    cl,0x0
  30:	41 b1 00             	mov    r9b,0x0
  33:	41 b2 00             	mov    r10b,0x0
  36:	41 b3 00             	mov    r11b,0x0
  39:	41 b4 00             	mov    r12b,0x0
  3c:	b3 00                	mov    bl,0x0
  3e:	b1 00                	mov    cl,0x0
  40:	41 f7 e0             	mul    r8d

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 9.93
- Reference cycles: 10.93
- UOPS_PORT_5: 9.05
- UOPS_PORT_0: 9.2
- UOPS_PORT_1: 8.76

⇨ One μop that can only use ports {'0', '1', '5'}