INC_LOCK (M32) - Port Usage

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	0f 7e c2             	movd   edx,mm0
  1d:	41 0f 7e c0          	movd   r8d,mm0
  21:	41 0f 7e c1          	movd   r9d,mm0
  25:	41 0f 7e c2          	movd   r10d,mm0
  29:	41 0f 7e c3          	movd   r11d,mm0
  2d:	41 0f 7e c4          	movd   r12d,mm0
  31:	0f 7e c3             	movd   ebx,mm0
  34:	0f 7e c1             	movd   ecx,mm0
  37:	0f 7e c2             	movd   edx,mm0
  3a:	41 0f 7e c0          	movd   r8d,mm0
  3e:	41 0f 7e c1          	movd   r9d,mm0
  42:	41 0f 7e c2          	movd   r10d,mm0
  46:	41 0f 7e c3          	movd   r11d,mm0
  4a:	41 0f 7e c4          	movd   r12d,mm0
  4e:	0f 7e c3             	movd   ebx,mm0
  51:	0f 7e c1             	movd   ecx,mm0
  54:	0f 7e c2             	movd   edx,mm0
  57:	41 0f 7e c0          	movd   r8d,mm0
  5b:	41 0f 7e c1          	movd   r9d,mm0
  5f:	41 0f 7e c2          	movd   r10d,mm0
  63:	41 0f 7e c3          	movd   r11d,mm0
  67:	41 0f 7e c4          	movd   r12d,mm0
  6b:	0f 7e c3             	movd   ebx,mm0
  6e:	0f 7e c1             	movd   ecx,mm0
  71:	0f 7e c2             	movd   edx,mm0
  74:	41 0f 7e c0          	movd   r8d,mm0
  78:	41 0f 7e c1          	movd   r9d,mm0
  7c:	41 0f 7e c2          	movd   r10d,mm0
  80:	41 0f 7e c3          	movd   r11d,mm0
  84:	41 0f 7e c4          	movd   r12d,mm0
  88:	0f 7e c3             	movd   ebx,mm0
  8b:	0f 7e c1             	movd   ecx,mm0
  8e:	0f 7e c2             	movd   edx,mm0
  91:	41 0f 7e c0          	movd   r8d,mm0
  95:	41 0f 7e c1          	movd   r9d,mm0
  99:	41 0f 7e c2          	movd   r10d,mm0
  9d:	41 0f 7e c3          	movd   r11d,mm0
  a1:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Init:
```
PXOR MM0, MM0
```
Show nanoBench command
Results:
- Instructions retired: 45.0
- Core cycles: 45.05
- Reference cycles: 49.45
- UOPS_PORT_0: 43.95

With blocking instructions for port '1':

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  30:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  35:	66 0f 58 c1          	addpd  xmm0,xmm1
  39:	66 0f 58 d1          	addpd  xmm2,xmm1
  3d:	66 0f 58 d9          	addpd  xmm3,xmm1
  41:	66 0f 58 e1          	addpd  xmm4,xmm1
  45:	66 0f 58 e9          	addpd  xmm5,xmm1
  49:	66 0f 58 f1          	addpd  xmm6,xmm1
  4d:	66 0f 58 f9          	addpd  xmm7,xmm1
  51:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  56:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  5b:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  60:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  65:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  6a:	66 0f 58 c1          	addpd  xmm0,xmm1
  6e:	66 0f 58 d1          	addpd  xmm2,xmm1
  72:	66 0f 58 d9          	addpd  xmm3,xmm1
  76:	66 0f 58 e1          	addpd  xmm4,xmm1
  7a:	66 0f 58 e9          	addpd  xmm5,xmm1
  7e:	66 0f 58 f1          	addpd  xmm6,xmm1
  82:	66 0f 58 f9          	addpd  xmm7,xmm1
  86:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  8b:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  90:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  95:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  9a:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  9f:	66 0f 58 c1          	addpd  xmm0,xmm1
  a3:	66 0f 58 d1          	addpd  xmm2,xmm1
  a7:	66 0f 58 d9          	addpd  xmm3,xmm1
  ab:	66 0f 58 e1          	addpd  xmm4,xmm1
  af:	66 0f 58 e9          	addpd  xmm5,xmm1
  b3:	66 0f 58 f1          	addpd  xmm6,xmm1
  b7:	66 0f 58 f9          	addpd  xmm7,xmm1
  bb:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  c0:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 45.0
- Core cycles: 45.66
- Reference cycles: 50.67
- UOPS_PORT_1: 43.95

With blocking instructions for port '4':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  35:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  3c:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  43:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  4a:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  51:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  58:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  5c:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  60:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  64:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  68:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  6c:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  70:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  74:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  78:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  7f:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  86:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  8d:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  94:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  9b:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  a2:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  a9:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  b0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  b4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  b8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  bc:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  c0:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  c4:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  c8:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  cc:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  d0:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  d7:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  de:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  e5:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  ec:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 45.0
- Core cycles: 66.67
- Reference cycles: 73.21
- UOPS_PORT_4: 46.95

⇨ One μop that can only use port '4'

With blocking instructions for port '5':

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	66 0f 55 c1          	andnpd xmm0,xmm1
  39:	66 0f 55 d1          	andnpd xmm2,xmm1
  3d:	66 0f 55 d9          	andnpd xmm3,xmm1
  41:	66 0f 55 e1          	andnpd xmm4,xmm1
  45:	66 0f 55 e9          	andnpd xmm5,xmm1
  49:	66 0f 55 f1          	andnpd xmm6,xmm1
  4d:	66 0f 55 f9          	andnpd xmm7,xmm1
  51:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  56:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  5b:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  60:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  65:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  6a:	66 0f 55 c1          	andnpd xmm0,xmm1
  6e:	66 0f 55 d1          	andnpd xmm2,xmm1
  72:	66 0f 55 d9          	andnpd xmm3,xmm1
  76:	66 0f 55 e1          	andnpd xmm4,xmm1
  7a:	66 0f 55 e9          	andnpd xmm5,xmm1
  7e:	66 0f 55 f1          	andnpd xmm6,xmm1
  82:	66 0f 55 f9          	andnpd xmm7,xmm1
  86:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  8b:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  90:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  95:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  9a:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  9f:	66 0f 55 c1          	andnpd xmm0,xmm1
  a3:	66 0f 55 d1          	andnpd xmm2,xmm1
  a7:	66 0f 55 d9          	andnpd xmm3,xmm1
  ab:	66 0f 55 e1          	andnpd xmm4,xmm1
  af:	66 0f 55 e9          	andnpd xmm5,xmm1
  b3:	66 0f 55 f1          	andnpd xmm6,xmm1
  b7:	66 0f 55 f9          	andnpd xmm7,xmm1
  bb:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  c0:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 45.0
- Core cycles: 47.0
- Reference cycles: 51.88
- UOPS_PORT_5: 46.0

⇨ 2 μops that can only use port '5'

With blocking instructions for ports {'0', '1'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	41 8d 16             	lea    edx,[r14]
  18:	45 8d 06             	lea    r8d,[r14]
  1b:	45 8d 0e             	lea    r9d,[r14]
  1e:	45 8d 16             	lea    r10d,[r14]
  21:	45 8d 1e             	lea    r11d,[r14]
  24:	45 8d 26             	lea    r12d,[r14]
  27:	41 8d 1e             	lea    ebx,[r14]
  2a:	41 8d 0e             	lea    ecx,[r14]
  2d:	41 8d 16             	lea    edx,[r14]
  30:	45 8d 06             	lea    r8d,[r14]
  33:	45 8d 0e             	lea    r9d,[r14]
  36:	45 8d 16             	lea    r10d,[r14]
  39:	45 8d 1e             	lea    r11d,[r14]
  3c:	45 8d 26             	lea    r12d,[r14]
  3f:	41 8d 1e             	lea    ebx,[r14]
  42:	41 8d 0e             	lea    ecx,[r14]
  45:	41 8d 16             	lea    edx,[r14]
  48:	45 8d 06             	lea    r8d,[r14]
  4b:	45 8d 0e             	lea    r9d,[r14]
  4e:	45 8d 16             	lea    r10d,[r14]
  51:	45 8d 1e             	lea    r11d,[r14]
  54:	45 8d 26             	lea    r12d,[r14]
  57:	41 8d 1e             	lea    ebx,[r14]
  5a:	41 8d 0e             	lea    ecx,[r14]
  5d:	41 8d 16             	lea    edx,[r14]
  60:	45 8d 06             	lea    r8d,[r14]
  63:	45 8d 0e             	lea    r9d,[r14]
  66:	45 8d 16             	lea    r10d,[r14]
  69:	45 8d 1e             	lea    r11d,[r14]
  6c:	45 8d 26             	lea    r12d,[r14]
  6f:	41 8d 1e             	lea    ebx,[r14]
  72:	41 8d 0e             	lea    ecx,[r14]
  75:	41 8d 16             	lea    edx,[r14]
  78:	45 8d 06             	lea    r8d,[r14]
  7b:	45 8d 0e             	lea    r9d,[r14]
  7e:	45 8d 16             	lea    r10d,[r14]
  81:	45 8d 1e             	lea    r11d,[r14]
  84:	45 8d 26             	lea    r12d,[r14]
  87:	41 8d 1e             	lea    ebx,[r14]
  8a:	41 8d 0e             	lea    ecx,[r14]
  8d:	41 8d 16             	lea    edx,[r14]
  90:	45 8d 06             	lea    r8d,[r14]
  93:	45 8d 0e             	lea    r9d,[r14]
  96:	45 8d 16             	lea    r10d,[r14]
  99:	45 8d 1e             	lea    r11d,[r14]
  9c:	45 8d 26             	lea    r12d,[r14]
  9f:	41 8d 1e             	lea    ebx,[r14]
  a2:	41 8d 0e             	lea    ecx,[r14]
  a5:	41 8d 16             	lea    edx,[r14]
  a8:	45 8d 06             	lea    r8d,[r14]
  ab:	45 8d 0e             	lea    r9d,[r14]
  ae:	45 8d 16             	lea    r10d,[r14]
  b1:	45 8d 1e             	lea    r11d,[r14]
  b4:	45 8d 26             	lea    r12d,[r14]
  b7:	41 8d 1e             	lea    ebx,[r14]
  ba:	41 8d 0e             	lea    ecx,[r14]
  bd:	41 8d 16             	lea    edx,[r14]
  c0:	45 8d 06             	lea    r8d,[r14]
  c3:	45 8d 0e             	lea    r9d,[r14]
  c6:	45 8d 16             	lea    r10d,[r14]
  c9:	45 8d 1e             	lea    r11d,[r14]
  cc:	45 8d 26             	lea    r12d,[r14]
  cf:	41 8d 1e             	lea    ebx,[r14]
  d2:	41 8d 0e             	lea    ecx,[r14]
  d5:	41 8d 16             	lea    edx,[r14]
  d8:	45 8d 06             	lea    r8d,[r14]
  db:	45 8d 0e             	lea    r9d,[r14]
  de:	45 8d 16             	lea    r10d,[r14]
  e1:	45 8d 1e             	lea    r11d,[r14]
  e4:	45 8d 26             	lea    r12d,[r14]
  e7:	41 8d 1e             	lea    ebx,[r14]
  ea:	41 8d 0e             	lea    ecx,[r14]
  ed:	41 8d 16             	lea    edx,[r14]
  f0:	45 8d 06             	lea    r8d,[r14]
  f3:	45 8d 0e             	lea    r9d,[r14]
  f6:	45 8d 16             	lea    r10d,[r14]
  f9:	45 8d 1e             	lea    r11d,[r14]
  fc:	45 8d 26             	lea    r12d,[r14]
  ff:	41 8d 1e             	lea    ebx,[r14]
 102:	41 8d 0e             	lea    ecx,[r14]
 105:	41 8d 16             	lea    edx,[r14]
 108:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 89.0
- Core cycles: 46.09
- Reference cycles: 50.91
- UOPS_PORT_0: 44.0
- UOPS_PORT_1: 43.91

With blocking instructions for ports {'0', '5'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 c1 c2 00          	rol    dx,0x0
  25:	66 41 c1 c0 00       	rol    r8w,0x0
  2a:	66 41 c1 c1 00       	rol    r9w,0x0
  2f:	66 41 c1 c2 00       	rol    r10w,0x0
  34:	66 41 c1 c3 00       	rol    r11w,0x0
  39:	66 41 c1 c4 00       	rol    r12w,0x0
  3e:	66 c1 c3 00          	rol    bx,0x0
  42:	66 c1 c1 00          	rol    cx,0x0
  46:	66 c1 c2 00          	rol    dx,0x0
  4a:	66 41 c1 c0 00       	rol    r8w,0x0
  4f:	66 41 c1 c1 00       	rol    r9w,0x0
  54:	66 41 c1 c2 00       	rol    r10w,0x0
  59:	66 41 c1 c3 00       	rol    r11w,0x0
  5e:	66 41 c1 c4 00       	rol    r12w,0x0
  63:	66 c1 c3 00          	rol    bx,0x0
  67:	66 c1 c1 00          	rol    cx,0x0
  6b:	66 c1 c2 00          	rol    dx,0x0
  6f:	66 41 c1 c0 00       	rol    r8w,0x0
  74:	66 41 c1 c1 00       	rol    r9w,0x0
  79:	66 41 c1 c2 00       	rol    r10w,0x0
  7e:	66 41 c1 c3 00       	rol    r11w,0x0
  83:	66 41 c1 c4 00       	rol    r12w,0x0
  88:	66 c1 c3 00          	rol    bx,0x0
  8c:	66 c1 c1 00          	rol    cx,0x0
  90:	66 c1 c2 00          	rol    dx,0x0
  94:	66 41 c1 c0 00       	rol    r8w,0x0
  99:	66 41 c1 c1 00       	rol    r9w,0x0
  9e:	66 41 c1 c2 00       	rol    r10w,0x0
  a3:	66 41 c1 c3 00       	rol    r11w,0x0
  a8:	66 41 c1 c4 00       	rol    r12w,0x0
  ad:	66 c1 c3 00          	rol    bx,0x0
  b1:	66 c1 c1 00          	rol    cx,0x0
  b5:	66 c1 c2 00          	rol    dx,0x0
  b9:	66 41 c1 c0 00       	rol    r8w,0x0
  be:	66 41 c1 c1 00       	rol    r9w,0x0
  c3:	66 41 c1 c2 00       	rol    r10w,0x0
  c8:	66 41 c1 c3 00       	rol    r11w,0x0
  cd:	66 41 c1 c4 00       	rol    r12w,0x0
  d2:	66 c1 c3 00          	rol    bx,0x0
  d6:	66 c1 c1 00          	rol    cx,0x0
  da:	66 c1 c2 00          	rol    dx,0x0
  de:	66 41 c1 c0 00       	rol    r8w,0x0
  e3:	66 41 c1 c1 00       	rol    r9w,0x0
  e8:	66 41 c1 c2 00       	rol    r10w,0x0
  ed:	66 41 c1 c3 00       	rol    r11w,0x0
  f2:	66 41 c1 c4 00       	rol    r12w,0x0
  f7:	66 c1 c3 00          	rol    bx,0x0
  fb:	66 c1 c1 00          	rol    cx,0x0
  ff:	66 c1 c2 00          	rol    dx,0x0
 103:	66 41 c1 c0 00       	rol    r8w,0x0
 108:	66 41 c1 c1 00       	rol    r9w,0x0
 10d:	66 41 c1 c2 00       	rol    r10w,0x0
 112:	66 41 c1 c3 00       	rol    r11w,0x0
 117:	66 41 c1 c4 00       	rol    r12w,0x0
 11c:	66 c1 c3 00          	rol    bx,0x0
 120:	66 c1 c1 00          	rol    cx,0x0
 124:	66 c1 c2 00          	rol    dx,0x0
 128:	66 41 c1 c0 00       	rol    r8w,0x0
 12d:	66 41 c1 c1 00       	rol    r9w,0x0
 132:	66 41 c1 c2 00       	rol    r10w,0x0
 137:	66 41 c1 c3 00       	rol    r11w,0x0
 13c:	66 41 c1 c4 00       	rol    r12w,0x0
 141:	66 c1 c3 00          	rol    bx,0x0
 145:	66 c1 c1 00          	rol    cx,0x0
 149:	66 c1 c2 00          	rol    dx,0x0
 14d:	66 41 c1 c0 00       	rol    r8w,0x0
 152:	66 41 c1 c1 00       	rol    r9w,0x0
 157:	66 41 c1 c2 00       	rol    r10w,0x0
 15c:	66 41 c1 c3 00       	rol    r11w,0x0
 161:	66 41 c1 c4 00       	rol    r12w,0x0
 166:	66 c1 c3 00          	rol    bx,0x0
 16a:	66 c1 c1 00          	rol    cx,0x0
 16e:	66 c1 c2 00          	rol    dx,0x0
 172:	66 41 c1 c0 00       	rol    r8w,0x0
 177:	66 41 c1 c1 00       	rol    r9w,0x0
 17c:	66 41 c1 c2 00       	rol    r10w,0x0
 181:	66 41 c1 c3 00       	rol    r11w,0x0
 186:	66 41 c1 c4 00       	rol    r12w,0x0
 18b:	66 c1 c3 00          	rol    bx,0x0
 18f:	66 c1 c1 00          	rol    cx,0x0
 193:	66 c1 c2 00          	rol    dx,0x0
 197:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 89.0
- Core cycles: 47.09
- Reference cycles: 52.36
- UOPS_PORT_5: 45.18
- UOPS_PORT_0: 44.91

With blocking instructions for ports {'1', '5'}:

Code:

   0:	0f 38 1c c1          	pabsb  mm0,mm1
   4:	0f 38 1c d1          	pabsb  mm2,mm1
   8:	0f 38 1c d9          	pabsb  mm3,mm1
   c:	0f 38 1c e1          	pabsb  mm4,mm1
  10:	0f 38 1c e9          	pabsb  mm5,mm1
  14:	0f 38 1c f1          	pabsb  mm6,mm1
  18:	0f 38 1c f9          	pabsb  mm7,mm1
  1c:	0f 38 1c c1          	pabsb  mm0,mm1
  20:	0f 38 1c d1          	pabsb  mm2,mm1
  24:	0f 38 1c d9          	pabsb  mm3,mm1
  28:	0f 38 1c e1          	pabsb  mm4,mm1
  2c:	0f 38 1c e9          	pabsb  mm5,mm1
  30:	0f 38 1c f1          	pabsb  mm6,mm1
  34:	0f 38 1c f9          	pabsb  mm7,mm1
  38:	0f 38 1c c1          	pabsb  mm0,mm1
  3c:	0f 38 1c d1          	pabsb  mm2,mm1
  40:	0f 38 1c d9          	pabsb  mm3,mm1
  44:	0f 38 1c e1          	pabsb  mm4,mm1
  48:	0f 38 1c e9          	pabsb  mm5,mm1
  4c:	0f 38 1c f1          	pabsb  mm6,mm1
  50:	0f 38 1c f9          	pabsb  mm7,mm1
  54:	0f 38 1c c1          	pabsb  mm0,mm1
  58:	0f 38 1c d1          	pabsb  mm2,mm1
  5c:	0f 38 1c d9          	pabsb  mm3,mm1
  60:	0f 38 1c e1          	pabsb  mm4,mm1
  64:	0f 38 1c e9          	pabsb  mm5,mm1
  68:	0f 38 1c f1          	pabsb  mm6,mm1
  6c:	0f 38 1c f9          	pabsb  mm7,mm1
  70:	0f 38 1c c1          	pabsb  mm0,mm1
  74:	0f 38 1c d1          	pabsb  mm2,mm1
  78:	0f 38 1c d9          	pabsb  mm3,mm1
  7c:	0f 38 1c e1          	pabsb  mm4,mm1
  80:	0f 38 1c e9          	pabsb  mm5,mm1
  84:	0f 38 1c f1          	pabsb  mm6,mm1
  88:	0f 38 1c f9          	pabsb  mm7,mm1
  8c:	0f 38 1c c1          	pabsb  mm0,mm1
  90:	0f 38 1c d1          	pabsb  mm2,mm1
  94:	0f 38 1c d9          	pabsb  mm3,mm1
  98:	0f 38 1c e1          	pabsb  mm4,mm1
  9c:	0f 38 1c e9          	pabsb  mm5,mm1
  a0:	0f 38 1c f1          	pabsb  mm6,mm1
  a4:	0f 38 1c f9          	pabsb  mm7,mm1
  a8:	0f 38 1c c1          	pabsb  mm0,mm1
  ac:	0f 38 1c d1          	pabsb  mm2,mm1
  b0:	0f 38 1c d9          	pabsb  mm3,mm1
  b4:	0f 38 1c e1          	pabsb  mm4,mm1
  b8:	0f 38 1c e9          	pabsb  mm5,mm1
  bc:	0f 38 1c f1          	pabsb  mm6,mm1
  c0:	0f 38 1c f9          	pabsb  mm7,mm1
  c4:	0f 38 1c c1          	pabsb  mm0,mm1
  c8:	0f 38 1c d1          	pabsb  mm2,mm1
  cc:	0f 38 1c d9          	pabsb  mm3,mm1
  d0:	0f 38 1c e1          	pabsb  mm4,mm1
  d4:	0f 38 1c e9          	pabsb  mm5,mm1
  d8:	0f 38 1c f1          	pabsb  mm6,mm1
  dc:	0f 38 1c f9          	pabsb  mm7,mm1
  e0:	0f 38 1c c1          	pabsb  mm0,mm1
  e4:	0f 38 1c d1          	pabsb  mm2,mm1
  e8:	0f 38 1c d9          	pabsb  mm3,mm1
  ec:	0f 38 1c e1          	pabsb  mm4,mm1
  f0:	0f 38 1c e9          	pabsb  mm5,mm1
  f4:	0f 38 1c f1          	pabsb  mm6,mm1
  f8:	0f 38 1c f9          	pabsb  mm7,mm1
  fc:	0f 38 1c c1          	pabsb  mm0,mm1
 100:	0f 38 1c d1          	pabsb  mm2,mm1
 104:	0f 38 1c d9          	pabsb  mm3,mm1
 108:	0f 38 1c e1          	pabsb  mm4,mm1
 10c:	0f 38 1c e9          	pabsb  mm5,mm1
 110:	0f 38 1c f1          	pabsb  mm6,mm1
 114:	0f 38 1c f9          	pabsb  mm7,mm1
 118:	0f 38 1c c1          	pabsb  mm0,mm1
 11c:	0f 38 1c d1          	pabsb  mm2,mm1
 120:	0f 38 1c d9          	pabsb  mm3,mm1
 124:	0f 38 1c e1          	pabsb  mm4,mm1
 128:	0f 38 1c e9          	pabsb  mm5,mm1
 12c:	0f 38 1c f1          	pabsb  mm6,mm1
 130:	0f 38 1c f9          	pabsb  mm7,mm1
 134:	0f 38 1c c1          	pabsb  mm0,mm1
 138:	0f 38 1c d1          	pabsb  mm2,mm1
 13c:	0f 38 1c d9          	pabsb  mm3,mm1
 140:	0f 38 1c e1          	pabsb  mm4,mm1
 144:	0f 38 1c e9          	pabsb  mm5,mm1
 148:	0f 38 1c f1          	pabsb  mm6,mm1
 14c:	0f 38 1c f9          	pabsb  mm7,mm1
 150:	0f 38 1c c1          	pabsb  mm0,mm1
 154:	0f 38 1c d1          	pabsb  mm2,mm1
 158:	0f 38 1c d9          	pabsb  mm3,mm1
 15c:	0f 38 1c e1          	pabsb  mm4,mm1
 160:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Init:
```
VZEROALL;
PXOR MM1, MM1
```
Show nanoBench command
Results:
- Instructions retired: 89.0
- Core cycles: 47.09
- Reference cycles: 55.27
- UOPS_PORT_5: 45.18
- UOPS_PORT_1: 44.82

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  81:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  88:	00 00 
  8a:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  91:	00 00 
  93:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  9a:	00 00 
  9c:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  a3:	00 00 
  a5:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  ac:	00 00 
  ae:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  b5:	00 00 
  b7:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  be:	00 00 
  c0:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  c7:	00 00 
  c9:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  d0:	00 00 
  d2:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  d8:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  de:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  e4:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  ea:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  f1:	00 00 
  f3:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  fa:	00 00 
  fc:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 103:	00 00 
 105:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 10c:	00 00 
 10e:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 115:	00 00 
 117:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 11e:	00 00 
 120:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 127:	00 00 
 129:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 130:	00 00 
 132:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 139:	00 00 
 13b:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 141:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 147:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 14d:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 153:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 15a:	00 00 
 15c:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 163:	00 00 
 165:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 16c:	00 00 
 16e:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 175:	00 00 
 177:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 17e:	00 00 
 180:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 187:	00 00 
 189:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 190:	00 00 
 192:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 199:	00 00 
 19b:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 1a2:	00 00 
 1a4:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 1aa:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 1b0:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 1b6:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 1bc:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 1c3:	00 00 
 1c5:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 1cc:	00 00 
 1ce:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 1d5:	00 00 
 1d7:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 1de:	00 00 
 1e0:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 1e7:	00 00 
 1e9:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 1f0:	00 00 
 1f2:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 1f9:	00 00 
 1fb:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 202:	00 00 
 204:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 20b:	00 00 
 20d:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 213:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 219:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 21f:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 225:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 22c:	00 00 
 22e:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 235:	00 00 
 237:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 23e:	00 00 
 240:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 247:	00 00 
 249:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 250:	00 00 
 252:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 259:	00 00 
 25b:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 262:	00 00 
 264:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 26b:	00 00 
 26d:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 274:	00 00 
 276:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 27c:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 282:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 288:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 28e:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 295:	00 00 
 297:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 29e:	00 00 
 2a0:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 2a7:	00 00 
 2a9:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 2b0:	00 00 
 2b2:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 2b9:	00 00 
 2bb:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 2c2:	00 00 
 2c4:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 89.0
- Core cycles: 50.86
- Reference cycles: 55.27
- UOPS_PORT_3: 45.23
- UOPS_PORT_2: 44.86

⇨ 2 μops that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	41 b0 00             	mov    r8b,0x0
   3:	41 b1 00             	mov    r9b,0x0
   6:	41 b2 00             	mov    r10b,0x0
   9:	41 b3 00             	mov    r11b,0x0
   c:	41 b4 00             	mov    r12b,0x0
   f:	b3 00                	mov    bl,0x0
  11:	b1 00                	mov    cl,0x0
  13:	b2 00                	mov    dl,0x0
  15:	41 b0 00             	mov    r8b,0x0
  18:	41 b1 00             	mov    r9b,0x0
  1b:	41 b2 00             	mov    r10b,0x0
  1e:	41 b3 00             	mov    r11b,0x0
  21:	41 b4 00             	mov    r12b,0x0
  24:	b3 00                	mov    bl,0x0
  26:	b1 00                	mov    cl,0x0
  28:	b2 00                	mov    dl,0x0
  2a:	41 b0 00             	mov    r8b,0x0
  2d:	41 b1 00             	mov    r9b,0x0
  30:	41 b2 00             	mov    r10b,0x0
  33:	41 b3 00             	mov    r11b,0x0
  36:	41 b4 00             	mov    r12b,0x0
  39:	b3 00                	mov    bl,0x0
  3b:	b1 00                	mov    cl,0x0
  3d:	b2 00                	mov    dl,0x0
  3f:	41 b0 00             	mov    r8b,0x0
  42:	41 b1 00             	mov    r9b,0x0
  45:	41 b2 00             	mov    r10b,0x0
  48:	41 b3 00             	mov    r11b,0x0
  4b:	41 b4 00             	mov    r12b,0x0
  4e:	b3 00                	mov    bl,0x0
  50:	b1 00                	mov    cl,0x0
  52:	b2 00                	mov    dl,0x0
  54:	41 b0 00             	mov    r8b,0x0
  57:	41 b1 00             	mov    r9b,0x0
  5a:	41 b2 00             	mov    r10b,0x0
  5d:	41 b3 00             	mov    r11b,0x0
  60:	41 b4 00             	mov    r12b,0x0
  63:	b3 00                	mov    bl,0x0
  65:	b1 00                	mov    cl,0x0
  67:	b2 00                	mov    dl,0x0
  69:	41 b0 00             	mov    r8b,0x0
  6c:	41 b1 00             	mov    r9b,0x0
  6f:	41 b2 00             	mov    r10b,0x0
  72:	41 b3 00             	mov    r11b,0x0
  75:	41 b4 00             	mov    r12b,0x0
  78:	b3 00                	mov    bl,0x0
  7a:	b1 00                	mov    cl,0x0
  7c:	b2 00                	mov    dl,0x0
  7e:	41 b0 00             	mov    r8b,0x0
  81:	41 b1 00             	mov    r9b,0x0
  84:	41 b2 00             	mov    r10b,0x0
  87:	41 b3 00             	mov    r11b,0x0
  8a:	41 b4 00             	mov    r12b,0x0
  8d:	b3 00                	mov    bl,0x0
  8f:	b1 00                	mov    cl,0x0
  91:	b2 00                	mov    dl,0x0
  93:	41 b0 00             	mov    r8b,0x0
  96:	41 b1 00             	mov    r9b,0x0
  99:	41 b2 00             	mov    r10b,0x0
  9c:	41 b3 00             	mov    r11b,0x0
  9f:	41 b4 00             	mov    r12b,0x0
  a2:	b3 00                	mov    bl,0x0
  a4:	b1 00                	mov    cl,0x0
  a6:	b2 00                	mov    dl,0x0
  a8:	41 b0 00             	mov    r8b,0x0
  ab:	41 b1 00             	mov    r9b,0x0
  ae:	41 b2 00             	mov    r10b,0x0
  b1:	41 b3 00             	mov    r11b,0x0
  b4:	41 b4 00             	mov    r12b,0x0
  b7:	b3 00                	mov    bl,0x0
  b9:	b1 00                	mov    cl,0x0
  bb:	b2 00                	mov    dl,0x0
  bd:	41 b0 00             	mov    r8b,0x0
  c0:	41 b1 00             	mov    r9b,0x0
  c3:	41 b2 00             	mov    r10b,0x0
  c6:	41 b3 00             	mov    r11b,0x0
  c9:	41 b4 00             	mov    r12b,0x0
  cc:	b3 00                	mov    bl,0x0
  ce:	b1 00                	mov    cl,0x0
  d0:	b2 00                	mov    dl,0x0
  d2:	41 b0 00             	mov    r8b,0x0
  d5:	41 b1 00             	mov    r9b,0x0
  d8:	41 b2 00             	mov    r10b,0x0
  db:	41 b3 00             	mov    r11b,0x0
  de:	41 b4 00             	mov    r12b,0x0
  e1:	b3 00                	mov    bl,0x0
  e3:	b1 00                	mov    cl,0x0
  e5:	b2 00                	mov    dl,0x0
  e7:	41 b0 00             	mov    r8b,0x0
  ea:	41 b1 00             	mov    r9b,0x0
  ed:	41 b2 00             	mov    r10b,0x0
  f0:	41 b3 00             	mov    r11b,0x0
  f3:	41 b4 00             	mov    r12b,0x0
  f6:	b3 00                	mov    bl,0x0
  f8:	b1 00                	mov    cl,0x0
  fa:	b2 00                	mov    dl,0x0
  fc:	41 b0 00             	mov    r8b,0x0
  ff:	41 b1 00             	mov    r9b,0x0
 102:	41 b2 00             	mov    r10b,0x0
 105:	41 b3 00             	mov    r11b,0x0
 108:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 101.0
- Core cycles: 44.6
- Reference cycles: 48.0
- UOPS_PORT_5: 35.28
- UOPS_PORT_0: 35.2
- UOPS_PORT_1: 34.78

⇨ 3 μops that can only use ports {'0', '1', '5'}

With an indexed addressing mode

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	0f 7e c2             	movd   edx,mm0
  1d:	41 0f 7e c0          	movd   r8d,mm0
  21:	41 0f 7e c1          	movd   r9d,mm0
  25:	41 0f 7e c2          	movd   r10d,mm0
  29:	41 0f 7e c3          	movd   r11d,mm0
  2d:	41 0f 7e c4          	movd   r12d,mm0
  31:	0f 7e c3             	movd   ebx,mm0
  34:	0f 7e c1             	movd   ecx,mm0
  37:	0f 7e c2             	movd   edx,mm0
  3a:	41 0f 7e c0          	movd   r8d,mm0
  3e:	41 0f 7e c1          	movd   r9d,mm0
  42:	41 0f 7e c2          	movd   r10d,mm0
  46:	41 0f 7e c3          	movd   r11d,mm0
  4a:	41 0f 7e c4          	movd   r12d,mm0
  4e:	0f 7e c3             	movd   ebx,mm0
  51:	0f 7e c1             	movd   ecx,mm0
  54:	0f 7e c2             	movd   edx,mm0
  57:	41 0f 7e c0          	movd   r8d,mm0
  5b:	41 0f 7e c1          	movd   r9d,mm0
  5f:	41 0f 7e c2          	movd   r10d,mm0
  63:	41 0f 7e c3          	movd   r11d,mm0
  67:	41 0f 7e c4          	movd   r12d,mm0
  6b:	0f 7e c3             	movd   ebx,mm0
  6e:	0f 7e c1             	movd   ecx,mm0
  71:	0f 7e c2             	movd   edx,mm0
  74:	41 0f 7e c0          	movd   r8d,mm0
  78:	41 0f 7e c1          	movd   r9d,mm0
  7c:	41 0f 7e c2          	movd   r10d,mm0
  80:	41 0f 7e c3          	movd   r11d,mm0
  84:	41 0f 7e c4          	movd   r12d,mm0
  88:	0f 7e c3             	movd   ebx,mm0
  8b:	0f 7e c1             	movd   ecx,mm0
  8e:	0f 7e c2             	movd   edx,mm0
  91:	41 0f 7e c0          	movd   r8d,mm0
  95:	41 0f 7e c1          	movd   r9d,mm0
  99:	41 0f 7e c2          	movd   r10d,mm0
  9d:	41 0f 7e c3          	movd   r11d,mm0
  a1:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
PXOR MM0, MM0;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 45.0
- Core cycles: 45.05
- Reference cycles: 49.45
- UOPS_PORT_0: 43.95

With blocking instructions for port '1':

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  30:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  35:	66 0f 58 c1          	addpd  xmm0,xmm1
  39:	66 0f 58 d1          	addpd  xmm2,xmm1
  3d:	66 0f 58 d9          	addpd  xmm3,xmm1
  41:	66 0f 58 e1          	addpd  xmm4,xmm1
  45:	66 0f 58 e9          	addpd  xmm5,xmm1
  49:	66 0f 58 f1          	addpd  xmm6,xmm1
  4d:	66 0f 58 f9          	addpd  xmm7,xmm1
  51:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  56:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  5b:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  60:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  65:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  6a:	66 0f 58 c1          	addpd  xmm0,xmm1
  6e:	66 0f 58 d1          	addpd  xmm2,xmm1
  72:	66 0f 58 d9          	addpd  xmm3,xmm1
  76:	66 0f 58 e1          	addpd  xmm4,xmm1
  7a:	66 0f 58 e9          	addpd  xmm5,xmm1
  7e:	66 0f 58 f1          	addpd  xmm6,xmm1
  82:	66 0f 58 f9          	addpd  xmm7,xmm1
  86:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  8b:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  90:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  95:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  9a:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  9f:	66 0f 58 c1          	addpd  xmm0,xmm1
  a3:	66 0f 58 d1          	addpd  xmm2,xmm1
  a7:	66 0f 58 d9          	addpd  xmm3,xmm1
  ab:	66 0f 58 e1          	addpd  xmm4,xmm1
  af:	66 0f 58 e9          	addpd  xmm5,xmm1
  b3:	66 0f 58 f1          	addpd  xmm6,xmm1
  b7:	66 0f 58 f9          	addpd  xmm7,xmm1
  bb:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  c0:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 45.0
- Core cycles: 45.59
- Reference cycles: 44.61
- UOPS_PORT_1: 43.95

With blocking instructions for port '4':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  35:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  3c:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  43:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  4a:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  51:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  58:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  5c:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  60:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  64:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  68:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  6c:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  70:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  74:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  78:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  7f:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  86:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  8d:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  94:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  9b:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  a2:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  a9:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  b0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  b4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  b8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  bc:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  c0:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  c4:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  c8:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  cc:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  d0:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  d7:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  de:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  e5:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  ec:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 45.0
- Core cycles: 66.64
- Reference cycles: 63.76
- UOPS_PORT_4: 46.95

⇨ One μop that can only use port '4'

With blocking instructions for port '5':

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	66 0f 55 c1          	andnpd xmm0,xmm1
  39:	66 0f 55 d1          	andnpd xmm2,xmm1
  3d:	66 0f 55 d9          	andnpd xmm3,xmm1
  41:	66 0f 55 e1          	andnpd xmm4,xmm1
  45:	66 0f 55 e9          	andnpd xmm5,xmm1
  49:	66 0f 55 f1          	andnpd xmm6,xmm1
  4d:	66 0f 55 f9          	andnpd xmm7,xmm1
  51:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  56:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  5b:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  60:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  65:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  6a:	66 0f 55 c1          	andnpd xmm0,xmm1
  6e:	66 0f 55 d1          	andnpd xmm2,xmm1
  72:	66 0f 55 d9          	andnpd xmm3,xmm1
  76:	66 0f 55 e1          	andnpd xmm4,xmm1
  7a:	66 0f 55 e9          	andnpd xmm5,xmm1
  7e:	66 0f 55 f1          	andnpd xmm6,xmm1
  82:	66 0f 55 f9          	andnpd xmm7,xmm1
  86:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  8b:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  90:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  95:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  9a:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  9f:	66 0f 55 c1          	andnpd xmm0,xmm1
  a3:	66 0f 55 d1          	andnpd xmm2,xmm1
  a7:	66 0f 55 d9          	andnpd xmm3,xmm1
  ab:	66 0f 55 e1          	andnpd xmm4,xmm1
  af:	66 0f 55 e9          	andnpd xmm5,xmm1
  b3:	66 0f 55 f1          	andnpd xmm6,xmm1
  b7:	66 0f 55 f9          	andnpd xmm7,xmm1
  bb:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  c0:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 45.0
- Core cycles: 47.0
- Reference cycles: 46.55
- UOPS_PORT_5: 46.0

⇨ 2 μops that can only use port '5'

With blocking instructions for ports {'0', '1'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	41 8d 16             	lea    edx,[r14]
  18:	45 8d 06             	lea    r8d,[r14]
  1b:	45 8d 0e             	lea    r9d,[r14]
  1e:	45 8d 16             	lea    r10d,[r14]
  21:	45 8d 1e             	lea    r11d,[r14]
  24:	45 8d 26             	lea    r12d,[r14]
  27:	41 8d 1e             	lea    ebx,[r14]
  2a:	41 8d 0e             	lea    ecx,[r14]
  2d:	41 8d 16             	lea    edx,[r14]
  30:	45 8d 06             	lea    r8d,[r14]
  33:	45 8d 0e             	lea    r9d,[r14]
  36:	45 8d 16             	lea    r10d,[r14]
  39:	45 8d 1e             	lea    r11d,[r14]
  3c:	45 8d 26             	lea    r12d,[r14]
  3f:	41 8d 1e             	lea    ebx,[r14]
  42:	41 8d 0e             	lea    ecx,[r14]
  45:	41 8d 16             	lea    edx,[r14]
  48:	45 8d 06             	lea    r8d,[r14]
  4b:	45 8d 0e             	lea    r9d,[r14]
  4e:	45 8d 16             	lea    r10d,[r14]
  51:	45 8d 1e             	lea    r11d,[r14]
  54:	45 8d 26             	lea    r12d,[r14]
  57:	41 8d 1e             	lea    ebx,[r14]
  5a:	41 8d 0e             	lea    ecx,[r14]
  5d:	41 8d 16             	lea    edx,[r14]
  60:	45 8d 06             	lea    r8d,[r14]
  63:	45 8d 0e             	lea    r9d,[r14]
  66:	45 8d 16             	lea    r10d,[r14]
  69:	45 8d 1e             	lea    r11d,[r14]
  6c:	45 8d 26             	lea    r12d,[r14]
  6f:	41 8d 1e             	lea    ebx,[r14]
  72:	41 8d 0e             	lea    ecx,[r14]
  75:	41 8d 16             	lea    edx,[r14]
  78:	45 8d 06             	lea    r8d,[r14]
  7b:	45 8d 0e             	lea    r9d,[r14]
  7e:	45 8d 16             	lea    r10d,[r14]
  81:	45 8d 1e             	lea    r11d,[r14]
  84:	45 8d 26             	lea    r12d,[r14]
  87:	41 8d 1e             	lea    ebx,[r14]
  8a:	41 8d 0e             	lea    ecx,[r14]
  8d:	41 8d 16             	lea    edx,[r14]
  90:	45 8d 06             	lea    r8d,[r14]
  93:	45 8d 0e             	lea    r9d,[r14]
  96:	45 8d 16             	lea    r10d,[r14]
  99:	45 8d 1e             	lea    r11d,[r14]
  9c:	45 8d 26             	lea    r12d,[r14]
  9f:	41 8d 1e             	lea    ebx,[r14]
  a2:	41 8d 0e             	lea    ecx,[r14]
  a5:	41 8d 16             	lea    edx,[r14]
  a8:	45 8d 06             	lea    r8d,[r14]
  ab:	45 8d 0e             	lea    r9d,[r14]
  ae:	45 8d 16             	lea    r10d,[r14]
  b1:	45 8d 1e             	lea    r11d,[r14]
  b4:	45 8d 26             	lea    r12d,[r14]
  b7:	41 8d 1e             	lea    ebx,[r14]
  ba:	41 8d 0e             	lea    ecx,[r14]
  bd:	41 8d 16             	lea    edx,[r14]
  c0:	45 8d 06             	lea    r8d,[r14]
  c3:	45 8d 0e             	lea    r9d,[r14]
  c6:	45 8d 16             	lea    r10d,[r14]
  c9:	45 8d 1e             	lea    r11d,[r14]
  cc:	45 8d 26             	lea    r12d,[r14]
  cf:	41 8d 1e             	lea    ebx,[r14]
  d2:	41 8d 0e             	lea    ecx,[r14]
  d5:	41 8d 16             	lea    edx,[r14]
  d8:	45 8d 06             	lea    r8d,[r14]
  db:	45 8d 0e             	lea    r9d,[r14]
  de:	45 8d 16             	lea    r10d,[r14]
  e1:	45 8d 1e             	lea    r11d,[r14]
  e4:	45 8d 26             	lea    r12d,[r14]
  e7:	41 8d 1e             	lea    ebx,[r14]
  ea:	41 8d 0e             	lea    ecx,[r14]
  ed:	41 8d 16             	lea    edx,[r14]
  f0:	45 8d 06             	lea    r8d,[r14]
  f3:	45 8d 0e             	lea    r9d,[r14]
  f6:	45 8d 16             	lea    r10d,[r14]
  f9:	45 8d 1e             	lea    r11d,[r14]
  fc:	45 8d 26             	lea    r12d,[r14]
  ff:	41 8d 1e             	lea    ebx,[r14]
 102:	41 8d 0e             	lea    ecx,[r14]
 105:	41 8d 16             	lea    edx,[r14]
 108:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 89.0
- Core cycles: 46.09
- Reference cycles: 45.58
- UOPS_PORT_0: 44.0
- UOPS_PORT_1: 43.91

With blocking instructions for ports {'0', '5'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 c1 c2 00          	rol    dx,0x0
  25:	66 41 c1 c0 00       	rol    r8w,0x0
  2a:	66 41 c1 c1 00       	rol    r9w,0x0
  2f:	66 41 c1 c2 00       	rol    r10w,0x0
  34:	66 41 c1 c3 00       	rol    r11w,0x0
  39:	66 41 c1 c4 00       	rol    r12w,0x0
  3e:	66 c1 c3 00          	rol    bx,0x0
  42:	66 c1 c1 00          	rol    cx,0x0
  46:	66 c1 c2 00          	rol    dx,0x0
  4a:	66 41 c1 c0 00       	rol    r8w,0x0
  4f:	66 41 c1 c1 00       	rol    r9w,0x0
  54:	66 41 c1 c2 00       	rol    r10w,0x0
  59:	66 41 c1 c3 00       	rol    r11w,0x0
  5e:	66 41 c1 c4 00       	rol    r12w,0x0
  63:	66 c1 c3 00          	rol    bx,0x0
  67:	66 c1 c1 00          	rol    cx,0x0
  6b:	66 c1 c2 00          	rol    dx,0x0
  6f:	66 41 c1 c0 00       	rol    r8w,0x0
  74:	66 41 c1 c1 00       	rol    r9w,0x0
  79:	66 41 c1 c2 00       	rol    r10w,0x0
  7e:	66 41 c1 c3 00       	rol    r11w,0x0
  83:	66 41 c1 c4 00       	rol    r12w,0x0
  88:	66 c1 c3 00          	rol    bx,0x0
  8c:	66 c1 c1 00          	rol    cx,0x0
  90:	66 c1 c2 00          	rol    dx,0x0
  94:	66 41 c1 c0 00       	rol    r8w,0x0
  99:	66 41 c1 c1 00       	rol    r9w,0x0
  9e:	66 41 c1 c2 00       	rol    r10w,0x0
  a3:	66 41 c1 c3 00       	rol    r11w,0x0
  a8:	66 41 c1 c4 00       	rol    r12w,0x0
  ad:	66 c1 c3 00          	rol    bx,0x0
  b1:	66 c1 c1 00          	rol    cx,0x0
  b5:	66 c1 c2 00          	rol    dx,0x0
  b9:	66 41 c1 c0 00       	rol    r8w,0x0
  be:	66 41 c1 c1 00       	rol    r9w,0x0
  c3:	66 41 c1 c2 00       	rol    r10w,0x0
  c8:	66 41 c1 c3 00       	rol    r11w,0x0
  cd:	66 41 c1 c4 00       	rol    r12w,0x0
  d2:	66 c1 c3 00          	rol    bx,0x0
  d6:	66 c1 c1 00          	rol    cx,0x0
  da:	66 c1 c2 00          	rol    dx,0x0
  de:	66 41 c1 c0 00       	rol    r8w,0x0
  e3:	66 41 c1 c1 00       	rol    r9w,0x0
  e8:	66 41 c1 c2 00       	rol    r10w,0x0
  ed:	66 41 c1 c3 00       	rol    r11w,0x0
  f2:	66 41 c1 c4 00       	rol    r12w,0x0
  f7:	66 c1 c3 00          	rol    bx,0x0
  fb:	66 c1 c1 00          	rol    cx,0x0
  ff:	66 c1 c2 00          	rol    dx,0x0
 103:	66 41 c1 c0 00       	rol    r8w,0x0
 108:	66 41 c1 c1 00       	rol    r9w,0x0
 10d:	66 41 c1 c2 00       	rol    r10w,0x0
 112:	66 41 c1 c3 00       	rol    r11w,0x0
 117:	66 41 c1 c4 00       	rol    r12w,0x0
 11c:	66 c1 c3 00          	rol    bx,0x0
 120:	66 c1 c1 00          	rol    cx,0x0
 124:	66 c1 c2 00          	rol    dx,0x0
 128:	66 41 c1 c0 00       	rol    r8w,0x0
 12d:	66 41 c1 c1 00       	rol    r9w,0x0
 132:	66 41 c1 c2 00       	rol    r10w,0x0
 137:	66 41 c1 c3 00       	rol    r11w,0x0
 13c:	66 41 c1 c4 00       	rol    r12w,0x0
 141:	66 c1 c3 00          	rol    bx,0x0
 145:	66 c1 c1 00          	rol    cx,0x0
 149:	66 c1 c2 00          	rol    dx,0x0
 14d:	66 41 c1 c0 00       	rol    r8w,0x0
 152:	66 41 c1 c1 00       	rol    r9w,0x0
 157:	66 41 c1 c2 00       	rol    r10w,0x0
 15c:	66 41 c1 c3 00       	rol    r11w,0x0
 161:	66 41 c1 c4 00       	rol    r12w,0x0
 166:	66 c1 c3 00          	rol    bx,0x0
 16a:	66 c1 c1 00          	rol    cx,0x0
 16e:	66 c1 c2 00          	rol    dx,0x0
 172:	66 41 c1 c0 00       	rol    r8w,0x0
 177:	66 41 c1 c1 00       	rol    r9w,0x0
 17c:	66 41 c1 c2 00       	rol    r10w,0x0
 181:	66 41 c1 c3 00       	rol    r11w,0x0
 186:	66 41 c1 c4 00       	rol    r12w,0x0
 18b:	66 c1 c3 00          	rol    bx,0x0
 18f:	66 c1 c1 00          	rol    cx,0x0
 193:	66 c1 c2 00          	rol    dx,0x0
 197:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 89.0
- Core cycles: 47.09
- Reference cycles: 46.06
- UOPS_PORT_5: 45.18
- UOPS_PORT_0: 44.91

With blocking instructions for ports {'1', '5'}:

Code:

   0:	0f 38 1c c1          	pabsb  mm0,mm1
   4:	0f 38 1c d1          	pabsb  mm2,mm1
   8:	0f 38 1c d9          	pabsb  mm3,mm1
   c:	0f 38 1c e1          	pabsb  mm4,mm1
  10:	0f 38 1c e9          	pabsb  mm5,mm1
  14:	0f 38 1c f1          	pabsb  mm6,mm1
  18:	0f 38 1c f9          	pabsb  mm7,mm1
  1c:	0f 38 1c c1          	pabsb  mm0,mm1
  20:	0f 38 1c d1          	pabsb  mm2,mm1
  24:	0f 38 1c d9          	pabsb  mm3,mm1
  28:	0f 38 1c e1          	pabsb  mm4,mm1
  2c:	0f 38 1c e9          	pabsb  mm5,mm1
  30:	0f 38 1c f1          	pabsb  mm6,mm1
  34:	0f 38 1c f9          	pabsb  mm7,mm1
  38:	0f 38 1c c1          	pabsb  mm0,mm1
  3c:	0f 38 1c d1          	pabsb  mm2,mm1
  40:	0f 38 1c d9          	pabsb  mm3,mm1
  44:	0f 38 1c e1          	pabsb  mm4,mm1
  48:	0f 38 1c e9          	pabsb  mm5,mm1
  4c:	0f 38 1c f1          	pabsb  mm6,mm1
  50:	0f 38 1c f9          	pabsb  mm7,mm1
  54:	0f 38 1c c1          	pabsb  mm0,mm1
  58:	0f 38 1c d1          	pabsb  mm2,mm1
  5c:	0f 38 1c d9          	pabsb  mm3,mm1
  60:	0f 38 1c e1          	pabsb  mm4,mm1
  64:	0f 38 1c e9          	pabsb  mm5,mm1
  68:	0f 38 1c f1          	pabsb  mm6,mm1
  6c:	0f 38 1c f9          	pabsb  mm7,mm1
  70:	0f 38 1c c1          	pabsb  mm0,mm1
  74:	0f 38 1c d1          	pabsb  mm2,mm1
  78:	0f 38 1c d9          	pabsb  mm3,mm1
  7c:	0f 38 1c e1          	pabsb  mm4,mm1
  80:	0f 38 1c e9          	pabsb  mm5,mm1
  84:	0f 38 1c f1          	pabsb  mm6,mm1
  88:	0f 38 1c f9          	pabsb  mm7,mm1
  8c:	0f 38 1c c1          	pabsb  mm0,mm1
  90:	0f 38 1c d1          	pabsb  mm2,mm1
  94:	0f 38 1c d9          	pabsb  mm3,mm1
  98:	0f 38 1c e1          	pabsb  mm4,mm1
  9c:	0f 38 1c e9          	pabsb  mm5,mm1
  a0:	0f 38 1c f1          	pabsb  mm6,mm1
  a4:	0f 38 1c f9          	pabsb  mm7,mm1
  a8:	0f 38 1c c1          	pabsb  mm0,mm1
  ac:	0f 38 1c d1          	pabsb  mm2,mm1
  b0:	0f 38 1c d9          	pabsb  mm3,mm1
  b4:	0f 38 1c e1          	pabsb  mm4,mm1
  b8:	0f 38 1c e9          	pabsb  mm5,mm1
  bc:	0f 38 1c f1          	pabsb  mm6,mm1
  c0:	0f 38 1c f9          	pabsb  mm7,mm1
  c4:	0f 38 1c c1          	pabsb  mm0,mm1
  c8:	0f 38 1c d1          	pabsb  mm2,mm1
  cc:	0f 38 1c d9          	pabsb  mm3,mm1
  d0:	0f 38 1c e1          	pabsb  mm4,mm1
  d4:	0f 38 1c e9          	pabsb  mm5,mm1
  d8:	0f 38 1c f1          	pabsb  mm6,mm1
  dc:	0f 38 1c f9          	pabsb  mm7,mm1
  e0:	0f 38 1c c1          	pabsb  mm0,mm1
  e4:	0f 38 1c d1          	pabsb  mm2,mm1
  e8:	0f 38 1c d9          	pabsb  mm3,mm1
  ec:	0f 38 1c e1          	pabsb  mm4,mm1
  f0:	0f 38 1c e9          	pabsb  mm5,mm1
  f4:	0f 38 1c f1          	pabsb  mm6,mm1
  f8:	0f 38 1c f9          	pabsb  mm7,mm1
  fc:	0f 38 1c c1          	pabsb  mm0,mm1
 100:	0f 38 1c d1          	pabsb  mm2,mm1
 104:	0f 38 1c d9          	pabsb  mm3,mm1
 108:	0f 38 1c e1          	pabsb  mm4,mm1
 10c:	0f 38 1c e9          	pabsb  mm5,mm1
 110:	0f 38 1c f1          	pabsb  mm6,mm1
 114:	0f 38 1c f9          	pabsb  mm7,mm1
 118:	0f 38 1c c1          	pabsb  mm0,mm1
 11c:	0f 38 1c d1          	pabsb  mm2,mm1
 120:	0f 38 1c d9          	pabsb  mm3,mm1
 124:	0f 38 1c e1          	pabsb  mm4,mm1
 128:	0f 38 1c e9          	pabsb  mm5,mm1
 12c:	0f 38 1c f1          	pabsb  mm6,mm1
 130:	0f 38 1c f9          	pabsb  mm7,mm1
 134:	0f 38 1c c1          	pabsb  mm0,mm1
 138:	0f 38 1c d1          	pabsb  mm2,mm1
 13c:	0f 38 1c d9          	pabsb  mm3,mm1
 140:	0f 38 1c e1          	pabsb  mm4,mm1
 144:	0f 38 1c e9          	pabsb  mm5,mm1
 148:	0f 38 1c f1          	pabsb  mm6,mm1
 14c:	0f 38 1c f9          	pabsb  mm7,mm1
 150:	0f 38 1c c1          	pabsb  mm0,mm1
 154:	0f 38 1c d1          	pabsb  mm2,mm1
 158:	0f 38 1c d9          	pabsb  mm3,mm1
 15c:	0f 38 1c e1          	pabsb  mm4,mm1
 160:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
PXOR MM1, MM1;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 89.0
- Core cycles: 47.09
- Reference cycles: 46.06
- UOPS_PORT_5: 45.18
- UOPS_PORT_1: 44.82

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  81:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  88:	00 00 
  8a:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  91:	00 00 
  93:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  9a:	00 00 
  9c:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  a3:	00 00 
  a5:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  ac:	00 00 
  ae:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  b5:	00 00 
  b7:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  be:	00 00 
  c0:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  c7:	00 00 
  c9:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  d0:	00 00 
  d2:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  d8:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  de:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  e4:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  ea:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  f1:	00 00 
  f3:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  fa:	00 00 
  fc:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 103:	00 00 
 105:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 10c:	00 00 
 10e:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 115:	00 00 
 117:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 11e:	00 00 
 120:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 127:	00 00 
 129:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 130:	00 00 
 132:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 139:	00 00 
 13b:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 141:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 147:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 14d:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 153:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 15a:	00 00 
 15c:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 163:	00 00 
 165:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 16c:	00 00 
 16e:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 175:	00 00 
 177:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 17e:	00 00 
 180:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 187:	00 00 
 189:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 190:	00 00 
 192:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 199:	00 00 
 19b:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 1a2:	00 00 
 1a4:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 1aa:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 1b0:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 1b6:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 1bc:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 1c3:	00 00 
 1c5:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 1cc:	00 00 
 1ce:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 1d5:	00 00 
 1d7:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 1de:	00 00 
 1e0:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 1e7:	00 00 
 1e9:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 1f0:	00 00 
 1f2:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 1f9:	00 00 
 1fb:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 202:	00 00 
 204:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 20b:	00 00 
 20d:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 213:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 219:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 21f:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 225:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 22c:	00 00 
 22e:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 235:	00 00 
 237:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 23e:	00 00 
 240:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 247:	00 00 
 249:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 250:	00 00 
 252:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 259:	00 00 
 25b:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 262:	00 00 
 264:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 26b:	00 00 
 26d:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 274:	00 00 
 276:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 27c:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 282:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 288:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 28e:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 295:	00 00 
 297:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 29e:	00 00 
 2a0:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 2a7:	00 00 
 2a9:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 2b0:	00 00 
 2b2:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 2b9:	00 00 
 2bb:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 2c2:	00 00 
 2c4:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 89.0
- Core cycles: 50.86
- Reference cycles: 49.45
- UOPS_PORT_3: 45.23
- UOPS_PORT_2: 44.86

⇨ 2 μops that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	41 b0 00             	mov    r8b,0x0
   3:	41 b1 00             	mov    r9b,0x0
   6:	41 b2 00             	mov    r10b,0x0
   9:	41 b3 00             	mov    r11b,0x0
   c:	41 b4 00             	mov    r12b,0x0
   f:	b3 00                	mov    bl,0x0
  11:	b1 00                	mov    cl,0x0
  13:	b2 00                	mov    dl,0x0
  15:	41 b0 00             	mov    r8b,0x0
  18:	41 b1 00             	mov    r9b,0x0
  1b:	41 b2 00             	mov    r10b,0x0
  1e:	41 b3 00             	mov    r11b,0x0
  21:	41 b4 00             	mov    r12b,0x0
  24:	b3 00                	mov    bl,0x0
  26:	b1 00                	mov    cl,0x0
  28:	b2 00                	mov    dl,0x0
  2a:	41 b0 00             	mov    r8b,0x0
  2d:	41 b1 00             	mov    r9b,0x0
  30:	41 b2 00             	mov    r10b,0x0
  33:	41 b3 00             	mov    r11b,0x0
  36:	41 b4 00             	mov    r12b,0x0
  39:	b3 00                	mov    bl,0x0
  3b:	b1 00                	mov    cl,0x0
  3d:	b2 00                	mov    dl,0x0
  3f:	41 b0 00             	mov    r8b,0x0
  42:	41 b1 00             	mov    r9b,0x0
  45:	41 b2 00             	mov    r10b,0x0
  48:	41 b3 00             	mov    r11b,0x0
  4b:	41 b4 00             	mov    r12b,0x0
  4e:	b3 00                	mov    bl,0x0
  50:	b1 00                	mov    cl,0x0
  52:	b2 00                	mov    dl,0x0
  54:	41 b0 00             	mov    r8b,0x0
  57:	41 b1 00             	mov    r9b,0x0
  5a:	41 b2 00             	mov    r10b,0x0
  5d:	41 b3 00             	mov    r11b,0x0
  60:	41 b4 00             	mov    r12b,0x0
  63:	b3 00                	mov    bl,0x0
  65:	b1 00                	mov    cl,0x0
  67:	b2 00                	mov    dl,0x0
  69:	41 b0 00             	mov    r8b,0x0
  6c:	41 b1 00             	mov    r9b,0x0
  6f:	41 b2 00             	mov    r10b,0x0
  72:	41 b3 00             	mov    r11b,0x0
  75:	41 b4 00             	mov    r12b,0x0
  78:	b3 00                	mov    bl,0x0
  7a:	b1 00                	mov    cl,0x0
  7c:	b2 00                	mov    dl,0x0
  7e:	41 b0 00             	mov    r8b,0x0
  81:	41 b1 00             	mov    r9b,0x0
  84:	41 b2 00             	mov    r10b,0x0
  87:	41 b3 00             	mov    r11b,0x0
  8a:	41 b4 00             	mov    r12b,0x0
  8d:	b3 00                	mov    bl,0x0
  8f:	b1 00                	mov    cl,0x0
  91:	b2 00                	mov    dl,0x0
  93:	41 b0 00             	mov    r8b,0x0
  96:	41 b1 00             	mov    r9b,0x0
  99:	41 b2 00             	mov    r10b,0x0
  9c:	41 b3 00             	mov    r11b,0x0
  9f:	41 b4 00             	mov    r12b,0x0
  a2:	b3 00                	mov    bl,0x0
  a4:	b1 00                	mov    cl,0x0
  a6:	b2 00                	mov    dl,0x0
  a8:	41 b0 00             	mov    r8b,0x0
  ab:	41 b1 00             	mov    r9b,0x0
  ae:	41 b2 00             	mov    r10b,0x0
  b1:	41 b3 00             	mov    r11b,0x0
  b4:	41 b4 00             	mov    r12b,0x0
  b7:	b3 00                	mov    bl,0x0
  b9:	b1 00                	mov    cl,0x0
  bb:	b2 00                	mov    dl,0x0
  bd:	41 b0 00             	mov    r8b,0x0
  c0:	41 b1 00             	mov    r9b,0x0
  c3:	41 b2 00             	mov    r10b,0x0
  c6:	41 b3 00             	mov    r11b,0x0
  c9:	41 b4 00             	mov    r12b,0x0
  cc:	b3 00                	mov    bl,0x0
  ce:	b1 00                	mov    cl,0x0
  d0:	b2 00                	mov    dl,0x0
  d2:	41 b0 00             	mov    r8b,0x0
  d5:	41 b1 00             	mov    r9b,0x0
  d8:	41 b2 00             	mov    r10b,0x0
  db:	41 b3 00             	mov    r11b,0x0
  de:	41 b4 00             	mov    r12b,0x0
  e1:	b3 00                	mov    bl,0x0
  e3:	b1 00                	mov    cl,0x0
  e5:	b2 00                	mov    dl,0x0
  e7:	41 b0 00             	mov    r8b,0x0
  ea:	41 b1 00             	mov    r9b,0x0
  ed:	41 b2 00             	mov    r10b,0x0
  f0:	41 b3 00             	mov    r11b,0x0
  f3:	41 b4 00             	mov    r12b,0x0
  f6:	b3 00                	mov    bl,0x0
  f8:	b1 00                	mov    cl,0x0
  fa:	b2 00                	mov    dl,0x0
  fc:	41 b0 00             	mov    r8b,0x0
  ff:	41 b1 00             	mov    r9b,0x0
 102:	41 b2 00             	mov    r10b,0x0
 105:	41 b3 00             	mov    r11b,0x0
 108:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 101.0
- Core cycles: 44.6
- Reference cycles: 44.27
- UOPS_PORT_5: 35.07
- UOPS_PORT_0: 35.32
- UOPS_PORT_1: 34.88

⇨ 3 μops that can only use ports {'0', '1', '5'}