DIV (R32) - Port Usage

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c1             	movd   ecx,mm0
  17:	41 0f 7e c0          	movd   r8d,mm0
  1b:	41 0f 7e c1          	movd   r9d,mm0
  1f:	41 0f 7e c2          	movd   r10d,mm0
  23:	41 0f 7e c3          	movd   r11d,mm0
  27:	41 0f 7e c4          	movd   r12d,mm0
  2b:	0f 7e c1             	movd   ecx,mm0
  2e:	41 0f 7e c0          	movd   r8d,mm0
  32:	41 0f 7e c1          	movd   r9d,mm0
  36:	41 0f 7e c2          	movd   r10d,mm0
  3a:	41 0f 7e c3          	movd   r11d,mm0
  3e:	41 0f 7e c4          	movd   r12d,mm0
  42:	0f 7e c1             	movd   ecx,mm0
  45:	48 c7 c0 00 00 00 00 	mov    rax,0x0
  4c:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
  53:	f7 f3                	div    ebx

Init:

PXOR MM0, MM0;
MOV EBX, 1;
MOV RAX, 0;
MOV RDX, 0

Show nanoBench command
Results:
- Instructions retired: 21.0
- Core cycles: 20.29
- Reference cycles: 22.5
- UOPS_PORT_0: 19.98

⇨ 2 μops that can only use port '0'

With blocking instructions for port '1':

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  30:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  35:	66 0f 58 c1          	addpd  xmm0,xmm1
  39:	66 0f 58 d1          	addpd  xmm2,xmm1
  3d:	66 0f 58 d9          	addpd  xmm3,xmm1
  41:	66 0f 58 e1          	addpd  xmm4,xmm1
  45:	66 0f 58 e9          	addpd  xmm5,xmm1
  49:	66 0f 58 f1          	addpd  xmm6,xmm1
  4d:	48 c7 c0 00 00 00 00 	mov    rax,0x0
  54:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
  5b:	f7 f3                	div    ebx

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14];
MOV EBX, 1;
MOV RAX, 0;
MOV RDX, 0

Show nanoBench command
Results:
- Instructions retired: 21.0
- Core cycles: 20.55
- Reference cycles: 22.69
- UOPS_PORT_1: 19.98

⇨ 2 μops that can only use port '1'

With blocking instructions for port '5':

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	66 0f 55 c1          	andnpd xmm0,xmm1
  39:	66 0f 55 d1          	andnpd xmm2,xmm1
  3d:	66 0f 55 d9          	andnpd xmm3,xmm1
  41:	66 0f 55 e1          	andnpd xmm4,xmm1
  45:	66 0f 55 e9          	andnpd xmm5,xmm1
  49:	66 0f 55 f1          	andnpd xmm6,xmm1
  4d:	48 c7 c0 00 00 00 00 	mov    rax,0x0
  54:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
  5b:	f7 f3                	div    ebx

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
MOV EBX, 1;
MOV RAX, 0;
MOV RDX, 0

Show nanoBench command
Results:
- Instructions retired: 21.0
- Core cycles: 21.38
- Reference cycles: 23.47
- UOPS_PORT_5: 21.0

⇨ 3 μops that can only use port '5'

With blocking instructions for ports {'0', '1'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 0e             	lea    ecx,[r14]
  12:	45 8d 06             	lea    r8d,[r14]
  15:	45 8d 0e             	lea    r9d,[r14]
  18:	45 8d 16             	lea    r10d,[r14]
  1b:	45 8d 1e             	lea    r11d,[r14]
  1e:	45 8d 26             	lea    r12d,[r14]
  21:	41 8d 0e             	lea    ecx,[r14]
  24:	45 8d 06             	lea    r8d,[r14]
  27:	45 8d 0e             	lea    r9d,[r14]
  2a:	45 8d 16             	lea    r10d,[r14]
  2d:	45 8d 1e             	lea    r11d,[r14]
  30:	45 8d 26             	lea    r12d,[r14]
  33:	41 8d 0e             	lea    ecx,[r14]
  36:	45 8d 06             	lea    r8d,[r14]
  39:	45 8d 0e             	lea    r9d,[r14]
  3c:	45 8d 16             	lea    r10d,[r14]
  3f:	45 8d 1e             	lea    r11d,[r14]
  42:	45 8d 26             	lea    r12d,[r14]
  45:	41 8d 0e             	lea    ecx,[r14]
  48:	45 8d 06             	lea    r8d,[r14]
  4b:	45 8d 0e             	lea    r9d,[r14]
  4e:	45 8d 16             	lea    r10d,[r14]
  51:	45 8d 1e             	lea    r11d,[r14]
  54:	45 8d 26             	lea    r12d,[r14]
  57:	41 8d 0e             	lea    ecx,[r14]
  5a:	45 8d 06             	lea    r8d,[r14]
  5d:	45 8d 0e             	lea    r9d,[r14]
  60:	45 8d 16             	lea    r10d,[r14]
  63:	45 8d 1e             	lea    r11d,[r14]
  66:	45 8d 26             	lea    r12d,[r14]
  69:	41 8d 0e             	lea    ecx,[r14]
  6c:	48 c7 c0 00 00 00 00 	mov    rax,0x0
  73:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
  7a:	f7 f3                	div    ebx

Init:
```
MOV EBX, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 39.0
- Core cycles: 20.78
- Reference cycles: 23.31
- UOPS_PORT_0: 19.96
- UOPS_PORT_1: 19.96

With blocking instructions for ports {'0', '5'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c1 00          	rol    cx,0x0
  1d:	66 41 c1 c0 00       	rol    r8w,0x0
  22:	66 41 c1 c1 00       	rol    r9w,0x0
  27:	66 41 c1 c2 00       	rol    r10w,0x0
  2c:	66 41 c1 c3 00       	rol    r11w,0x0
  31:	66 41 c1 c4 00       	rol    r12w,0x0
  36:	66 c1 c1 00          	rol    cx,0x0
  3a:	66 41 c1 c0 00       	rol    r8w,0x0
  3f:	66 41 c1 c1 00       	rol    r9w,0x0
  44:	66 41 c1 c2 00       	rol    r10w,0x0
  49:	66 41 c1 c3 00       	rol    r11w,0x0
  4e:	66 41 c1 c4 00       	rol    r12w,0x0
  53:	66 c1 c1 00          	rol    cx,0x0
  57:	66 41 c1 c0 00       	rol    r8w,0x0
  5c:	66 41 c1 c1 00       	rol    r9w,0x0
  61:	66 41 c1 c2 00       	rol    r10w,0x0
  66:	66 41 c1 c3 00       	rol    r11w,0x0
  6b:	66 41 c1 c4 00       	rol    r12w,0x0
  70:	66 c1 c1 00          	rol    cx,0x0
  74:	66 41 c1 c0 00       	rol    r8w,0x0
  79:	66 41 c1 c1 00       	rol    r9w,0x0
  7e:	66 41 c1 c2 00       	rol    r10w,0x0
  83:	66 41 c1 c3 00       	rol    r11w,0x0
  88:	66 41 c1 c4 00       	rol    r12w,0x0
  8d:	66 c1 c1 00          	rol    cx,0x0
  91:	66 41 c1 c0 00       	rol    r8w,0x0
  96:	66 41 c1 c1 00       	rol    r9w,0x0
  9b:	66 41 c1 c2 00       	rol    r10w,0x0
  a0:	66 41 c1 c3 00       	rol    r11w,0x0
  a5:	66 41 c1 c4 00       	rol    r12w,0x0
  aa:	66 c1 c1 00          	rol    cx,0x0
  ae:	48 c7 c0 00 00 00 00 	mov    rax,0x0
  b5:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
  bc:	f7 f3                	div    ebx

Init:
```
MOV EBX, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 39.0
- Core cycles: 22.26
- Reference cycles: 24.69
- UOPS_PORT_5: 21.56
- UOPS_PORT_0: 21.41

⇨ 2 μops that can only use ports {'0', '5'}

With blocking instructions for ports {'1', '5'}:

Code:

   0:	0f 38 1c c1          	pabsb  mm0,mm1
   4:	0f 38 1c d1          	pabsb  mm2,mm1
   8:	0f 38 1c d9          	pabsb  mm3,mm1
   c:	0f 38 1c e1          	pabsb  mm4,mm1
  10:	0f 38 1c e9          	pabsb  mm5,mm1
  14:	0f 38 1c f1          	pabsb  mm6,mm1
  18:	0f 38 1c f9          	pabsb  mm7,mm1
  1c:	0f 38 1c c1          	pabsb  mm0,mm1
  20:	0f 38 1c d1          	pabsb  mm2,mm1
  24:	0f 38 1c d9          	pabsb  mm3,mm1
  28:	0f 38 1c e1          	pabsb  mm4,mm1
  2c:	0f 38 1c e9          	pabsb  mm5,mm1
  30:	0f 38 1c f1          	pabsb  mm6,mm1
  34:	0f 38 1c f9          	pabsb  mm7,mm1
  38:	0f 38 1c c1          	pabsb  mm0,mm1
  3c:	0f 38 1c d1          	pabsb  mm2,mm1
  40:	0f 38 1c d9          	pabsb  mm3,mm1
  44:	0f 38 1c e1          	pabsb  mm4,mm1
  48:	0f 38 1c e9          	pabsb  mm5,mm1
  4c:	0f 38 1c f1          	pabsb  mm6,mm1
  50:	0f 38 1c f9          	pabsb  mm7,mm1
  54:	0f 38 1c c1          	pabsb  mm0,mm1
  58:	0f 38 1c d1          	pabsb  mm2,mm1
  5c:	0f 38 1c d9          	pabsb  mm3,mm1
  60:	0f 38 1c e1          	pabsb  mm4,mm1
  64:	0f 38 1c e9          	pabsb  mm5,mm1
  68:	0f 38 1c f1          	pabsb  mm6,mm1
  6c:	0f 38 1c f9          	pabsb  mm7,mm1
  70:	0f 38 1c c1          	pabsb  mm0,mm1
  74:	0f 38 1c d1          	pabsb  mm2,mm1
  78:	0f 38 1c d9          	pabsb  mm3,mm1
  7c:	0f 38 1c e1          	pabsb  mm4,mm1
  80:	0f 38 1c e9          	pabsb  mm5,mm1
  84:	0f 38 1c f1          	pabsb  mm6,mm1
  88:	0f 38 1c f9          	pabsb  mm7,mm1
  8c:	0f 38 1c c1          	pabsb  mm0,mm1
  90:	48 c7 c0 00 00 00 00 	mov    rax,0x0
  97:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
  9e:	f7 f3                	div    ebx

Init:

VZEROALL;
PXOR MM1, MM1;
MOV EBX, 1;
MOV RAX, 0;
MOV RDX, 0

Show nanoBench command
Results:
- Instructions retired: 39.0
- Core cycles: 22.44
- Reference cycles: 24.89
- UOPS_PORT_5: 21.56
- UOPS_PORT_1: 19.41

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	41 b0 00             	mov    r8b,0x0
   3:	41 b1 00             	mov    r9b,0x0
   6:	41 b2 00             	mov    r10b,0x0
   9:	41 b3 00             	mov    r11b,0x0
   c:	41 b4 00             	mov    r12b,0x0
   f:	b1 00                	mov    cl,0x0
  11:	41 b0 00             	mov    r8b,0x0
  14:	41 b1 00             	mov    r9b,0x0
  17:	41 b2 00             	mov    r10b,0x0
  1a:	41 b3 00             	mov    r11b,0x0
  1d:	41 b4 00             	mov    r12b,0x0
  20:	b1 00                	mov    cl,0x0
  22:	41 b0 00             	mov    r8b,0x0
  25:	41 b1 00             	mov    r9b,0x0
  28:	41 b2 00             	mov    r10b,0x0
  2b:	41 b3 00             	mov    r11b,0x0
  2e:	41 b4 00             	mov    r12b,0x0
  31:	b1 00                	mov    cl,0x0
  33:	41 b0 00             	mov    r8b,0x0
  36:	41 b1 00             	mov    r9b,0x0
  39:	41 b2 00             	mov    r10b,0x0
  3c:	41 b3 00             	mov    r11b,0x0
  3f:	41 b4 00             	mov    r12b,0x0
  42:	b1 00                	mov    cl,0x0
  44:	41 b0 00             	mov    r8b,0x0
  47:	41 b1 00             	mov    r9b,0x0
  4a:	41 b2 00             	mov    r10b,0x0
  4d:	41 b3 00             	mov    r11b,0x0
  50:	41 b4 00             	mov    r12b,0x0
  53:	b1 00                	mov    cl,0x0
  55:	41 b0 00             	mov    r8b,0x0
  58:	41 b1 00             	mov    r9b,0x0
  5b:	41 b2 00             	mov    r10b,0x0
  5e:	41 b3 00             	mov    r11b,0x0
  61:	41 b4 00             	mov    r12b,0x0
  64:	b1 00                	mov    cl,0x0
  66:	41 b0 00             	mov    r8b,0x0
  69:	41 b1 00             	mov    r9b,0x0
  6c:	41 b2 00             	mov    r10b,0x0
  6f:	41 b3 00             	mov    r11b,0x0
  72:	41 b4 00             	mov    r12b,0x0
  75:	b1 00                	mov    cl,0x0
  77:	41 b0 00             	mov    r8b,0x0
  7a:	41 b1 00             	mov    r9b,0x0
  7d:	41 b2 00             	mov    r10b,0x0
  80:	41 b3 00             	mov    r11b,0x0
  83:	41 b4 00             	mov    r12b,0x0
  86:	b1 00                	mov    cl,0x0
  88:	41 b0 00             	mov    r8b,0x0
  8b:	41 b1 00             	mov    r9b,0x0
  8e:	41 b2 00             	mov    r10b,0x0
  91:	41 b3 00             	mov    r11b,0x0
  94:	41 b4 00             	mov    r12b,0x0
  97:	b1 00                	mov    cl,0x0
  99:	48 c7 c0 00 00 00 00 	mov    rax,0x0
  a0:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
  a7:	f7 f3                	div    ebx

Init:
```
MOV EBX, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 57.0
- Core cycles: 26.89
- Reference cycles: 29.63
- UOPS_PORT_5: 23.22
- UOPS_PORT_0: 21.11
- UOPS_PORT_1: 21.67

⇨ One μop that can only use ports {'0', '1', '5'}