DIVPS (XMM, M128) - Port Usage

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	0f 7e c2             	movd   edx,mm0
  1d:	41 0f 7e c0          	movd   r8d,mm0
  21:	41 0f 7e c1          	movd   r9d,mm0
  25:	41 0f 7e c2          	movd   r10d,mm0
  29:	41 0f 7e c3          	movd   r11d,mm0
  2d:	41 0f 7e c4          	movd   r12d,mm0
  31:	0f 7e c3             	movd   ebx,mm0
  34:	0f 10 d1             	movups xmm2,xmm1
  37:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

PXOR MM0, MM0;
VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 15.18
- Reference cycles: 14.87
- UOPS_PORT_0: 15.0

⇨ One μop that can only use port '0'

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  12:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  18:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
  31:	00 00 
  33:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 9e e0 00 	lddqu  xmm11,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 a6 f0 00 	lddqu  xmm12,[r14+0xf0]
  5e:	00 00 
  60:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  66:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  6c:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  72:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  78:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
  7f:	00 00 
  81:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
  88:	00 00 
  8a:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
  91:	00 00 
  93:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
  9a:	00 00 
  9c:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
  a3:	00 00 
  a5:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
  ac:	00 00 
  ae:	f2 45 0f f0 9e e0 00 	lddqu  xmm11,[r14+0xe0]
  b5:	00 00 
  b7:	f2 45 0f f0 a6 f0 00 	lddqu  xmm12,[r14+0xf0]
  be:	00 00 
  c0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  c6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  cc:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  d2:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  d8:	0f 10 d1             	movups xmm2,xmm1
  db:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 30.0
- Core cycles: 15.37
- Reference cycles: 14.78
- UOPS_PORT_3: 14.49
- UOPS_PORT_2: 14.49

⇨ One μop that can only use ports {'2', '3'}

With an indexed addressing mode

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	0f 7e c2             	movd   edx,mm0
  1d:	41 0f 7e c0          	movd   r8d,mm0
  21:	41 0f 7e c1          	movd   r9d,mm0
  25:	41 0f 7e c2          	movd   r10d,mm0
  29:	41 0f 7e c3          	movd   r11d,mm0
  2d:	41 0f 7e c4          	movd   r12d,mm0
  31:	0f 7e c3             	movd   ebx,mm0
  34:	0f 10 d1             	movups xmm2,xmm1
  37:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

PXOR MM0, MM0;
VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 15.18
- Reference cycles: 14.8
- UOPS_PORT_0: 15.0

⇨ One μop that can only use port '0'

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  12:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  18:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
  31:	00 00 
  33:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 9e e0 00 	lddqu  xmm11,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 a6 f0 00 	lddqu  xmm12,[r14+0xf0]
  5e:	00 00 
  60:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  66:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  6c:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  72:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  78:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
  7f:	00 00 
  81:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
  88:	00 00 
  8a:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
  91:	00 00 
  93:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
  9a:	00 00 
  9c:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
  a3:	00 00 
  a5:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
  ac:	00 00 
  ae:	f2 45 0f f0 9e e0 00 	lddqu  xmm11,[r14+0xe0]
  b5:	00 00 
  b7:	f2 45 0f f0 a6 f0 00 	lddqu  xmm12,[r14+0xf0]
  be:	00 00 
  c0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  c6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  cc:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  d2:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  d8:	0f 10 d1             	movups xmm2,xmm1
  db:	41 0f 5e 16          	divps  xmm2,XMMWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV RBX, 0x3f8000003f800000;
MOV [R14+0], RBX;
MOV [R14+8], RBX;
MOV [R14+16], RBX;
MOV [R14+24], RBX;
MOV [R14+32], RBX;
MOV [R14+40], RBX;
MOV [R14+48], RBX;
MOV [R14+56], RBX;
MOV [R14+64], RAX;
MOV [R14+72], RAX;
MOV [R14+80], RAX;
MOV [R14+88], RAX;
MOV [R14+96], RAX;
MOV [R14+104], RAX;
MOV [R14+112], RAX;
MOV [R14+120], RAX;
MOVUPS XMM0, [R14];
MOVUPS XMM1, [R14+64];
MOVUPS XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 30.0
- Core cycles: 15.37
- Reference cycles: 14.93
- UOPS_PORT_3: 14.49
- UOPS_PORT_2: 14.49

⇨ One μop that can only use ports {'2', '3'}