DIVPS (XMM, M128) - Port Usage (IACA 2.3)
With blocking instructions for port '0':
Throughput Analysis Report
--------------------------
Block Throughput: 25.00 Cycles Throughput Bottleneck: Backend. Port0
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 25.0 7.0 | 0.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm0, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm3, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm4, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm5, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm6, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm7, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm8, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm9, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm10, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm11, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm12, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm0, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm3, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm4, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm5, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm6, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm7, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm8, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm9, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm10, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm11, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm12, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm0, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm3, xmm1
| 2^ | 1.0 7.0 | | 0.5 0.5 | 0.5 0.5 | | | CP | divps xmm2, xmmword ptr [r14]
Total Num Of Uops: 26
⇨ One μop that can only use port '0'
With blocking instructions for ports {'2', '3'}:
Throughput Analysis Report
--------------------------
Block Throughput: 24.50 Cycles Throughput Bottleneck: Backend. PORT2_AGU, Port2_DATA, PORT3_AGU, Port3_DATA
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 1.0 7.0 | 0.0 | 24.5 24.5 | 24.5 24.5 | 0.0 | 0.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm0, xmmword ptr [r14+0x40]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm1, xmmword ptr [r14+0x50]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm3, xmmword ptr [r14+0x60]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm4, xmmword ptr [r14+0x70]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm5, xmmword ptr [r14+0x80]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm6, xmmword ptr [r14+0x90]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm7, xmmword ptr [r14+0xa0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm8, xmmword ptr [r14+0xb0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm9, xmmword ptr [r14+0xc0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm10, xmmword ptr [r14+0xd0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm11, xmmword ptr [r14+0xe0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm12, xmmword ptr [r14+0xf0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm0, xmmword ptr [r14+0x40]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm1, xmmword ptr [r14+0x50]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm3, xmmword ptr [r14+0x60]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm4, xmmword ptr [r14+0x70]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm5, xmmword ptr [r14+0x80]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm6, xmmword ptr [r14+0x90]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm7, xmmword ptr [r14+0xa0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm8, xmmword ptr [r14+0xb0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm9, xmmword ptr [r14+0xc0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm10, xmmword ptr [r14+0xd0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm11, xmmword ptr [r14+0xe0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm12, xmmword ptr [r14+0xf0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm0, xmmword ptr [r14+0x40]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm1, xmmword ptr [r14+0x50]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm3, xmmword ptr [r14+0x60]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm4, xmmword ptr [r14+0x70]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm5, xmmword ptr [r14+0x80]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm6, xmmword ptr [r14+0x90]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm7, xmmword ptr [r14+0xa0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm8, xmmword ptr [r14+0xb0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm9, xmmword ptr [r14+0xc0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm10, xmmword ptr [r14+0xd0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm11, xmmword ptr [r14+0xe0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm12, xmmword ptr [r14+0xf0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm0, xmmword ptr [r14+0x40]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm1, xmmword ptr [r14+0x50]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm3, xmmword ptr [r14+0x60]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm4, xmmword ptr [r14+0x70]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm5, xmmword ptr [r14+0x80]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm6, xmmword ptr [r14+0x90]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm7, xmmword ptr [r14+0xa0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm8, xmmword ptr [r14+0xb0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm9, xmmword ptr [r14+0xc0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm10, xmmword ptr [r14+0xd0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm11, xmmword ptr [r14+0xe0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm12, xmmword ptr [r14+0xf0]
| 2^ | 1.0 7.0 | | 0.5 0.5 | 0.5 0.5 | | | CP | divps xmm2, xmmword ptr [r14]
Total Num Of Uops: 50
⇨ One μop that can only use ports {'2', '3'}
With an indexed addressing mode
With blocking instructions for port '0':
Throughput Analysis Report
--------------------------
Block Throughput: 25.00 Cycles Throughput Bottleneck: Backend. Port0
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 25.0 7.0 | 0.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm0, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm3, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm4, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm5, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm6, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm7, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm8, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm9, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm10, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm11, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm12, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm0, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm3, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm4, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm5, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm6, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm7, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm8, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm9, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm10, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm11, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm12, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm0, xmm1
| 1 | 1.0 | | | | | | CP | cvtss2sd xmm3, xmm1
| 2^ | 1.0 7.0 | | 0.5 0.5 | 0.5 0.5 | | | CP | divps xmm2, xmmword ptr [r14]
Total Num Of Uops: 26
⇨ One μop that can only use port '0'
With blocking instructions for ports {'2', '3'}:
Throughput Analysis Report
--------------------------
Block Throughput: 24.50 Cycles Throughput Bottleneck: Backend. PORT2_AGU, Port2_DATA, PORT3_AGU, Port3_DATA
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 1.0 7.0 | 0.0 | 24.5 24.5 | 24.5 24.5 | 0.0 | 0.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm0, xmmword ptr [r14+0x40]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm1, xmmword ptr [r14+0x50]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm3, xmmword ptr [r14+0x60]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm4, xmmword ptr [r14+0x70]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm5, xmmword ptr [r14+0x80]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm6, xmmword ptr [r14+0x90]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm7, xmmword ptr [r14+0xa0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm8, xmmword ptr [r14+0xb0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm9, xmmword ptr [r14+0xc0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm10, xmmword ptr [r14+0xd0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm11, xmmword ptr [r14+0xe0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm12, xmmword ptr [r14+0xf0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm0, xmmword ptr [r14+0x40]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm1, xmmword ptr [r14+0x50]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm3, xmmword ptr [r14+0x60]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm4, xmmword ptr [r14+0x70]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm5, xmmword ptr [r14+0x80]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm6, xmmword ptr [r14+0x90]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm7, xmmword ptr [r14+0xa0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm8, xmmword ptr [r14+0xb0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm9, xmmword ptr [r14+0xc0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm10, xmmword ptr [r14+0xd0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm11, xmmword ptr [r14+0xe0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm12, xmmword ptr [r14+0xf0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm0, xmmword ptr [r14+0x40]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm1, xmmword ptr [r14+0x50]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm3, xmmword ptr [r14+0x60]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm4, xmmword ptr [r14+0x70]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm5, xmmword ptr [r14+0x80]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm6, xmmword ptr [r14+0x90]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm7, xmmword ptr [r14+0xa0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm8, xmmword ptr [r14+0xb0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm9, xmmword ptr [r14+0xc0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm10, xmmword ptr [r14+0xd0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm11, xmmword ptr [r14+0xe0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm12, xmmword ptr [r14+0xf0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm0, xmmword ptr [r14+0x40]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm1, xmmword ptr [r14+0x50]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm3, xmmword ptr [r14+0x60]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm4, xmmword ptr [r14+0x70]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm5, xmmword ptr [r14+0x80]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm6, xmmword ptr [r14+0x90]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm7, xmmword ptr [r14+0xa0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm8, xmmword ptr [r14+0xb0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm9, xmmword ptr [r14+0xc0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm10, xmmword ptr [r14+0xd0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm11, xmmword ptr [r14+0xe0]
| 1 | | | 0.5 0.5 | 0.5 0.5 | | | CP | lddqu xmm12, xmmword ptr [r14+0xf0]
| 2^ | 1.0 7.0 | | 0.5 0.5 | 0.5 0.5 | | | CP | divps xmm2, xmmword ptr [r14]
Total Num Of Uops: 50
⇨ One μop that can only use ports {'2', '3'}