CMOVB (R32, R32) - Port Usage

With blocking instructions for port '1':

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	45 0f 42 c1          	cmovb  r8d,r9d

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.17
- Reference cycles: 11.2
- UOPS_PORT_1: 9.99

With blocking instructions for ports {'0', '1'}:

Code:

   0:	45 8d 16             	lea    r10d,[r14]
   3:	45 8d 1e             	lea    r11d,[r14]
   6:	45 8d 26             	lea    r12d,[r14]
   9:	41 8d 1e             	lea    ebx,[r14]
   c:	41 8d 0e             	lea    ecx,[r14]
   f:	41 8d 16             	lea    edx,[r14]
  12:	45 8d 16             	lea    r10d,[r14]
  15:	45 8d 1e             	lea    r11d,[r14]
  18:	45 8d 26             	lea    r12d,[r14]
  1b:	41 8d 1e             	lea    ebx,[r14]
  1e:	45 0f 42 c1          	cmovb  r8d,r9d

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.05
- Reference cycles: 5.49
- UOPS_PORT_0: 5.0
- UOPS_PORT_1: 4.99

With blocking instructions for ports {'0', '5'}:

Code:

   0:	66 41 c1 c2 00       	rol    r10w,0x0
   5:	66 41 c1 c3 00       	rol    r11w,0x0
   a:	66 41 c1 c4 00       	rol    r12w,0x0
   f:	66 c1 c3 00          	rol    bx,0x0
  13:	66 c1 c1 00          	rol    cx,0x0
  17:	66 c1 c2 00          	rol    dx,0x0
  1b:	66 41 c1 c2 00       	rol    r10w,0x0
  20:	66 41 c1 c3 00       	rol    r11w,0x0
  25:	66 41 c1 c4 00       	rol    r12w,0x0
  2a:	66 c1 c3 00          	rol    bx,0x0
  2e:	45 0f 42 c1          	cmovb  r8d,r9d

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.55
- Reference cycles: 6.08
- UOPS_PORT_5: 5.5
- UOPS_PORT_0: 5.5

⇨ One μop that can only use ports {'0', '5'}

With blocking instructions for ports {'1', '5'}:

Code:

   0:	0f 38 1c c1          	pabsb  mm0,mm1
   4:	0f 38 1c d1          	pabsb  mm2,mm1
   8:	0f 38 1c d9          	pabsb  mm3,mm1
   c:	0f 38 1c e1          	pabsb  mm4,mm1
  10:	0f 38 1c e9          	pabsb  mm5,mm1
  14:	0f 38 1c f1          	pabsb  mm6,mm1
  18:	0f 38 1c f9          	pabsb  mm7,mm1
  1c:	0f 38 1c c1          	pabsb  mm0,mm1
  20:	0f 38 1c d1          	pabsb  mm2,mm1
  24:	0f 38 1c d9          	pabsb  mm3,mm1
  28:	45 0f 42 c1          	cmovb  r8d,r9d

Init:
```
VZEROALL;
PXOR MM1, MM1
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.05
- Reference cycles: 5.55
- UOPS_PORT_5: 5.0
- UOPS_PORT_1: 5.0

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	41 b2 00             	mov    r10b,0x0
   3:	41 b3 00             	mov    r11b,0x0
   6:	41 b4 00             	mov    r12b,0x0
   9:	b3 00                	mov    bl,0x0
   b:	b1 00                	mov    cl,0x0
   d:	b2 00                	mov    dl,0x0
   f:	41 b2 00             	mov    r10b,0x0
  12:	41 b3 00             	mov    r11b,0x0
  15:	41 b4 00             	mov    r12b,0x0
  18:	b3 00                	mov    bl,0x0
  1a:	45 0f 42 c1          	cmovb  r8d,r9d

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 4.06
- Reference cycles: 4.48
- UOPS_PORT_5: 4.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.0

⇨ One μop that can only use ports {'0', '1', '5'}