AESENC (XMM, XMM) - Port Usage

With blocking instructions for port '5':

Code:

   0:	66 0f 55 d3          	andnpd xmm2,xmm3
   4:	66 0f 55 e3          	andnpd xmm4,xmm3
   8:	66 0f 55 eb          	andnpd xmm5,xmm3
   c:	66 0f 55 f3          	andnpd xmm6,xmm3
  10:	66 0f 55 fb          	andnpd xmm7,xmm3
  14:	66 44 0f 55 c3       	andnpd xmm8,xmm3
  19:	66 44 0f 55 cb       	andnpd xmm9,xmm3
  1e:	66 44 0f 55 d3       	andnpd xmm10,xmm3
  23:	66 44 0f 55 db       	andnpd xmm11,xmm3
  28:	66 44 0f 55 e3       	andnpd xmm12,xmm3
  2d:	66 0f 55 d3          	andnpd xmm2,xmm3
  31:	66 0f 55 e3          	andnpd xmm4,xmm3
  35:	66 0f 55 eb          	andnpd xmm5,xmm3
  39:	66 0f 55 f3          	andnpd xmm6,xmm3
  3d:	66 0f 55 fb          	andnpd xmm7,xmm3
  41:	66 44 0f 55 c3       	andnpd xmm8,xmm3
  46:	66 0f 38 dc c1       	aesenc xmm0,xmm1

Init:

VZEROALL;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 18.16
- Reference cycles: 20.13
- UOPS_PORT_5: 17.0

⇨ One μop that can only use port '5'

With blocking instructions for ports {'0', '1'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	41 8d 16             	lea    edx,[r14]
  18:	45 8d 06             	lea    r8d,[r14]
  1b:	45 8d 0e             	lea    r9d,[r14]
  1e:	45 8d 16             	lea    r10d,[r14]
  21:	45 8d 1e             	lea    r11d,[r14]
  24:	45 8d 26             	lea    r12d,[r14]
  27:	41 8d 1e             	lea    ebx,[r14]
  2a:	41 8d 0e             	lea    ecx,[r14]
  2d:	41 8d 16             	lea    edx,[r14]
  30:	45 8d 06             	lea    r8d,[r14]
  33:	45 8d 0e             	lea    r9d,[r14]
  36:	45 8d 16             	lea    r10d,[r14]
  39:	45 8d 1e             	lea    r11d,[r14]
  3c:	45 8d 26             	lea    r12d,[r14]
  3f:	41 8d 1e             	lea    ebx,[r14]
  42:	41 8d 0e             	lea    ecx,[r14]
  45:	41 8d 16             	lea    edx,[r14]
  48:	45 8d 06             	lea    r8d,[r14]
  4b:	45 8d 0e             	lea    r9d,[r14]
  4e:	45 8d 16             	lea    r10d,[r14]
  51:	45 8d 1e             	lea    r11d,[r14]
  54:	45 8d 26             	lea    r12d,[r14]
  57:	41 8d 1e             	lea    ebx,[r14]
  5a:	41 8d 0e             	lea    ecx,[r14]
  5d:	41 8d 16             	lea    edx,[r14]
  60:	66 0f 38 dc c1       	aesenc xmm0,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 33.0
- Core cycles: 16.19
- Reference cycles: 17.55
- UOPS_PORT_0: 15.97
- UOPS_PORT_1: 15.97

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	41 b0 00             	mov    r8b,0x0
   3:	41 b1 00             	mov    r9b,0x0
   6:	41 b2 00             	mov    r10b,0x0
   9:	41 b3 00             	mov    r11b,0x0
   c:	41 b4 00             	mov    r12b,0x0
   f:	b3 00                	mov    bl,0x0
  11:	b1 00                	mov    cl,0x0
  13:	b2 00                	mov    dl,0x0
  15:	41 b0 00             	mov    r8b,0x0
  18:	41 b1 00             	mov    r9b,0x0
  1b:	41 b2 00             	mov    r10b,0x0
  1e:	41 b3 00             	mov    r11b,0x0
  21:	41 b4 00             	mov    r12b,0x0
  24:	b3 00                	mov    bl,0x0
  26:	b1 00                	mov    cl,0x0
  28:	b2 00                	mov    dl,0x0
  2a:	41 b0 00             	mov    r8b,0x0
  2d:	41 b1 00             	mov    r9b,0x0
  30:	41 b2 00             	mov    r10b,0x0
  33:	41 b3 00             	mov    r11b,0x0
  36:	41 b4 00             	mov    r12b,0x0
  39:	b3 00                	mov    bl,0x0
  3b:	b1 00                	mov    cl,0x0
  3d:	b2 00                	mov    dl,0x0
  3f:	41 b0 00             	mov    r8b,0x0
  42:	41 b1 00             	mov    r9b,0x0
  45:	41 b2 00             	mov    r10b,0x0
  48:	41 b3 00             	mov    r11b,0x0
  4b:	41 b4 00             	mov    r12b,0x0
  4e:	b3 00                	mov    bl,0x0
  50:	b1 00                	mov    cl,0x0
  52:	b2 00                	mov    dl,0x0
  54:	41 b0 00             	mov    r8b,0x0
  57:	41 b1 00             	mov    r9b,0x0
  5a:	41 b2 00             	mov    r10b,0x0
  5d:	41 b3 00             	mov    r11b,0x0
  60:	41 b4 00             	mov    r12b,0x0
  63:	b3 00                	mov    bl,0x0
  65:	b1 00                	mov    cl,0x0
  67:	b2 00                	mov    dl,0x0
  69:	41 b0 00             	mov    r8b,0x0
  6c:	41 b1 00             	mov    r9b,0x0
  6f:	41 b2 00             	mov    r10b,0x0
  72:	41 b3 00             	mov    r11b,0x0
  75:	41 b4 00             	mov    r12b,0x0
  78:	b3 00                	mov    bl,0x0
  7a:	b1 00                	mov    cl,0x0
  7c:	b2 00                	mov    dl,0x0
  7e:	66 0f 38 dc c1       	aesenc xmm0,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 49.0
- Core cycles: 17.7
- Reference cycles: 21.07
- UOPS_PORT_5: 16.15
- UOPS_PORT_0: 17.0
- UOPS_PORT_1: 16.85

⇨ One μop that can only use ports {'0', '1', '5'}